media: platform: stm32: wait end of transmission
It is mandatory to write CEC_CFGR only when CECEN=0. To protect transmission, a check have been added to delayed logical address modification. This patch is necessary tp pass all tests of compliance. Signed-off-by: Yannick Fertré <yannick.fertre@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
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@ -56,6 +56,13 @@
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#define ALL_TX_IT (TXEND | TXBR | TXACKE | TXERR | TXUDR | ARBLST)
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#define ALL_TX_IT (TXEND | TXBR | TXACKE | TXERR | TXUDR | ARBLST)
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#define ALL_RX_IT (RXEND | RXBR | RXACKE | RXOVR)
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#define ALL_RX_IT (RXEND | RXBR | RXACKE | RXOVR)
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/*
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* 400 ms is the time it takes for one 16 byte message to be
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* transferred and 5 is the maximum number of retries. Add
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* another 100 ms as a margin.
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*/
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#define CEC_XFER_TIMEOUT_MS (5 * 400 + 100)
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struct stm32_cec {
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struct stm32_cec {
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struct cec_adapter *adap;
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struct cec_adapter *adap;
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struct device *dev;
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struct device *dev;
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@ -188,7 +195,11 @@ static int stm32_cec_adap_log_addr(struct cec_adapter *adap, u8 logical_addr)
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{
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{
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struct stm32_cec *cec = adap->priv;
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struct stm32_cec *cec = adap->priv;
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u32 oar = (1 << logical_addr) << 16;
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u32 oar = (1 << logical_addr) << 16;
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u32 val;
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/* Poll every 100µs the register CEC_CR to wait end of transmission */
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regmap_read_poll_timeout(cec->regmap, CEC_CR, val, !(val & TXSOM),
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100, CEC_XFER_TIMEOUT_MS * 1000);
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regmap_update_bits(cec->regmap, CEC_CR, CECEN, 0);
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regmap_update_bits(cec->regmap, CEC_CR, CECEN, 0);
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if (logical_addr == CEC_LOG_ADDR_INVALID)
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if (logical_addr == CEC_LOG_ADDR_INVALID)
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