net:add one common config ARCH_WANT_RELAX_ORDER to support relax ordering
Relax ordering(RO) is one feature of 82599 NIC, to enable this feature can enhance the performance for some cpu architecure, such as SPARC and so on. Currently it only supports one special cpu architecture(SPARC) in 82599 driver to enable RO feature, this is not very common for other cpu architecture which really needs RO feature. This patch add one common config CONFIG_ARCH_WANT_RELAX_ORDER to set RO feature, and should define CONFIG_ARCH_WANT_RELAX_ORDER in sparc Kconfig firstly. Signed-off-by: Mao Wenan <maowenan@huawei.com> Reviewed-by: Alexander Duyck <alexander.duyck@gmail.com> Reviewed-by: Alexander Duyck <alexander.h.duyck@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -781,4 +781,7 @@ config VMAP_STACK
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the stack to map directly to the KASAN shadow map using a formula
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the stack to map directly to the KASAN shadow map using a formula
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that is incorrect if the stack is in vmalloc space.
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that is incorrect if the stack is in vmalloc space.
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config ARCH_WANT_RELAX_ORDER
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bool
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source "kernel/gcov/Kconfig"
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source "kernel/gcov/Kconfig"
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@ -44,6 +44,7 @@ config SPARC
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select CPU_NO_EFFICIENT_FFS
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select CPU_NO_EFFICIENT_FFS
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select HAVE_ARCH_HARDENED_USERCOPY
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select HAVE_ARCH_HARDENED_USERCOPY
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select PROVE_LOCKING_SMALL if PROVE_LOCKING
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select PROVE_LOCKING_SMALL if PROVE_LOCKING
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select ARCH_WANT_RELAX_ORDER
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config SPARC32
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config SPARC32
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def_bool !64BIT
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def_bool !64BIT
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@ -350,7 +350,7 @@ s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
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}
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}
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IXGBE_WRITE_FLUSH(hw);
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IXGBE_WRITE_FLUSH(hw);
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#ifndef CONFIG_SPARC
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#ifndef CONFIG_ARCH_WANT_RELAX_ORDER
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/* Disable relaxed ordering */
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/* Disable relaxed ordering */
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for (i = 0; i < hw->mac.max_tx_queues; i++) {
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for (i = 0; i < hw->mac.max_tx_queues; i++) {
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u32 regval;
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u32 regval;
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