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mfd: wm5102: Expose DRE control registers 

Certain use cases may require specific DRE settings so expose the
necessary registers.

Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
This commit is contained in:
Charles Keepax 2013-06-12 17:44:07 +01:00 committed by Mark Brown
parent 6dc6a3f81e
commit 1b4d7d9787
2 changed files with 52 additions and 1 deletions
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9
drivers/mfd/wm5102-tables.c
View File

@ -65,7 +65,8 @@ static const struct reg_default wm5102_revb_patch[] = {
{ 0x418, 0xa080 },
{ 0x420, 0xa080 },
{ 0x428, 0xe000 },
{ 0x443, 0xDC1A },
{ 0x442, 0x3F0A },
{ 0x443, 0xDC1F },
{ 0x4B0, 0x0066 },
{ 0x458, 0x000b },
{ 0x212, 0x0000 },
@ -424,6 +425,9 @@ static const struct reg_default wm5102_reg_default[] = {
{ 0x00000435, 0x0180 }, /* R1077 - DAC Digital Volume 5R */
{ 0x00000436, 0x0081 }, /* R1078 - DAC Volume Limit 5R */
{ 0x00000437, 0x0200 }, /* R1079 - Noise Gate Select 5R */
{ 0x00000440, 0x8FFF }, /* R1088 - DRE Enable */
{ 0x00000442, 0x3F0A }, /* R1090 - DRE Control 2 */
{ 0x00000443, 0xDC1F }, /* R1090 - DRE Control 3 */
{ 0x00000450, 0x0000 }, /* R1104 - DAC AEC Control 1 */
{ 0x00000458, 0x000B }, /* R1112 - Noise Gate Control */
{ 0x00000490, 0x0069 }, /* R1168 - PDM SPK1 CTRL 1 */
@ -1197,6 +1201,9 @@ static bool wm5102_readable_register(struct device *dev, unsigned int reg)
case ARIZONA_DAC_DIGITAL_VOLUME_5R:
case ARIZONA_DAC_VOLUME_LIMIT_5R:
case ARIZONA_NOISE_GATE_SELECT_5R:
case ARIZONA_DRE_ENABLE:
case ARIZONA_DRE_CONTROL_2:
case ARIZONA_DRE_CONTROL_3:
case ARIZONA_DAC_AEC_CONTROL_1:
case ARIZONA_NOISE_GATE_CONTROL:
case ARIZONA_PDM_SPK1_CTRL_1:

44
include/linux/mfd/arizona/registers.h
View File

@ -215,6 +215,9 @@
#define ARIZONA_DAC_DIGITAL_VOLUME_6R 0x43D
#define ARIZONA_DAC_VOLUME_LIMIT_6R 0x43E
#define ARIZONA_NOISE_GATE_SELECT_6R 0x43F
#define ARIZONA_DRE_ENABLE 0x440
#define ARIZONA_DRE_CONTROL_2 0x442
#define ARIZONA_DRE_CONTROL_3 0x443
#define ARIZONA_DAC_AEC_CONTROL_1 0x450
#define ARIZONA_NOISE_GATE_CONTROL 0x458
#define ARIZONA_PDM_SPK1_CTRL_1 0x490
@ -3132,6 +3135,47 @@
#define ARIZONA_OUT6R_NGATE_SRC_SHIFT 0 /* OUT6R_NGATE_SRC - [11:0] */
#define ARIZONA_OUT6R_NGATE_SRC_WIDTH 12 /* OUT6R_NGATE_SRC - [11:0] */
/*
* R1088 (0x440) - DRE Enable
*/
#define ARIZONA_DRE3L_ENA 0x0010 /* DRE3L_ENA */
#define ARIZONA_DRE3L_ENA_MASK 0x0010 /* DRE3L_ENA */
#define ARIZONA_DRE3L_ENA_SHIFT 4 /* DRE3L_ENA */
#define ARIZONA_DRE3L_ENA_WIDTH 1 /* DRE3L_ENA */
#define ARIZONA_DRE2R_ENA 0x0008 /* DRE2R_ENA */
#define ARIZONA_DRE2R_ENA_MASK 0x0008 /* DRE2R_ENA */
#define ARIZONA_DRE2R_ENA_SHIFT 3 /* DRE2R_ENA */
#define ARIZONA_DRE2R_ENA_WIDTH 1 /* DRE2R_ENA */
#define ARIZONA_DRE2L_ENA 0x0004 /* DRE2L_ENA */
#define ARIZONA_DRE2L_ENA_MASK 0x0004 /* DRE2L_ENA */
#define ARIZONA_DRE2L_ENA_SHIFT 2 /* DRE2L_ENA */
#define ARIZONA_DRE2L_ENA_WIDTH 1 /* DRE2L_ENA */
#define ARIZONA_DRE1R_ENA 0x0002 /* DRE1R_ENA */
#define ARIZONA_DRE1R_ENA_MASK 0x0002 /* DRE1R_ENA */
#define ARIZONA_DRE1R_ENA_SHIFT 1 /* DRE1R_ENA */
#define ARIZONA_DRE1R_ENA_WIDTH 1 /* DRE1R_ENA */
#define ARIZONA_DRE1L_ENA 0x0001 /* DRE1L_ENA */
#define ARIZONA_DRE1L_ENA_MASK 0x0001 /* DRE1L_ENA */
#define ARIZONA_DRE1L_ENA_SHIFT 0 /* DRE1L_ENA */
#define ARIZONA_DRE1L_ENA_WIDTH 1 /* DRE1L_ENA */
/*
* R1090 (0x442) - DRE Control 2
*/
#define ARIZONA_DRE_T_LOW_MASK 0x3F00 /* DRE_T_LOW - [13:8] */
#define ARIZONA_DRE_T_LOW_SHIFT 8 /* DRE_T_LOW - [13:8] */
#define ARIZONA_DRE_T_LOW_WIDTH 6 /* DRE_T_LOW - [13:8] */
/*
* R1091 (0x443) - DRE Control 3
*/
#define ARIZONA_DRE_GAIN_SHIFT_MASK 0xC000 /* DRE_GAIN_SHIFT - [15:14] */
#define ARIZONA_DRE_GAIN_SHIFT_SHIFT 14 /* DRE_GAIN_SHIFT - [15:14] */
#define ARIZONA_DRE_GAIN_SHIFT_WIDTH 2 /* DRE_GAIN_SHIFT - [15:14] */
#define ARIZONA_DRE_LOW_LEVEL_ABS_MASK 0x000F /* LOW_LEVEL_ABS - [3:0] */
#define ARIZONA_DRE_LOW_LEVEL_ABS_SHIFT 0 /* LOW_LEVEL_ABS - [3:0] */
#define ARIZONA_DRE_LOW_LEVEL_ABS_WIDTH 4 /* LOW_LEVEL_ABS - [3:0] */
/*
* R1104 (0x450) - DAC AEC Control 1
*/