Pin control fixes for the v4.6 series:
- On Super-H PFC (Renesas) controllers: only use dummies on legacy systems. This fixes a serious ethernet regression on a Renesas board. - Pistachio: Fix errors in the pin table. - Allwinner SunXi: fix the external interrupts to work. - Intel: fix so the high level interrupts start working, and fix a spurious interrupt issue. - Qualcomm ipq4019: fix the number of GPIOs provided (bump to 100), correct register offsets and handle GPIO mode properly. - Revert the revert on the revert so that Xway has a .to_irq() callback again. - Minor fixes to errorpaths and debug info. - A MAINTAINERS update. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJXA6YTAAoJEEEQszewGV1zHWAQAK3xt7WbhVNDENZv+aCvcmYz TrZvTifwwYGxkZ/vDJ1PSZ17cN6B+2UtsUR8tN7MLXcbtpiz1RwXkxc+gtpOZkPI fQAwQHNrziMsIRWi6LrD3zYsZg13ijsEHItKS8fpaO47Vv3PNuq1w25Ui6hX+qbt z535Y2HAeRd/d3PIvodXfGGys9ZolYaPyIAYHTl4rSHXkYGk0UaSIHTm4SBhLxUS 8GWaXg3Rb9J8h3H3qJirmy41wkP1WnG3JrmK++lS2kfkD4kq2Yg+4OoWyXlwBlD0 8mmW2ZjJBzQcUta9q3VsDLfO7FzcAWBdc7UFygRzb8JpxCeO400A79d7ahqhbnN0 ebf461Dz8wSq0W/kEgrQeVPez/ud2pC4n7hqIqyWVhR/bO9h4betOqb6ofNmv6rZ fwggySJHVpKBjF/O+CFtqntSMwksgX17ZLweZOww26Vza5J7khc/fEQxRW597C8m JtWvs8FtvCZCUNEVc4rdan1iNvSe3DIpgiTw8n+zIB8+b5ruS13XMgjaPmen94eO ArzeeDup+mrCRLpjNi2h5YumTC8+ZPuYIF4siGKetpC0s6e7WSS+IUllKfPXE8vt xirhPXLYLSE+HxZgw5ZP3vzXLw0cQPU/HEGuPcUQK6vKbGJuXBAIusT9IbnF2pcY uf8LL/OYpsUKLGQlHW7q =atcX -----END PGP SIGNATURE----- Merge tag 'pinctrl-v4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control fixes from Linus Walleij: "Here is a set of pin control fixes for the v4.6 series. A bit bigger than what I hoped for, but all fixes are confined to drivers, a few of them also targeted to stable. Summary: - On Super-H PFC (Renesas) controllers: only use dummies on legacy systems. This fixes a serious ethernet regression on a Renesas board. - Pistachio: Fix errors in the pin table. - Allwinner SunXi: fix the external interrupts to work. - Intel: fix so the high level interrupts start working, and fix a spurious interrupt issue. - Qualcomm ipq4019: fix the number of GPIOs provided (bump to 100), correct register offsets and handle GPIO mode properly. - Revert the revert on the revert so that Xway has a .to_irq() callback again. - Minor fixes to errorpaths and debug info. - A MAINTAINERS update" * tag 'pinctrl-v4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: Revert "Revert "pinctrl: lantiq: Implement gpio_chip.to_irq"" pinctrl: qcom: ipq4019: fix register offsets pinctrl: qcom: ipq4019: fix the function enum for gpio mode pinctrl: qcom: ipq4019: set ngpios to correct value pinctrl: nomadik: fix pull debug print inversion MAINTAINERS: pinctrl: samsung: Add two new maintainers pinctrl: intel: implement gpio_irq_enable pinctrl: intel: make the high level interrupt working pinctrl: freescale: imx: fix bogus check of of_iomap() return value pinctrl: sunxi: Fix A33 external interrupts not working pinctrl: pistachio: fix mfio84-89 function description and pinmux. pinctrl: sh-pfc: only use dummy states for non-DT platforms
This commit is contained in:
commit
1b5caa3eaa
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@ -134,12 +134,12 @@ mfio80 ddr_debug, mips_trace_data, mips_debug
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mfio81 dreq0, mips_trace_data, eth_debug
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mfio82 dreq1, mips_trace_data, eth_debug
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mfio83 mips_pll_lock, mips_trace_data, usb_debug
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mfio84 sys_pll_lock, mips_trace_data, usb_debug
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mfio85 wifi_pll_lock, mips_trace_data, sdhost_debug
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mfio86 bt_pll_lock, mips_trace_data, sdhost_debug
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mfio87 rpu_v_pll_lock, dreq2, socif_debug
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mfio88 rpu_l_pll_lock, dreq3, socif_debug
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mfio89 audio_pll_lock, dreq4, dreq5
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mfio84 audio_pll_lock, mips_trace_data, usb_debug
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mfio85 rpu_v_pll_lock, mips_trace_data, sdhost_debug
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mfio86 rpu_l_pll_lock, mips_trace_data, sdhost_debug
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mfio87 sys_pll_lock, dreq2, socif_debug
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mfio88 wifi_pll_lock, dreq3, socif_debug
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mfio89 bt_pll_lock, dreq4, dreq5
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tck
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trstn
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tdi
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@ -8712,6 +8712,8 @@ F: drivers/pinctrl/sh-pfc/
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PIN CONTROLLER - SAMSUNG
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M: Tomasz Figa <tomasz.figa@gmail.com>
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M: Krzysztof Kozlowski <k.kozlowski@samsung.com>
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M: Sylwester Nawrocki <s.nawrocki@samsung.com>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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L: linux-samsung-soc@vger.kernel.org (moderated for non-subscribers)
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S: Maintained
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@ -762,19 +762,18 @@ int imx_pinctrl_probe(struct platform_device *pdev,
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if (of_property_read_bool(dev_np, "fsl,input-sel")) {
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np = of_parse_phandle(dev_np, "fsl,input-sel", 0);
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if (np) {
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ipctl->input_sel_base = of_iomap(np, 0);
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if (IS_ERR(ipctl->input_sel_base)) {
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of_node_put(np);
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dev_err(&pdev->dev,
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"iomuxc input select base address not found\n");
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return PTR_ERR(ipctl->input_sel_base);
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}
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} else {
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if (!np) {
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dev_err(&pdev->dev, "iomuxc fsl,input-sel property not found\n");
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return -EINVAL;
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}
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ipctl->input_sel_base = of_iomap(np, 0);
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of_node_put(np);
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if (!ipctl->input_sel_base) {
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dev_err(&pdev->dev,
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"iomuxc input select base address not found\n");
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return -ENOMEM;
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}
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}
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imx_pinctrl_desc.name = dev_name(&pdev->dev);
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@ -665,6 +665,35 @@ static void intel_gpio_irq_ack(struct irq_data *d)
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spin_unlock(&pctrl->lock);
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}
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static void intel_gpio_irq_enable(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
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const struct intel_community *community;
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unsigned pin = irqd_to_hwirq(d);
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unsigned long flags;
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spin_lock_irqsave(&pctrl->lock, flags);
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community = intel_get_community(pctrl, pin);
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if (community) {
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unsigned padno = pin_to_padno(community, pin);
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unsigned gpp_size = community->gpp_size;
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unsigned gpp_offset = padno % gpp_size;
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unsigned gpp = padno / gpp_size;
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u32 value;
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/* Clear interrupt status first to avoid unexpected interrupt */
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writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4);
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value = readl(community->regs + community->ie_offset + gpp * 4);
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value |= BIT(gpp_offset);
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writel(value, community->regs + community->ie_offset + gpp * 4);
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}
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spin_unlock_irqrestore(&pctrl->lock, flags);
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}
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static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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@ -741,8 +770,9 @@ static int intel_gpio_irq_type(struct irq_data *d, unsigned type)
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value |= PADCFG0_RXINV;
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} else if (type & IRQ_TYPE_EDGE_RISING) {
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value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
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} else if (type & IRQ_TYPE_LEVEL_LOW) {
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value |= PADCFG0_RXINV;
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} else if (type & IRQ_TYPE_LEVEL_MASK) {
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if (type & IRQ_TYPE_LEVEL_LOW)
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value |= PADCFG0_RXINV;
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} else {
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value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT;
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}
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@ -852,6 +882,7 @@ static irqreturn_t intel_gpio_irq(int irq, void *data)
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static struct irq_chip intel_gpio_irqchip = {
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.name = "intel-gpio",
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.irq_enable = intel_gpio_irq_enable,
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.irq_ack = intel_gpio_irq_ack,
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.irq_mask = intel_gpio_irq_mask,
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.irq_unmask = intel_gpio_irq_unmask,
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@ -990,7 +990,7 @@ static void nmk_gpio_dbg_show_one(struct seq_file *s,
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int val;
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if (pull)
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pullidx = data_out ? 1 : 2;
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pullidx = data_out ? 2 : 1;
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seq_printf(s, " gpio-%-3d (%-20.20s) in %s %s",
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gpio,
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@ -469,27 +469,27 @@ static const char * const pistachio_mips_pll_lock_groups[] = {
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"mfio83",
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};
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static const char * const pistachio_sys_pll_lock_groups[] = {
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static const char * const pistachio_audio_pll_lock_groups[] = {
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"mfio84",
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};
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static const char * const pistachio_wifi_pll_lock_groups[] = {
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static const char * const pistachio_rpu_v_pll_lock_groups[] = {
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"mfio85",
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};
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static const char * const pistachio_bt_pll_lock_groups[] = {
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static const char * const pistachio_rpu_l_pll_lock_groups[] = {
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"mfio86",
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};
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static const char * const pistachio_rpu_v_pll_lock_groups[] = {
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static const char * const pistachio_sys_pll_lock_groups[] = {
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"mfio87",
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};
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static const char * const pistachio_rpu_l_pll_lock_groups[] = {
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static const char * const pistachio_wifi_pll_lock_groups[] = {
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"mfio88",
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};
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static const char * const pistachio_audio_pll_lock_groups[] = {
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static const char * const pistachio_bt_pll_lock_groups[] = {
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"mfio89",
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};
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@ -559,12 +559,12 @@ enum pistachio_mux_option {
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PISTACHIO_FUNCTION_DREQ4,
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PISTACHIO_FUNCTION_DREQ5,
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PISTACHIO_FUNCTION_MIPS_PLL_LOCK,
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PISTACHIO_FUNCTION_AUDIO_PLL_LOCK,
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PISTACHIO_FUNCTION_RPU_V_PLL_LOCK,
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PISTACHIO_FUNCTION_RPU_L_PLL_LOCK,
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PISTACHIO_FUNCTION_SYS_PLL_LOCK,
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PISTACHIO_FUNCTION_WIFI_PLL_LOCK,
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PISTACHIO_FUNCTION_BT_PLL_LOCK,
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PISTACHIO_FUNCTION_RPU_V_PLL_LOCK,
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PISTACHIO_FUNCTION_RPU_L_PLL_LOCK,
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PISTACHIO_FUNCTION_AUDIO_PLL_LOCK,
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PISTACHIO_FUNCTION_DEBUG_RAW_CCA_IND,
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PISTACHIO_FUNCTION_DEBUG_ED_SEC20_CCA_IND,
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PISTACHIO_FUNCTION_DEBUG_ED_SEC40_CCA_IND,
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@ -620,12 +620,12 @@ static const struct pistachio_function pistachio_functions[] = {
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FUNCTION(dreq4),
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FUNCTION(dreq5),
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FUNCTION(mips_pll_lock),
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FUNCTION(audio_pll_lock),
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FUNCTION(rpu_v_pll_lock),
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FUNCTION(rpu_l_pll_lock),
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FUNCTION(sys_pll_lock),
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FUNCTION(wifi_pll_lock),
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FUNCTION(bt_pll_lock),
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FUNCTION(rpu_v_pll_lock),
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FUNCTION(rpu_l_pll_lock),
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FUNCTION(audio_pll_lock),
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FUNCTION(debug_raw_cca_ind),
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FUNCTION(debug_ed_sec20_cca_ind),
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FUNCTION(debug_ed_sec40_cca_ind),
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@ -1573,6 +1573,22 @@ static int xway_gpio_dir_out(struct gpio_chip *chip, unsigned int pin, int val)
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return 0;
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}
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/*
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* gpiolib gpiod_to_irq callback function.
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* Returns the mapped IRQ (external interrupt) number for a given GPIO pin.
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*/
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static int xway_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
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{
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struct ltq_pinmux_info *info = dev_get_drvdata(chip->parent);
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int i;
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for (i = 0; i < info->num_exin; i++)
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if (info->exin[i] == offset)
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return ltq_eiu_get_irq(i);
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return -1;
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}
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static struct gpio_chip xway_chip = {
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.label = "gpio-xway",
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.direction_input = xway_gpio_dir_in,
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@ -1581,6 +1597,7 @@ static struct gpio_chip xway_chip = {
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.set = xway_gpio_set,
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.request = gpiochip_generic_request,
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.free = gpiochip_generic_free,
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.to_irq = xway_gpio_to_irq,
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.base = -1,
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};
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@ -237,7 +237,7 @@ DECLARE_QCA_GPIO_PINS(99);
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.pins = gpio##id##_pins, \
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.npins = (unsigned)ARRAY_SIZE(gpio##id##_pins), \
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.funcs = (int[]){ \
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qca_mux_NA, /* gpio mode */ \
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qca_mux_gpio, /* gpio mode */ \
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qca_mux_##f1, \
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qca_mux_##f2, \
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qca_mux_##f3, \
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@ -254,11 +254,11 @@ DECLARE_QCA_GPIO_PINS(99);
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qca_mux_##f14 \
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}, \
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.nfuncs = 15, \
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.ctl_reg = 0x1000 + 0x10 * id, \
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.io_reg = 0x1004 + 0x10 * id, \
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.intr_cfg_reg = 0x1008 + 0x10 * id, \
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.intr_status_reg = 0x100c + 0x10 * id, \
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.intr_target_reg = 0x400 + 0x4 * id, \
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.ctl_reg = 0x0 + 0x1000 * id, \
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.io_reg = 0x4 + 0x1000 * id, \
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.intr_cfg_reg = 0x8 + 0x1000 * id, \
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.intr_status_reg = 0xc + 0x1000 * id, \
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.intr_target_reg = 0x8 + 0x1000 * id, \
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.mux_bit = 2, \
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.pull_bit = 0, \
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.drv_bit = 6, \
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@ -414,7 +414,7 @@ static const struct msm_pinctrl_soc_data ipq4019_pinctrl = {
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.nfunctions = ARRAY_SIZE(ipq4019_functions),
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.groups = ipq4019_groups,
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.ngroups = ARRAY_SIZE(ipq4019_groups),
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.ngpios = 70,
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.ngpios = 100,
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};
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static int ipq4019_pinctrl_probe(struct platform_device *pdev)
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|
|
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@ -546,7 +546,9 @@ static int sh_pfc_probe(struct platform_device *pdev)
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return ret;
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}
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pinctrl_provide_dummies();
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/* Enable dummy states for those platforms without pinctrl support */
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if (!of_have_populated_dt())
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pinctrl_provide_dummies();
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ret = sh_pfc_init_ranges(pfc);
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if (ret < 0)
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|
|
|
@ -485,6 +485,7 @@ static const struct sunxi_pinctrl_desc sun8i_a33_pinctrl_data = {
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.pins = sun8i_a33_pins,
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.npins = ARRAY_SIZE(sun8i_a33_pins),
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.irq_banks = 2,
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.irq_bank_base = 1,
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};
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static int sun8i_a33_pinctrl_probe(struct platform_device *pdev)
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|
|
|
@ -579,7 +579,7 @@ static void sunxi_pinctrl_irq_release_resources(struct irq_data *d)
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static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type)
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{
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struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
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u32 reg = sunxi_irq_cfg_reg(d->hwirq);
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u32 reg = sunxi_irq_cfg_reg(d->hwirq, pctl->desc->irq_bank_base);
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u8 index = sunxi_irq_cfg_offset(d->hwirq);
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unsigned long flags;
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u32 regval;
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|
@ -626,7 +626,8 @@ static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type)
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static void sunxi_pinctrl_irq_ack(struct irq_data *d)
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{
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struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
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u32 status_reg = sunxi_irq_status_reg(d->hwirq);
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u32 status_reg = sunxi_irq_status_reg(d->hwirq,
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pctl->desc->irq_bank_base);
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u8 status_idx = sunxi_irq_status_offset(d->hwirq);
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/* Clear the IRQ */
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|
@ -636,7 +637,7 @@ static void sunxi_pinctrl_irq_ack(struct irq_data *d)
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static void sunxi_pinctrl_irq_mask(struct irq_data *d)
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{
|
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struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
|
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u32 reg = sunxi_irq_ctrl_reg(d->hwirq);
|
||||
u32 reg = sunxi_irq_ctrl_reg(d->hwirq, pctl->desc->irq_bank_base);
|
||||
u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
|
||||
unsigned long flags;
|
||||
u32 val;
|
||||
|
@ -653,7 +654,7 @@ static void sunxi_pinctrl_irq_mask(struct irq_data *d)
|
|||
static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
|
||||
{
|
||||
struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
|
||||
u32 reg = sunxi_irq_ctrl_reg(d->hwirq);
|
||||
u32 reg = sunxi_irq_ctrl_reg(d->hwirq, pctl->desc->irq_bank_base);
|
||||
u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
|
||||
unsigned long flags;
|
||||
u32 val;
|
||||
|
@ -745,7 +746,7 @@ static void sunxi_pinctrl_irq_handler(struct irq_desc *desc)
|
|||
if (bank == pctl->desc->irq_banks)
|
||||
return;
|
||||
|
||||
reg = sunxi_irq_status_reg_from_bank(bank);
|
||||
reg = sunxi_irq_status_reg_from_bank(bank, pctl->desc->irq_bank_base);
|
||||
val = readl(pctl->membase + reg);
|
||||
|
||||
if (val) {
|
||||
|
@ -1024,9 +1025,11 @@ int sunxi_pinctrl_init(struct platform_device *pdev,
|
|||
|
||||
for (i = 0; i < pctl->desc->irq_banks; i++) {
|
||||
/* Mask and clear all IRQs before registering a handler */
|
||||
writel(0, pctl->membase + sunxi_irq_ctrl_reg_from_bank(i));
|
||||
writel(0, pctl->membase + sunxi_irq_ctrl_reg_from_bank(i,
|
||||
pctl->desc->irq_bank_base));
|
||||
writel(0xffffffff,
|
||||
pctl->membase + sunxi_irq_status_reg_from_bank(i));
|
||||
pctl->membase + sunxi_irq_status_reg_from_bank(i,
|
||||
pctl->desc->irq_bank_base));
|
||||
|
||||
irq_set_chained_handler_and_data(pctl->irq[i],
|
||||
sunxi_pinctrl_irq_handler,
|
||||
|
|
|
@ -97,6 +97,7 @@ struct sunxi_pinctrl_desc {
|
|||
int npins;
|
||||
unsigned pin_base;
|
||||
unsigned irq_banks;
|
||||
unsigned irq_bank_base;
|
||||
bool irq_read_needs_mux;
|
||||
};
|
||||
|
||||
|
@ -233,12 +234,12 @@ static inline u32 sunxi_pull_offset(u16 pin)
|
|||
return pin_num * PULL_PINS_BITS;
|
||||
}
|
||||
|
||||
static inline u32 sunxi_irq_cfg_reg(u16 irq)
|
||||
static inline u32 sunxi_irq_cfg_reg(u16 irq, unsigned bank_base)
|
||||
{
|
||||
u8 bank = irq / IRQ_PER_BANK;
|
||||
u8 reg = (irq % IRQ_PER_BANK) / IRQ_CFG_IRQ_PER_REG * 0x04;
|
||||
|
||||
return IRQ_CFG_REG + bank * IRQ_MEM_SIZE + reg;
|
||||
return IRQ_CFG_REG + (bank_base + bank) * IRQ_MEM_SIZE + reg;
|
||||
}
|
||||
|
||||
static inline u32 sunxi_irq_cfg_offset(u16 irq)
|
||||
|
@ -247,16 +248,16 @@ static inline u32 sunxi_irq_cfg_offset(u16 irq)
|
|||
return irq_num * IRQ_CFG_IRQ_BITS;
|
||||
}
|
||||
|
||||
static inline u32 sunxi_irq_ctrl_reg_from_bank(u8 bank)
|
||||
static inline u32 sunxi_irq_ctrl_reg_from_bank(u8 bank, unsigned bank_base)
|
||||
{
|
||||
return IRQ_CTRL_REG + bank * IRQ_MEM_SIZE;
|
||||
return IRQ_CTRL_REG + (bank_base + bank) * IRQ_MEM_SIZE;
|
||||
}
|
||||
|
||||
static inline u32 sunxi_irq_ctrl_reg(u16 irq)
|
||||
static inline u32 sunxi_irq_ctrl_reg(u16 irq, unsigned bank_base)
|
||||
{
|
||||
u8 bank = irq / IRQ_PER_BANK;
|
||||
|
||||
return sunxi_irq_ctrl_reg_from_bank(bank);
|
||||
return sunxi_irq_ctrl_reg_from_bank(bank, bank_base);
|
||||
}
|
||||
|
||||
static inline u32 sunxi_irq_ctrl_offset(u16 irq)
|
||||
|
@ -265,16 +266,16 @@ static inline u32 sunxi_irq_ctrl_offset(u16 irq)
|
|||
return irq_num * IRQ_CTRL_IRQ_BITS;
|
||||
}
|
||||
|
||||
static inline u32 sunxi_irq_status_reg_from_bank(u8 bank)
|
||||
static inline u32 sunxi_irq_status_reg_from_bank(u8 bank, unsigned bank_base)
|
||||
{
|
||||
return IRQ_STATUS_REG + bank * IRQ_MEM_SIZE;
|
||||
return IRQ_STATUS_REG + (bank_base + bank) * IRQ_MEM_SIZE;
|
||||
}
|
||||
|
||||
static inline u32 sunxi_irq_status_reg(u16 irq)
|
||||
static inline u32 sunxi_irq_status_reg(u16 irq, unsigned bank_base)
|
||||
{
|
||||
u8 bank = irq / IRQ_PER_BANK;
|
||||
|
||||
return sunxi_irq_status_reg_from_bank(bank);
|
||||
return sunxi_irq_status_reg_from_bank(bank, bank_base);
|
||||
}
|
||||
|
||||
static inline u32 sunxi_irq_status_offset(u16 irq)
|
||||
|
|
Loading…
Reference in New Issue