Staging: cx25821: Fix wrong statement indent in cx25821-core.c
Fix wrong brace placement and statement indent in cx25821-core.c Signed-off-by: Leonid V. Fedorenchik <leonidsbox@gmail.com> Reviewed-By: Valdis Kletnieks <valdis.kletnieks@vt.edu> Reviewed-by: Dan Carpenter <error27@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Leonid V. Fedorenchik
Greg Kroah-Hartman
parent
0fe773df50
commit
1c2b552032
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@ -50,270 +50,270 @@ EXPORT_SYMBOL(cx25821_devlist);
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struct sram_channel cx25821_sram_channels[] = {
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[SRAM_CH00] = {
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.i = SRAM_CH00,
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.name = "VID A",
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.cmds_start = VID_A_DOWN_CMDS,
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.ctrl_start = VID_A_IQ,
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.cdt = VID_A_CDT,
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.fifo_start = VID_A_DOWN_CLUSTER_1,
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.fifo_size = (VID_CLUSTER_SIZE << 2),
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.ptr1_reg = DMA1_PTR1,
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.ptr2_reg = DMA1_PTR2,
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.cnt1_reg = DMA1_CNT1,
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.cnt2_reg = DMA1_CNT2,
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.int_msk = VID_A_INT_MSK,
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.int_stat = VID_A_INT_STAT,
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.int_mstat = VID_A_INT_MSTAT,
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.dma_ctl = VID_DST_A_DMA_CTL,
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.gpcnt_ctl = VID_DST_A_GPCNT_CTL,
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.gpcnt = VID_DST_A_GPCNT,
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.vip_ctl = VID_DST_A_VIP_CTL,
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.pix_frmt = VID_DST_A_PIX_FRMT,
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},
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.i = SRAM_CH00,
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.name = "VID A",
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.cmds_start = VID_A_DOWN_CMDS,
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.ctrl_start = VID_A_IQ,
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.cdt = VID_A_CDT,
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.fifo_start = VID_A_DOWN_CLUSTER_1,
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.fifo_size = (VID_CLUSTER_SIZE << 2),
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.ptr1_reg = DMA1_PTR1,
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.ptr2_reg = DMA1_PTR2,
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.cnt1_reg = DMA1_CNT1,
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.cnt2_reg = DMA1_CNT2,
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.int_msk = VID_A_INT_MSK,
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.int_stat = VID_A_INT_STAT,
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.int_mstat = VID_A_INT_MSTAT,
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.dma_ctl = VID_DST_A_DMA_CTL,
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.gpcnt_ctl = VID_DST_A_GPCNT_CTL,
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.gpcnt = VID_DST_A_GPCNT,
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.vip_ctl = VID_DST_A_VIP_CTL,
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.pix_frmt = VID_DST_A_PIX_FRMT,
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},
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[SRAM_CH01] = {
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.i = SRAM_CH01,
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.name = "VID B",
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.cmds_start = VID_B_DOWN_CMDS,
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.ctrl_start = VID_B_IQ,
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.cdt = VID_B_CDT,
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.fifo_start = VID_B_DOWN_CLUSTER_1,
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.fifo_size = (VID_CLUSTER_SIZE << 2),
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.ptr1_reg = DMA2_PTR1,
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.ptr2_reg = DMA2_PTR2,
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.cnt1_reg = DMA2_CNT1,
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.cnt2_reg = DMA2_CNT2,
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.int_msk = VID_B_INT_MSK,
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.int_stat = VID_B_INT_STAT,
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.int_mstat = VID_B_INT_MSTAT,
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.dma_ctl = VID_DST_B_DMA_CTL,
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.gpcnt_ctl = VID_DST_B_GPCNT_CTL,
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.gpcnt = VID_DST_B_GPCNT,
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.vip_ctl = VID_DST_B_VIP_CTL,
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.pix_frmt = VID_DST_B_PIX_FRMT,
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},
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.i = SRAM_CH01,
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.name = "VID B",
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.cmds_start = VID_B_DOWN_CMDS,
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.ctrl_start = VID_B_IQ,
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.cdt = VID_B_CDT,
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.fifo_start = VID_B_DOWN_CLUSTER_1,
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.fifo_size = (VID_CLUSTER_SIZE << 2),
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.ptr1_reg = DMA2_PTR1,
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.ptr2_reg = DMA2_PTR2,
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.cnt1_reg = DMA2_CNT1,
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.cnt2_reg = DMA2_CNT2,
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.int_msk = VID_B_INT_MSK,
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.int_stat = VID_B_INT_STAT,
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.int_mstat = VID_B_INT_MSTAT,
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.dma_ctl = VID_DST_B_DMA_CTL,
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.gpcnt_ctl = VID_DST_B_GPCNT_CTL,
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.gpcnt = VID_DST_B_GPCNT,
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.vip_ctl = VID_DST_B_VIP_CTL,
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.pix_frmt = VID_DST_B_PIX_FRMT,
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},
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[SRAM_CH02] = {
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.i = SRAM_CH02,
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.name = "VID C",
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.cmds_start = VID_C_DOWN_CMDS,
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.ctrl_start = VID_C_IQ,
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.cdt = VID_C_CDT,
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.fifo_start = VID_C_DOWN_CLUSTER_1,
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.fifo_size = (VID_CLUSTER_SIZE << 2),
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.ptr1_reg = DMA3_PTR1,
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.ptr2_reg = DMA3_PTR2,
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.cnt1_reg = DMA3_CNT1,
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.cnt2_reg = DMA3_CNT2,
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.int_msk = VID_C_INT_MSK,
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.int_stat = VID_C_INT_STAT,
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.int_mstat = VID_C_INT_MSTAT,
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.dma_ctl = VID_DST_C_DMA_CTL,
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.gpcnt_ctl = VID_DST_C_GPCNT_CTL,
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.gpcnt = VID_DST_C_GPCNT,
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.vip_ctl = VID_DST_C_VIP_CTL,
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.pix_frmt = VID_DST_C_PIX_FRMT,
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},
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.i = SRAM_CH02,
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.name = "VID C",
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.cmds_start = VID_C_DOWN_CMDS,
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.ctrl_start = VID_C_IQ,
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.cdt = VID_C_CDT,
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.fifo_start = VID_C_DOWN_CLUSTER_1,
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.fifo_size = (VID_CLUSTER_SIZE << 2),
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.ptr1_reg = DMA3_PTR1,
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.ptr2_reg = DMA3_PTR2,
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.cnt1_reg = DMA3_CNT1,
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.cnt2_reg = DMA3_CNT2,
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.int_msk = VID_C_INT_MSK,
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.int_stat = VID_C_INT_STAT,
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.int_mstat = VID_C_INT_MSTAT,
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.dma_ctl = VID_DST_C_DMA_CTL,
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.gpcnt_ctl = VID_DST_C_GPCNT_CTL,
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.gpcnt = VID_DST_C_GPCNT,
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.vip_ctl = VID_DST_C_VIP_CTL,
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.pix_frmt = VID_DST_C_PIX_FRMT,
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},
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[SRAM_CH03] = {
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.i = SRAM_CH03,
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.name = "VID D",
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.cmds_start = VID_D_DOWN_CMDS,
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.ctrl_start = VID_D_IQ,
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.cdt = VID_D_CDT,
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.fifo_start = VID_D_DOWN_CLUSTER_1,
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.fifo_size = (VID_CLUSTER_SIZE << 2),
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.ptr1_reg = DMA4_PTR1,
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.ptr2_reg = DMA4_PTR2,
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.cnt1_reg = DMA4_CNT1,
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.cnt2_reg = DMA4_CNT2,
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.int_msk = VID_D_INT_MSK,
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.int_stat = VID_D_INT_STAT,
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.int_mstat = VID_D_INT_MSTAT,
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.dma_ctl = VID_DST_D_DMA_CTL,
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.gpcnt_ctl = VID_DST_D_GPCNT_CTL,
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.gpcnt = VID_DST_D_GPCNT,
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.vip_ctl = VID_DST_D_VIP_CTL,
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.pix_frmt = VID_DST_D_PIX_FRMT,
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},
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.i = SRAM_CH03,
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.name = "VID D",
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.cmds_start = VID_D_DOWN_CMDS,
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.ctrl_start = VID_D_IQ,
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.cdt = VID_D_CDT,
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.fifo_start = VID_D_DOWN_CLUSTER_1,
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.fifo_size = (VID_CLUSTER_SIZE << 2),
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.ptr1_reg = DMA4_PTR1,
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.ptr2_reg = DMA4_PTR2,
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.cnt1_reg = DMA4_CNT1,
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.cnt2_reg = DMA4_CNT2,
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.int_msk = VID_D_INT_MSK,
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.int_stat = VID_D_INT_STAT,
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.int_mstat = VID_D_INT_MSTAT,
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.dma_ctl = VID_DST_D_DMA_CTL,
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.gpcnt_ctl = VID_DST_D_GPCNT_CTL,
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.gpcnt = VID_DST_D_GPCNT,
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.vip_ctl = VID_DST_D_VIP_CTL,
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.pix_frmt = VID_DST_D_PIX_FRMT,
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},
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[SRAM_CH04] = {
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.i = SRAM_CH04,
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.name = "VID E",
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.cmds_start = VID_E_DOWN_CMDS,
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.ctrl_start = VID_E_IQ,
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.cdt = VID_E_CDT,
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.fifo_start = VID_E_DOWN_CLUSTER_1,
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.fifo_size = (VID_CLUSTER_SIZE << 2),
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.ptr1_reg = DMA5_PTR1,
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.ptr2_reg = DMA5_PTR2,
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.cnt1_reg = DMA5_CNT1,
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.cnt2_reg = DMA5_CNT2,
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.int_msk = VID_E_INT_MSK,
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.int_stat = VID_E_INT_STAT,
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.int_mstat = VID_E_INT_MSTAT,
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.dma_ctl = VID_DST_E_DMA_CTL,
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.gpcnt_ctl = VID_DST_E_GPCNT_CTL,
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.gpcnt = VID_DST_E_GPCNT,
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.vip_ctl = VID_DST_E_VIP_CTL,
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.pix_frmt = VID_DST_E_PIX_FRMT,
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},
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.i = SRAM_CH04,
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.name = "VID E",
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.cmds_start = VID_E_DOWN_CMDS,
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.ctrl_start = VID_E_IQ,
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.cdt = VID_E_CDT,
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.fifo_start = VID_E_DOWN_CLUSTER_1,
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.fifo_size = (VID_CLUSTER_SIZE << 2),
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.ptr1_reg = DMA5_PTR1,
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.ptr2_reg = DMA5_PTR2,
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.cnt1_reg = DMA5_CNT1,
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.cnt2_reg = DMA5_CNT2,
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.int_msk = VID_E_INT_MSK,
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.int_stat = VID_E_INT_STAT,
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.int_mstat = VID_E_INT_MSTAT,
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.dma_ctl = VID_DST_E_DMA_CTL,
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.gpcnt_ctl = VID_DST_E_GPCNT_CTL,
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.gpcnt = VID_DST_E_GPCNT,
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.vip_ctl = VID_DST_E_VIP_CTL,
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.pix_frmt = VID_DST_E_PIX_FRMT,
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},
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[SRAM_CH05] = {
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.i = SRAM_CH05,
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.name = "VID F",
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.cmds_start = VID_F_DOWN_CMDS,
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.ctrl_start = VID_F_IQ,
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.cdt = VID_F_CDT,
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.fifo_start = VID_F_DOWN_CLUSTER_1,
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.fifo_size = (VID_CLUSTER_SIZE << 2),
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.ptr1_reg = DMA6_PTR1,
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.ptr2_reg = DMA6_PTR2,
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.cnt1_reg = DMA6_CNT1,
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.cnt2_reg = DMA6_CNT2,
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.int_msk = VID_F_INT_MSK,
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.int_stat = VID_F_INT_STAT,
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.int_mstat = VID_F_INT_MSTAT,
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.dma_ctl = VID_DST_F_DMA_CTL,
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.gpcnt_ctl = VID_DST_F_GPCNT_CTL,
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.gpcnt = VID_DST_F_GPCNT,
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.vip_ctl = VID_DST_F_VIP_CTL,
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.pix_frmt = VID_DST_F_PIX_FRMT,
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},
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.i = SRAM_CH05,
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.name = "VID F",
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.cmds_start = VID_F_DOWN_CMDS,
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.ctrl_start = VID_F_IQ,
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.cdt = VID_F_CDT,
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.fifo_start = VID_F_DOWN_CLUSTER_1,
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.fifo_size = (VID_CLUSTER_SIZE << 2),
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.ptr1_reg = DMA6_PTR1,
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.ptr2_reg = DMA6_PTR2,
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.cnt1_reg = DMA6_CNT1,
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.cnt2_reg = DMA6_CNT2,
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.int_msk = VID_F_INT_MSK,
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.int_stat = VID_F_INT_STAT,
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.int_mstat = VID_F_INT_MSTAT,
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.dma_ctl = VID_DST_F_DMA_CTL,
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.gpcnt_ctl = VID_DST_F_GPCNT_CTL,
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.gpcnt = VID_DST_F_GPCNT,
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.vip_ctl = VID_DST_F_VIP_CTL,
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.pix_frmt = VID_DST_F_PIX_FRMT,
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},
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[SRAM_CH06] = {
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.i = SRAM_CH06,
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.name = "VID G",
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.cmds_start = VID_G_DOWN_CMDS,
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.ctrl_start = VID_G_IQ,
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.cdt = VID_G_CDT,
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.fifo_start = VID_G_DOWN_CLUSTER_1,
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.fifo_size = (VID_CLUSTER_SIZE << 2),
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.ptr1_reg = DMA7_PTR1,
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.ptr2_reg = DMA7_PTR2,
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.cnt1_reg = DMA7_CNT1,
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.cnt2_reg = DMA7_CNT2,
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.int_msk = VID_G_INT_MSK,
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.int_stat = VID_G_INT_STAT,
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.int_mstat = VID_G_INT_MSTAT,
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.dma_ctl = VID_DST_G_DMA_CTL,
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.gpcnt_ctl = VID_DST_G_GPCNT_CTL,
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.gpcnt = VID_DST_G_GPCNT,
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.vip_ctl = VID_DST_G_VIP_CTL,
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.pix_frmt = VID_DST_G_PIX_FRMT,
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},
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.i = SRAM_CH06,
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.name = "VID G",
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.cmds_start = VID_G_DOWN_CMDS,
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.ctrl_start = VID_G_IQ,
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.cdt = VID_G_CDT,
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.fifo_start = VID_G_DOWN_CLUSTER_1,
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.fifo_size = (VID_CLUSTER_SIZE << 2),
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.ptr1_reg = DMA7_PTR1,
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.ptr2_reg = DMA7_PTR2,
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.cnt1_reg = DMA7_CNT1,
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.cnt2_reg = DMA7_CNT2,
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.int_msk = VID_G_INT_MSK,
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.int_stat = VID_G_INT_STAT,
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.int_mstat = VID_G_INT_MSTAT,
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.dma_ctl = VID_DST_G_DMA_CTL,
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.gpcnt_ctl = VID_DST_G_GPCNT_CTL,
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.gpcnt = VID_DST_G_GPCNT,
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.vip_ctl = VID_DST_G_VIP_CTL,
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.pix_frmt = VID_DST_G_PIX_FRMT,
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},
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[SRAM_CH07] = {
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.i = SRAM_CH07,
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.name = "VID H",
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.cmds_start = VID_H_DOWN_CMDS,
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.ctrl_start = VID_H_IQ,
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.cdt = VID_H_CDT,
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.fifo_start = VID_H_DOWN_CLUSTER_1,
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.fifo_size = (VID_CLUSTER_SIZE << 2),
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.ptr1_reg = DMA8_PTR1,
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.ptr2_reg = DMA8_PTR2,
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.cnt1_reg = DMA8_CNT1,
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.cnt2_reg = DMA8_CNT2,
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.int_msk = VID_H_INT_MSK,
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.int_stat = VID_H_INT_STAT,
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.int_mstat = VID_H_INT_MSTAT,
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.dma_ctl = VID_DST_H_DMA_CTL,
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.gpcnt_ctl = VID_DST_H_GPCNT_CTL,
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.gpcnt = VID_DST_H_GPCNT,
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.vip_ctl = VID_DST_H_VIP_CTL,
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.pix_frmt = VID_DST_H_PIX_FRMT,
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},
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.i = SRAM_CH07,
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.name = "VID H",
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.cmds_start = VID_H_DOWN_CMDS,
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.ctrl_start = VID_H_IQ,
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.cdt = VID_H_CDT,
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.fifo_start = VID_H_DOWN_CLUSTER_1,
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.fifo_size = (VID_CLUSTER_SIZE << 2),
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.ptr1_reg = DMA8_PTR1,
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.ptr2_reg = DMA8_PTR2,
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.cnt1_reg = DMA8_CNT1,
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.cnt2_reg = DMA8_CNT2,
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.int_msk = VID_H_INT_MSK,
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.int_stat = VID_H_INT_STAT,
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.int_mstat = VID_H_INT_MSTAT,
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.dma_ctl = VID_DST_H_DMA_CTL,
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.gpcnt_ctl = VID_DST_H_GPCNT_CTL,
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.gpcnt = VID_DST_H_GPCNT,
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.vip_ctl = VID_DST_H_VIP_CTL,
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.pix_frmt = VID_DST_H_PIX_FRMT,
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},
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[SRAM_CH08] = {
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.name = "audio from",
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.cmds_start = AUD_A_DOWN_CMDS,
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.ctrl_start = AUD_A_IQ,
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.cdt = AUD_A_CDT,
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.fifo_start = AUD_A_DOWN_CLUSTER_1,
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.fifo_size = AUDIO_CLUSTER_SIZE * 3,
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.ptr1_reg = DMA17_PTR1,
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.ptr2_reg = DMA17_PTR2,
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.cnt1_reg = DMA17_CNT1,
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.cnt2_reg = DMA17_CNT2,
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},
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.name = "audio from",
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.cmds_start = AUD_A_DOWN_CMDS,
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.ctrl_start = AUD_A_IQ,
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.cdt = AUD_A_CDT,
|
||||
.fifo_start = AUD_A_DOWN_CLUSTER_1,
|
||||
.fifo_size = AUDIO_CLUSTER_SIZE * 3,
|
||||
.ptr1_reg = DMA17_PTR1,
|
||||
.ptr2_reg = DMA17_PTR2,
|
||||
.cnt1_reg = DMA17_CNT1,
|
||||
.cnt2_reg = DMA17_CNT2,
|
||||
},
|
||||
|
||||
[SRAM_CH09] = {
|
||||
.i = SRAM_CH09,
|
||||
.name = "VID Upstream I",
|
||||
.cmds_start = VID_I_UP_CMDS,
|
||||
.ctrl_start = VID_I_IQ,
|
||||
.cdt = VID_I_CDT,
|
||||
.fifo_start = VID_I_UP_CLUSTER_1,
|
||||
.fifo_size = (VID_CLUSTER_SIZE << 2),
|
||||
.ptr1_reg = DMA15_PTR1,
|
||||
.ptr2_reg = DMA15_PTR2,
|
||||
.cnt1_reg = DMA15_CNT1,
|
||||
.cnt2_reg = DMA15_CNT2,
|
||||
.int_msk = VID_I_INT_MSK,
|
||||
.int_stat = VID_I_INT_STAT,
|
||||
.int_mstat = VID_I_INT_MSTAT,
|
||||
.dma_ctl = VID_SRC_I_DMA_CTL,
|
||||
.gpcnt_ctl = VID_SRC_I_GPCNT_CTL,
|
||||
.gpcnt = VID_SRC_I_GPCNT,
|
||||
.i = SRAM_CH09,
|
||||
.name = "VID Upstream I",
|
||||
.cmds_start = VID_I_UP_CMDS,
|
||||
.ctrl_start = VID_I_IQ,
|
||||
.cdt = VID_I_CDT,
|
||||
.fifo_start = VID_I_UP_CLUSTER_1,
|
||||
.fifo_size = (VID_CLUSTER_SIZE << 2),
|
||||
.ptr1_reg = DMA15_PTR1,
|
||||
.ptr2_reg = DMA15_PTR2,
|
||||
.cnt1_reg = DMA15_CNT1,
|
||||
.cnt2_reg = DMA15_CNT2,
|
||||
.int_msk = VID_I_INT_MSK,
|
||||
.int_stat = VID_I_INT_STAT,
|
||||
.int_mstat = VID_I_INT_MSTAT,
|
||||
.dma_ctl = VID_SRC_I_DMA_CTL,
|
||||
.gpcnt_ctl = VID_SRC_I_GPCNT_CTL,
|
||||
.gpcnt = VID_SRC_I_GPCNT,
|
||||
|
||||
.vid_fmt_ctl = VID_SRC_I_FMT_CTL,
|
||||
.vid_active_ctl1 = VID_SRC_I_ACTIVE_CTL1,
|
||||
.vid_active_ctl2 = VID_SRC_I_ACTIVE_CTL2,
|
||||
.vid_cdt_size = VID_SRC_I_CDT_SZ,
|
||||
.irq_bit = 8,
|
||||
},
|
||||
.vid_fmt_ctl = VID_SRC_I_FMT_CTL,
|
||||
.vid_active_ctl1 = VID_SRC_I_ACTIVE_CTL1,
|
||||
.vid_active_ctl2 = VID_SRC_I_ACTIVE_CTL2,
|
||||
.vid_cdt_size = VID_SRC_I_CDT_SZ,
|
||||
.irq_bit = 8,
|
||||
},
|
||||
|
||||
[SRAM_CH10] = {
|
||||
.i = SRAM_CH10,
|
||||
.name = "VID Upstream J",
|
||||
.cmds_start = VID_J_UP_CMDS,
|
||||
.ctrl_start = VID_J_IQ,
|
||||
.cdt = VID_J_CDT,
|
||||
.fifo_start = VID_J_UP_CLUSTER_1,
|
||||
.fifo_size = (VID_CLUSTER_SIZE << 2),
|
||||
.ptr1_reg = DMA16_PTR1,
|
||||
.ptr2_reg = DMA16_PTR2,
|
||||
.cnt1_reg = DMA16_CNT1,
|
||||
.cnt2_reg = DMA16_CNT2,
|
||||
.int_msk = VID_J_INT_MSK,
|
||||
.int_stat = VID_J_INT_STAT,
|
||||
.int_mstat = VID_J_INT_MSTAT,
|
||||
.dma_ctl = VID_SRC_J_DMA_CTL,
|
||||
.gpcnt_ctl = VID_SRC_J_GPCNT_CTL,
|
||||
.gpcnt = VID_SRC_J_GPCNT,
|
||||
.i = SRAM_CH10,
|
||||
.name = "VID Upstream J",
|
||||
.cmds_start = VID_J_UP_CMDS,
|
||||
.ctrl_start = VID_J_IQ,
|
||||
.cdt = VID_J_CDT,
|
||||
.fifo_start = VID_J_UP_CLUSTER_1,
|
||||
.fifo_size = (VID_CLUSTER_SIZE << 2),
|
||||
.ptr1_reg = DMA16_PTR1,
|
||||
.ptr2_reg = DMA16_PTR2,
|
||||
.cnt1_reg = DMA16_CNT1,
|
||||
.cnt2_reg = DMA16_CNT2,
|
||||
.int_msk = VID_J_INT_MSK,
|
||||
.int_stat = VID_J_INT_STAT,
|
||||
.int_mstat = VID_J_INT_MSTAT,
|
||||
.dma_ctl = VID_SRC_J_DMA_CTL,
|
||||
.gpcnt_ctl = VID_SRC_J_GPCNT_CTL,
|
||||
.gpcnt = VID_SRC_J_GPCNT,
|
||||
|
||||
.vid_fmt_ctl = VID_SRC_J_FMT_CTL,
|
||||
.vid_active_ctl1 = VID_SRC_J_ACTIVE_CTL1,
|
||||
.vid_active_ctl2 = VID_SRC_J_ACTIVE_CTL2,
|
||||
.vid_cdt_size = VID_SRC_J_CDT_SZ,
|
||||
.irq_bit = 9,
|
||||
},
|
||||
.vid_fmt_ctl = VID_SRC_J_FMT_CTL,
|
||||
.vid_active_ctl1 = VID_SRC_J_ACTIVE_CTL1,
|
||||
.vid_active_ctl2 = VID_SRC_J_ACTIVE_CTL2,
|
||||
.vid_cdt_size = VID_SRC_J_CDT_SZ,
|
||||
.irq_bit = 9,
|
||||
},
|
||||
|
||||
[SRAM_CH11] = {
|
||||
.i = SRAM_CH11,
|
||||
.name = "Audio Upstream Channel B",
|
||||
.cmds_start = AUD_B_UP_CMDS,
|
||||
.ctrl_start = AUD_B_IQ,
|
||||
.cdt = AUD_B_CDT,
|
||||
.fifo_start = AUD_B_UP_CLUSTER_1,
|
||||
.fifo_size = (AUDIO_CLUSTER_SIZE * 3),
|
||||
.ptr1_reg = DMA22_PTR1,
|
||||
.ptr2_reg = DMA22_PTR2,
|
||||
.cnt1_reg = DMA22_CNT1,
|
||||
.cnt2_reg = DMA22_CNT2,
|
||||
.int_msk = AUD_B_INT_MSK,
|
||||
.int_stat = AUD_B_INT_STAT,
|
||||
.int_mstat = AUD_B_INT_MSTAT,
|
||||
.dma_ctl = AUD_INT_DMA_CTL,
|
||||
.gpcnt_ctl = AUD_B_GPCNT_CTL,
|
||||
.gpcnt = AUD_B_GPCNT,
|
||||
.aud_length = AUD_B_LNGTH,
|
||||
.aud_cfg = AUD_B_CFG,
|
||||
.fld_aud_fifo_en = FLD_AUD_SRC_B_FIFO_EN,
|
||||
.fld_aud_risc_en = FLD_AUD_SRC_B_RISC_EN,
|
||||
.irq_bit = 11,
|
||||
},
|
||||
.i = SRAM_CH11,
|
||||
.name = "Audio Upstream Channel B",
|
||||
.cmds_start = AUD_B_UP_CMDS,
|
||||
.ctrl_start = AUD_B_IQ,
|
||||
.cdt = AUD_B_CDT,
|
||||
.fifo_start = AUD_B_UP_CLUSTER_1,
|
||||
.fifo_size = (AUDIO_CLUSTER_SIZE * 3),
|
||||
.ptr1_reg = DMA22_PTR1,
|
||||
.ptr2_reg = DMA22_PTR2,
|
||||
.cnt1_reg = DMA22_CNT1,
|
||||
.cnt2_reg = DMA22_CNT2,
|
||||
.int_msk = AUD_B_INT_MSK,
|
||||
.int_stat = AUD_B_INT_STAT,
|
||||
.int_mstat = AUD_B_INT_MSTAT,
|
||||
.dma_ctl = AUD_INT_DMA_CTL,
|
||||
.gpcnt_ctl = AUD_B_GPCNT_CTL,
|
||||
.gpcnt = AUD_B_GPCNT,
|
||||
.aud_length = AUD_B_LNGTH,
|
||||
.aud_cfg = AUD_B_CFG,
|
||||
.fld_aud_fifo_en = FLD_AUD_SRC_B_FIFO_EN,
|
||||
.fld_aud_risc_en = FLD_AUD_SRC_B_RISC_EN,
|
||||
.irq_bit = 11,
|
||||
},
|
||||
};
|
||||
EXPORT_SYMBOL(cx25821_sram_channels);
|
||||
|
||||
|
|
@ -1475,15 +1475,15 @@ static void __devexit cx25821_finidev(struct pci_dev *pci_dev)
|
|||
|
||||
static DEFINE_PCI_DEVICE_TABLE(cx25821_pci_tbl) = {
|
||||
{
|
||||
/* CX25821 Athena */
|
||||
.vendor = 0x14f1,
|
||||
.device = 0x8210,
|
||||
.subvendor = 0x14f1,
|
||||
.subdevice = 0x0920,
|
||||
},
|
||||
/* CX25821 Athena */
|
||||
.vendor = 0x14f1,
|
||||
.device = 0x8210,
|
||||
.subvendor = 0x14f1,
|
||||
.subdevice = 0x0920,
|
||||
},
|
||||
{
|
||||
/* --- end of list --- */
|
||||
}
|
||||
/* --- end of list --- */
|
||||
}
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(pci, cx25821_pci_tbl);
|
||||
|
|
|
|||
Loading…
Reference in New Issue