Merge branch 'gpio/merge' of git://git.secretlab.ca/git/linux-2.6
* 'gpio/merge' of git://git.secretlab.ca/git/linux-2.6: gpio: Fix DA9052 GPIO build errors. gpio: mpc8xxx: don't allow input-only pins to be output for MPC5121 gpio-ml-ioh: Add the irq_disable/irq_enable hooks for ml-ioh irq chip gpio-ml-ioh: fix a bug in the interrupt handler gpio: pl061: drop extra check for NULL platform_data
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commit
1c5ff0f54d
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@ -22,7 +22,6 @@
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#include <linux/mfd/da9052/da9052.h>
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#include <linux/mfd/da9052/reg.h>
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#include <linux/mfd/da9052/pdata.h>
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#include <linux/mfd/da9052/gpio.h>
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#define DA9052_INPUT 1
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#define DA9052_OUTPUT_OPENDRAIN 2
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@ -43,6 +42,9 @@
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#define DA9052_GPIO_MASK_UPPER_NIBBLE 0xF0
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#define DA9052_GPIO_MASK_LOWER_NIBBLE 0x0F
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#define DA9052_GPIO_NIBBLE_SHIFT 4
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#define DA9052_IRQ_GPI0 16
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#define DA9052_GPIO_ODD_SHIFT 7
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#define DA9052_GPIO_EVEN_SHIFT 3
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struct da9052_gpio {
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struct da9052 *da9052;
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@ -104,33 +106,26 @@ static int da9052_gpio_get(struct gpio_chip *gc, unsigned offset)
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static void da9052_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
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{
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struct da9052_gpio *gpio = to_da9052_gpio(gc);
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unsigned char register_value = 0;
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int ret;
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if (da9052_gpio_port_odd(offset)) {
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if (value) {
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register_value = DA9052_GPIO_ODD_PORT_MODE;
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ret = da9052_reg_update(gpio->da9052, (offset >> 1) +
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DA9052_GPIO_0_1_REG,
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DA9052_GPIO_ODD_PORT_MODE,
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register_value);
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value << DA9052_GPIO_ODD_SHIFT);
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if (ret != 0)
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dev_err(gpio->da9052->dev,
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"Failed to updated gpio odd reg,%d",
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ret);
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}
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} else {
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if (value) {
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register_value = DA9052_GPIO_EVEN_PORT_MODE;
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ret = da9052_reg_update(gpio->da9052, (offset >> 1) +
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DA9052_GPIO_0_1_REG,
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DA9052_GPIO_EVEN_PORT_MODE,
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register_value);
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value << DA9052_GPIO_EVEN_SHIFT);
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if (ret != 0)
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dev_err(gpio->da9052->dev,
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"Failed to updated gpio even reg,%d",
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ret);
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}
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}
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}
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@ -201,9 +196,9 @@ static struct gpio_chip reference_gp __devinitdata = {
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.direction_input = da9052_gpio_direction_input,
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.direction_output = da9052_gpio_direction_output,
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.to_irq = da9052_gpio_to_irq,
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.can_sleep = 1;
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.ngpio = 16;
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.base = -1;
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.can_sleep = 1,
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.ngpio = 16,
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.base = -1,
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};
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static int __devinit da9052_gpio_probe(struct platform_device *pdev)
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@ -332,6 +332,34 @@ static void ioh_irq_mask(struct irq_data *d)
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&chip->reg->regs[chip->ch].imask);
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}
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static void ioh_irq_disable(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct ioh_gpio *chip = gc->private;
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unsigned long flags;
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u32 ien;
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spin_lock_irqsave(&chip->spinlock, flags);
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ien = ioread32(&chip->reg->regs[chip->ch].ien);
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ien &= ~(1 << (d->irq - chip->irq_base));
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iowrite32(ien, &chip->reg->regs[chip->ch].ien);
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spin_unlock_irqrestore(&chip->spinlock, flags);
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}
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static void ioh_irq_enable(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct ioh_gpio *chip = gc->private;
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unsigned long flags;
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u32 ien;
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spin_lock_irqsave(&chip->spinlock, flags);
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ien = ioread32(&chip->reg->regs[chip->ch].ien);
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ien |= 1 << (d->irq - chip->irq_base);
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iowrite32(ien, &chip->reg->regs[chip->ch].ien);
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spin_unlock_irqrestore(&chip->spinlock, flags);
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}
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static irqreturn_t ioh_gpio_handler(int irq, void *dev_id)
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{
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struct ioh_gpio *chip = dev_id;
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@ -339,7 +367,7 @@ static irqreturn_t ioh_gpio_handler(int irq, void *dev_id)
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int i, j;
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int ret = IRQ_NONE;
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for (i = 0; i < 8; i++) {
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for (i = 0; i < 8; i++, chip++) {
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reg_val = ioread32(&chip->reg->regs[i].istatus);
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for (j = 0; j < num_ports[i]; j++) {
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if (reg_val & BIT(j)) {
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@ -370,6 +398,8 @@ static __devinit void ioh_gpio_alloc_generic_chip(struct ioh_gpio *chip,
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ct->chip.irq_mask = ioh_irq_mask;
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ct->chip.irq_unmask = ioh_irq_unmask;
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ct->chip.irq_set_type = ioh_irq_type;
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ct->chip.irq_disable = ioh_irq_disable;
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ct->chip.irq_enable = ioh_irq_enable;
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irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
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IRQ_NOREQUEST | IRQ_NOPROBE, 0);
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@ -132,6 +132,15 @@ static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val
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return 0;
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}
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static int mpc5121_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
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{
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/* GPIO 28..31 are input only on MPC5121 */
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if (gpio >= 28)
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return -EINVAL;
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return mpc8xxx_gpio_dir_out(gc, gpio, val);
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}
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static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
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{
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struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
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@ -340,11 +349,10 @@ static void __init mpc8xxx_add_controller(struct device_node *np)
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mm_gc->save_regs = mpc8xxx_gpio_save_regs;
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gc->ngpio = MPC8XXX_GPIO_PINS;
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gc->direction_input = mpc8xxx_gpio_dir_in;
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gc->direction_output = mpc8xxx_gpio_dir_out;
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if (of_device_is_compatible(np, "fsl,mpc8572-gpio"))
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gc->get = mpc8572_gpio_get;
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else
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gc->get = mpc8xxx_gpio_get;
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gc->direction_output = of_device_is_compatible(np, "fsl,mpc5121-gpio") ?
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mpc5121_gpio_dir_out : mpc8xxx_gpio_dir_out;
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gc->get = of_device_is_compatible(np, "fsl,mpc8572-gpio") ?
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mpc8572_gpio_get : mpc8xxx_gpio_get;
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gc->set = mpc8xxx_gpio_set;
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gc->to_irq = mpc8xxx_gpio_to_irq;
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@ -238,10 +238,6 @@ static int pl061_probe(struct amba_device *dev, const struct amba_id *id)
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int ret, irq, i;
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static DECLARE_BITMAP(init_irq, NR_IRQS);
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pdata = dev->dev.platform_data;
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if (pdata == NULL)
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return -ENODEV;
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chip = kzalloc(sizeof(*chip), GFP_KERNEL);
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if (chip == NULL)
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return -ENOMEM;
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