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i.MX SoC updates for 4.9: 

- Set INT_MEM_CLK_LPM bit to get proper WAIT mode support on i.MX6SX.
    This is a workaround for i.MX6SX WAIT mode hardware issue.
  - Enable cpuidle support with 3 low-power states (WFI, WAIT, POWER-OFF)
    for i.MX6UL.
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Merge tag 'imx-soc-4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/soc

Pull "i.MX SoC updates for 4.9" from Shawn Guo:

 - Set INT_MEM_CLK_LPM bit to get proper WAIT mode support on i.MX6SX.
   This is a workaround for i.MX6SX WAIT mode hardware issue.
 - Enable cpuidle support with 3 low-power states (WFI, WAIT, POWER-OFF)
   for i.MX6UL.

* tag 'imx-soc-4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  ARM: imx: build cpuidle-imx6sx.o for imx6ul
  ARM: imx: add cpuidle support for i.mx6ul
  ARM: imx: enable WAIT mode hardware workaround for imx6sx
  ARM: imx: rename imx6q_set_int_mem_clk_lpm() function
This commit is contained in:
Arnd Bergmann 2016-09-19 16:48:45 +02:00
parent 4a5c99462a d64299daf4
commit 1c90e170fe
6 changed files with 21 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/mach-imx/Makefile
View File

@ -28,6 +28,7 @@ obj-$(CONFIG_SOC_IMX5) += cpuidle-imx5.o
obj-$(CONFIG_SOC_IMX6Q) += cpuidle-imx6q.o
obj-$(CONFIG_SOC_IMX6SL) += cpuidle-imx6sl.o
obj-$(CONFIG_SOC_IMX6SX) += cpuidle-imx6sx.o
obj-$(CONFIG_SOC_IMX6UL) += cpuidle-imx6sx.o
endif
ifdef CONFIG_SND_IMX_SOC

2
arch/arm/mach-imx/common.h
View File

@ -109,7 +109,7 @@ void imx_anatop_init(void);
void imx_anatop_pre_suspend(void);
void imx_anatop_post_resume(void);
int imx6_set_lpm(enum mxc_cpu_pwr_mode mode);
void imx6q_set_int_mem_clk_lpm(bool enable);
void imx6_set_int_mem_clk_lpm(bool enable);
void imx6sl_set_wait_clk(bool enter);
int imx_mmdc_get_ddr_type(void);

2
arch/arm/mach-imx/cpuidle-imx6q.c
View File

@ -85,7 +85,7 @@ EXPORT_SYMBOL_GPL(imx6q_cpuidle_fec_irqs_unused);
int __init imx6q_cpuidle_init(void)
{
/* Set INT_MEM_CLK_LPM bit to get a reliable WAIT mode support */
imx6q_set_int_mem_clk_lpm(true);
imx6_set_int_mem_clk_lpm(true);
return cpuidle_register(&imx6q_cpuidle_driver, NULL);
}

11
arch/arm/mach-imx/cpuidle-imx6sx.c
View File

@ -9,6 +9,7 @@
#include <linux/cpuidle.h>
#include <linux/cpu_pm.h>
#include <linux/module.h>
#include <asm/cacheflush.h>
#include <asm/cpuidle.h>
#include <asm/suspend.h>
@ -17,6 +18,15 @@
static int imx6sx_idle_finish(unsigned long val)
{
/*
* for Cortex-A7 which has an internal L2
* cache, need to flush it before powering
* down ARM platform, since flushing L1 cache
* here again has very small overhead, compared
* to adding conditional code for L2 cache type,
* just call flush_cache_all() is fine.
*/
flush_cache_all();
cpu_do_idle();
return 0;
@ -90,6 +100,7 @@ static struct cpuidle_driver imx6sx_cpuidle_driver = {
int __init imx6sx_cpuidle_init(void)
{
imx6_set_int_mem_clk_lpm(true);
imx6_enable_rbc(false);
/*
* set ARM power up/down timing to the fastest,

3
arch/arm/mach-imx/mach-imx6ul.c
View File

@ -16,6 +16,7 @@
#include <asm/mach/map.h>
#include "common.h"
#include "cpuidle.h"
static void __init imx6ul_enet_clk_init(void)
{
@ -79,6 +80,8 @@ static void __init imx6ul_init_irq(void)
static void __init imx6ul_init_late(void)
{
imx6sx_cpuidle_init();
if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ))
platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0);
}

8
arch/arm/mach-imx/pm-imx6.c
View File

@ -217,7 +217,7 @@ struct imx6_cpu_pm_info {
u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][2]; /* To save offset and value */
} __aligned(8);
void imx6q_set_int_mem_clk_lpm(bool enable)
void imx6_set_int_mem_clk_lpm(bool enable)
{
u32 val = readl_relaxed(ccm_base + CGPR);
@ -367,7 +367,7 @@ static int imx6q_pm_enter(suspend_state_t state)
switch (state) {
case PM_SUSPEND_STANDBY:
imx6_set_lpm(STOP_POWER_ON);
imx6q_set_int_mem_clk_lpm(true);
imx6_set_int_mem_clk_lpm(true);
imx_gpc_pre_suspend(false);
if (cpu_is_imx6sl())
imx6sl_set_wait_clk(true);
@ -380,7 +380,7 @@ static int imx6q_pm_enter(suspend_state_t state)
break;
case PM_SUSPEND_MEM:
imx6_set_lpm(STOP_POWER_OFF);
imx6q_set_int_mem_clk_lpm(false);
imx6_set_int_mem_clk_lpm(false);
imx6q_enable_wb(true);
/*
* For suspend into ocram, asm code already take care of
@ -398,7 +398,7 @@ static int imx6q_pm_enter(suspend_state_t state)
imx_gpc_post_resume();
imx6_enable_rbc(false);
imx6q_enable_wb(false);
imx6q_set_int_mem_clk_lpm(true);
imx6_set_int_mem_clk_lpm(true);
imx6_set_lpm(WAIT_CLOCKED);
break;
default: