drm/amdgpu: Avoid HW reset if guilty job already signaled.
Also reject TDRs if another one already running. v2: Stop all schedulers across device and entire XGMI hive before force signaling HW fences. Avoid passing job_signaled to helper fnctions to keep all the decision making about skipping HW reset in one place. v3: Fix SW sched. hang after non HW reset. sched.hw_rq_count has to be balanced against it's decrement in drm_sched_stop in non HW reset case. v4: rebase v5: Revert v3 as we do it now in sceduler code. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/1555599624-12285-6-git-send-email-andrey.grodzovsky@amd.com
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@ -3334,8 +3334,6 @@ static int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
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if (!ring || !ring->sched.thread)
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continue;
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drm_sched_stop(&ring->sched, &job->base);
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/* after all hw jobs are reset, hw fence is meaningless, so force_completion */
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amdgpu_fence_driver_force_completion(ring);
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}
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@ -3343,6 +3341,7 @@ static int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
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if(job)
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drm_sched_increase_karma(&job->base);
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/* Don't suspend on bare metal if we are not going to HW reset the ASIC */
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if (!amdgpu_sriov_vf(adev)) {
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if (!need_full_reset)
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@ -3480,37 +3479,21 @@ end:
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return r;
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}
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static void amdgpu_device_post_asic_reset(struct amdgpu_device *adev)
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static bool amdgpu_device_lock_adev(struct amdgpu_device *adev, bool trylock)
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{
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int i;
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if (trylock) {
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if (!mutex_trylock(&adev->lock_reset))
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return false;
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} else
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mutex_lock(&adev->lock_reset);
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for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
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struct amdgpu_ring *ring = adev->rings[i];
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if (!ring || !ring->sched.thread)
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continue;
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if (!adev->asic_reset_res)
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drm_sched_resubmit_jobs(&ring->sched);
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drm_sched_start(&ring->sched, !adev->asic_reset_res);
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}
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if (!amdgpu_device_has_dc_support(adev)) {
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drm_helper_resume_force_mode(adev->ddev);
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}
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adev->asic_reset_res = 0;
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}
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static void amdgpu_device_lock_adev(struct amdgpu_device *adev)
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{
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mutex_lock(&adev->lock_reset);
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atomic_inc(&adev->gpu_reset_counter);
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adev->in_gpu_reset = 1;
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/* Block kfd: SRIOV would do it separately */
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if (!amdgpu_sriov_vf(adev))
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amdgpu_amdkfd_pre_reset(adev);
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return true;
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}
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static void amdgpu_device_unlock_adev(struct amdgpu_device *adev)
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@ -3538,40 +3521,42 @@ static void amdgpu_device_unlock_adev(struct amdgpu_device *adev)
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int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
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struct amdgpu_job *job)
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{
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int r;
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struct amdgpu_hive_info *hive = NULL;
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bool need_full_reset = false;
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struct amdgpu_device *tmp_adev = NULL;
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struct list_head device_list, *device_list_handle = NULL;
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bool need_full_reset, job_signaled;
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struct amdgpu_hive_info *hive = NULL;
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struct amdgpu_device *tmp_adev = NULL;
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int i, r = 0;
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need_full_reset = job_signaled = false;
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INIT_LIST_HEAD(&device_list);
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dev_info(adev->dev, "GPU reset begin!\n");
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hive = amdgpu_get_xgmi_hive(adev, false);
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/*
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* In case of XGMI hive disallow concurrent resets to be triggered
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* by different nodes. No point also since the one node already executing
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* reset will also reset all the other nodes in the hive.
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* Here we trylock to avoid chain of resets executing from
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* either trigger by jobs on different adevs in XGMI hive or jobs on
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* different schedulers for same device while this TO handler is running.
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* We always reset all schedulers for device and all devices for XGMI
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* hive so that should take care of them too.
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*/
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hive = amdgpu_get_xgmi_hive(adev, 0);
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if (hive && adev->gmc.xgmi.num_physical_nodes > 1 &&
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!mutex_trylock(&hive->reset_lock))
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if (hive && !mutex_trylock(&hive->reset_lock)) {
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DRM_INFO("Bailing on TDR for s_job:%llx, hive: %llx as another already in progress",
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job->base.id, hive->hive_id);
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return 0;
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}
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/* Start with adev pre asic reset first for soft reset check.*/
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amdgpu_device_lock_adev(adev);
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r = amdgpu_device_pre_asic_reset(adev,
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job,
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&need_full_reset);
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if (r) {
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/*TODO Should we stop ?*/
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DRM_ERROR("GPU pre asic reset failed with err, %d for drm dev, %s ",
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r, adev->ddev->unique);
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adev->asic_reset_res = r;
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if (!amdgpu_device_lock_adev(adev, !hive)) {
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DRM_INFO("Bailing on TDR for s_job:%llx, as another already in progress",
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job->base.id);
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return 0;
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}
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/* Build list of devices to reset */
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if (need_full_reset && adev->gmc.xgmi.num_physical_nodes > 1) {
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if (adev->gmc.xgmi.num_physical_nodes > 1) {
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if (!hive) {
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amdgpu_device_unlock_adev(adev);
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return -ENODEV;
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@ -3588,13 +3573,56 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
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device_list_handle = &device_list;
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}
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/* block all schedulers and reset given job's ring */
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list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
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for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
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struct amdgpu_ring *ring = tmp_adev->rings[i];
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if (!ring || !ring->sched.thread)
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continue;
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drm_sched_stop(&ring->sched, &job->base);
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}
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}
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/*
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* Must check guilty signal here since after this point all old
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* HW fences are force signaled.
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*
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* job->base holds a reference to parent fence
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*/
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if (job && job->base.s_fence->parent &&
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dma_fence_is_signaled(job->base.s_fence->parent))
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job_signaled = true;
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if (!amdgpu_device_ip_need_full_reset(adev))
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device_list_handle = &device_list;
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if (job_signaled) {
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dev_info(adev->dev, "Guilty job already signaled, skipping HW reset");
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goto skip_hw_reset;
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}
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/* Guilty job will be freed after this*/
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r = amdgpu_device_pre_asic_reset(adev,
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job,
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&need_full_reset);
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if (r) {
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/*TODO Should we stop ?*/
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DRM_ERROR("GPU pre asic reset failed with err, %d for drm dev, %s ",
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r, adev->ddev->unique);
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adev->asic_reset_res = r;
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}
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retry: /* Rest of adevs pre asic reset from XGMI hive. */
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list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
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if (tmp_adev == adev)
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continue;
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amdgpu_device_lock_adev(tmp_adev);
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amdgpu_device_lock_adev(tmp_adev, false);
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r = amdgpu_device_pre_asic_reset(tmp_adev,
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NULL,
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&need_full_reset);
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@ -3618,9 +3646,28 @@ retry: /* Rest of adevs pre asic reset from XGMI hive. */
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goto retry;
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}
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skip_hw_reset:
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/* Post ASIC reset for all devs .*/
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list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) {
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amdgpu_device_post_asic_reset(tmp_adev);
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for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
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struct amdgpu_ring *ring = tmp_adev->rings[i];
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if (!ring || !ring->sched.thread)
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continue;
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/* No point to resubmit jobs if we didn't HW reset*/
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if (!tmp_adev->asic_reset_res && !job_signaled)
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drm_sched_resubmit_jobs(&ring->sched);
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drm_sched_start(&ring->sched, !tmp_adev->asic_reset_res);
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}
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if (!amdgpu_device_has_dc_support(tmp_adev) && !job_signaled) {
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drm_helper_resume_force_mode(tmp_adev->ddev);
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}
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tmp_adev->asic_reset_res = 0;
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if (r) {
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/* bad news, how to tell it to userspace ? */
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@ -3633,7 +3680,7 @@ retry: /* Rest of adevs pre asic reset from XGMI hive. */
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amdgpu_device_unlock_adev(tmp_adev);
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}
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if (hive && adev->gmc.xgmi.num_physical_nodes > 1)
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if (hive)
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mutex_unlock(&hive->reset_lock);
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if (r)
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