[MIPS] Kill duplicated setup_irq() for cp0 timer
Also many plat_timer_setup() can be killed too. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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d527eef5b7
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1d9ef3ecd7
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@ -46,10 +46,3 @@ void __init plat_time_init(void)
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/* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
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/* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
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mips_hpt_frequency = hz;
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mips_hpt_frequency = hz;
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}
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}
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void __init
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plat_timer_setup(struct irqaction *irq)
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{
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/* Enable the timer interrupt */
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setup_irq(7, irq);
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}
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@ -104,12 +104,6 @@ void __init plat_time_init(void)
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mips_hpt_frequency = (bus_frequency * (4 + reg)) / 4 / 2;
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mips_hpt_frequency = (bus_frequency * (4 + reg)) / 4 / 2;
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}
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}
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void __init plat_timer_setup(struct irqaction *irq)
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{
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/* we are using the cpu counter for timer interrupts */
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setup_irq(CPU_IRQ_BASE + 7, irq);
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}
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static void markeins_board_init(void);
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static void markeins_board_init(void);
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extern void markeins_irq_setup(void);
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extern void markeins_irq_setup(void);
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@ -53,11 +53,6 @@ unsigned long bus_clock;
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unsigned int memsize;
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unsigned int memsize;
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unsigned int highmemsize = 0;
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unsigned int highmemsize = 0;
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void __init plat_timer_setup(struct irqaction *irq)
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{
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setup_irq(MIPS_CPU_IRQ_BASE + 7, irq);
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}
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void __init plat_time_init(void)
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void __init plat_time_init(void)
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{
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{
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/* setup mips r4k timer */
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/* setup mips r4k timer */
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@ -86,8 +86,5 @@ void __init plat_timer_setup(struct irqaction *irq)
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#ifdef CONFIG_IRQ_MSP_CIC
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#ifdef CONFIG_IRQ_MSP_CIC
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/* we are using the vpe0 counter for timer interrupts */
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/* we are using the vpe0 counter for timer interrupts */
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setup_irq(MSP_INT_VPE0_TIMER, irq);
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setup_irq(MSP_INT_VPE0_TIMER, irq);
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#else
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/* we are using the mips counter for timer interrupts */
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setup_irq(MSP_INT_TIMER, irq);
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#endif
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#endif
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}
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}
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@ -137,11 +137,6 @@ int rtc_mips_set_time(unsigned long tim)
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return 0;
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return 0;
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}
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}
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void __init plat_timer_setup(struct irqaction *irq)
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{
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setup_irq(7, irq);
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}
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void __init plat_time_init(void)
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void __init plat_time_init(void)
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{
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{
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mips_hpt_frequency = cpu_clock_freq / 2;
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mips_hpt_frequency = cpu_clock_freq / 2;
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@ -121,15 +121,6 @@ void __init plat_time_init(void)
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setup_pit_timer();
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setup_pit_timer();
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}
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}
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/*
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* R4k counter based timer interrupt. Works on RM200-225 and possibly
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* others but not on RM400
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*/
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static void __init sni_cpu_timer_setup(struct irqaction *irq)
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{
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setup_irq(SNI_MIPS_IRQ_CPU_TIMER, irq);
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}
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void __init plat_timer_setup(struct irqaction *irq)
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void __init plat_timer_setup(struct irqaction *irq)
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{
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{
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switch (sni_brd_type) {
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switch (sni_brd_type) {
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@ -139,15 +130,6 @@ void __init plat_timer_setup(struct irqaction *irq)
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case SNI_BRD_MINITOWER:
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case SNI_BRD_MINITOWER:
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sni_a20r_timer_setup(irq);
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sni_a20r_timer_setup(irq);
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break;
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break;
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case SNI_BRD_PCI_TOWER:
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case SNI_BRD_RM200:
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case SNI_BRD_PCI_MTOWER:
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case SNI_BRD_PCI_DESKTOP:
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case SNI_BRD_PCI_TOWER_CPLUS:
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case SNI_BRD_PCI_MTOWER_CPLUS:
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sni_cpu_timer_setup(irq);
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break;
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}
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}
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}
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}
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@ -72,22 +72,6 @@ void __init plat_time_init(void)
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#endif
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#endif
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}
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}
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void __init plat_timer_setup(struct irqaction *irq)
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{
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setup_irq(TX4927_IRQ_CPU_TIMER, irq);
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#ifdef CONFIG_TOSHIBA_RBTX4927
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{
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extern void toshiba_rbtx4927_timer_setup(struct irqaction
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*irq);
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toshiba_rbtx4927_timer_setup(irq);
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}
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#endif
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return;
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}
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#ifdef DEBUG
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#ifdef DEBUG
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void print_cp0(char *key, int num, char *name, u32 val)
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void print_cp0(char *key, int num, char *name, u32 val)
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{
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{
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@ -94,7 +94,6 @@
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#define TOSHIBA_RBTX4927_SETUP_EFWFU ( 1 << 3 )
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#define TOSHIBA_RBTX4927_SETUP_EFWFU ( 1 << 3 )
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#define TOSHIBA_RBTX4927_SETUP_SETUP ( 1 << 4 )
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#define TOSHIBA_RBTX4927_SETUP_SETUP ( 1 << 4 )
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#define TOSHIBA_RBTX4927_SETUP_TIME_INIT ( 1 << 5 )
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#define TOSHIBA_RBTX4927_SETUP_TIME_INIT ( 1 << 5 )
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#define TOSHIBA_RBTX4927_SETUP_TIMER_SETUP ( 1 << 6 )
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#define TOSHIBA_RBTX4927_SETUP_PCIBIOS ( 1 << 7 )
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#define TOSHIBA_RBTX4927_SETUP_PCIBIOS ( 1 << 7 )
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#define TOSHIBA_RBTX4927_SETUP_PCI1 ( 1 << 8 )
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#define TOSHIBA_RBTX4927_SETUP_PCI1 ( 1 << 8 )
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#define TOSHIBA_RBTX4927_SETUP_PCI2 ( 1 << 9 )
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#define TOSHIBA_RBTX4927_SETUP_PCI2 ( 1 << 9 )
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@ -108,7 +107,6 @@ static const u32 toshiba_rbtx4927_setup_debug_flag =
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(TOSHIBA_RBTX4927_SETUP_NONE | TOSHIBA_RBTX4927_SETUP_INFO |
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(TOSHIBA_RBTX4927_SETUP_NONE | TOSHIBA_RBTX4927_SETUP_INFO |
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TOSHIBA_RBTX4927_SETUP_WARN | TOSHIBA_RBTX4927_SETUP_EROR |
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TOSHIBA_RBTX4927_SETUP_WARN | TOSHIBA_RBTX4927_SETUP_EROR |
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TOSHIBA_RBTX4927_SETUP_EFWFU | TOSHIBA_RBTX4927_SETUP_SETUP |
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TOSHIBA_RBTX4927_SETUP_EFWFU | TOSHIBA_RBTX4927_SETUP_SETUP |
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TOSHIBA_RBTX4927_SETUP_TIME_INIT | TOSHIBA_RBTX4927_SETUP_TIMER_SETUP
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| TOSHIBA_RBTX4927_SETUP_PCIBIOS | TOSHIBA_RBTX4927_SETUP_PCI1 |
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| TOSHIBA_RBTX4927_SETUP_PCIBIOS | TOSHIBA_RBTX4927_SETUP_PCI1 |
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TOSHIBA_RBTX4927_SETUP_PCI2 | TOSHIBA_RBTX4927_SETUP_PCI66);
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TOSHIBA_RBTX4927_SETUP_PCI2 | TOSHIBA_RBTX4927_SETUP_PCI66);
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#endif
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#endif
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@ -947,14 +945,6 @@ toshiba_rbtx4927_time_init(void)
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}
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}
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void __init toshiba_rbtx4927_timer_setup(struct irqaction *irq)
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{
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TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIMER_SETUP,
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"-\n");
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TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIMER_SETUP,
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"+\n");
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}
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static int __init toshiba_rbtx4927_rtc_init(void)
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static int __init toshiba_rbtx4927_rtc_init(void)
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{
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{
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static struct resource __initdata res = {
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static struct resource __initdata res = {
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@ -43,8 +43,3 @@ plat_mem_setup(void)
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{
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{
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toshiba_rbtx4938_setup();
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toshiba_rbtx4938_setup();
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}
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}
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void __init plat_timer_setup(struct irqaction *irq)
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{
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setup_irq(TX4938_IRQ_CPU_TIMER, irq);
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}
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@ -48,11 +48,6 @@ void __init plat_time_init(void)
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mips_hpt_frequency = tclock / 4;
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mips_hpt_frequency = tclock / 4;
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}
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}
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void __init plat_timer_setup(struct irqaction *irq)
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{
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setup_irq(TIMER_IRQ, irq);
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}
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void __init plat_mem_setup(void)
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void __init plat_mem_setup(void)
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{
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{
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vr41xx_calculate_clock_frequency();
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vr41xx_calculate_clock_frequency();
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@ -141,8 +141,6 @@ extern unsigned int sni_brd_type;
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#define A20R_PT_TIM0_ACK 0xbc050000
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#define A20R_PT_TIM0_ACK 0xbc050000
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#define A20R_PT_TIM1_ACK 0xbc060000
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#define A20R_PT_TIM1_ACK 0xbc060000
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#define SNI_MIPS_IRQ_CPU_TIMER (MIPS_CPU_IRQ_BASE+7)
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#define SNI_A20R_IRQ_BASE MIPS_CPU_IRQ_BASE
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#define SNI_A20R_IRQ_BASE MIPS_CPU_IRQ_BASE
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#define SNI_A20R_IRQ_TIMER (SNI_A20R_IRQ_BASE+5)
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#define SNI_A20R_IRQ_TIMER (SNI_A20R_IRQ_BASE+5)
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