x86/platform/UV: Clean up the NMI code to match current coding style
Update UV NMI to current coding style. Signed-off-by: Mike Travis <travis@sgi.com> Acked-by: Thomas Gleixner <tglx@linutronix.de> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Russ Anderson <rja@hpe.com> Link: http://lkml.kernel.org/r/20170125163518.419094259@asylum.americas.sgi.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
travis@sgi.com
Ingo Molnar
parent
9ec808a022
commit
1e74016370
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@ -45,8 +45,8 @@
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*
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* Handle system-wide NMI events generated by the global 'power nmi' command.
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*
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* Basic operation is to field the NMI interrupt on each cpu and wait
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* until all cpus have arrived into the nmi handler. If some cpus do not
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* Basic operation is to field the NMI interrupt on each CPU and wait
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* until all CPU's have arrived into the nmi handler. If some CPU's do not
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* make it into the handler, try and force them in with the IPI(NMI) signal.
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*
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* We also have to lessen UV Hub MMR accesses as much as possible as this
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@ -56,7 +56,7 @@
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* To do this we register our primary NMI notifier on the NMI_UNKNOWN
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* chain. This reduces the number of false NMI calls when the perf
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* tools are running which generate an enormous number of NMIs per
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* second (~4M/s for 1024 cpu threads). Our secondary NMI handler is
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* second (~4M/s for 1024 CPU threads). Our secondary NMI handler is
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* very short as it only checks that if it has been "pinged" with the
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* IPI(NMI) signal as mentioned above, and does not read the UV Hub's MMR.
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*
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@ -113,7 +113,7 @@ static int param_get_local64(char *buffer, const struct kernel_param *kp)
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static int param_set_local64(const char *val, const struct kernel_param *kp)
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{
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/* clear on any write */
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/* Clear on any write */
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local64_set((local64_t *)kp->arg, 0);
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return 0;
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}
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@ -322,7 +322,7 @@ static struct init_nmi {
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.data = 0x0, /* ACPI Mode */
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},
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/* clear status */
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/* Clear status: */
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{ /* GPI_INT_STS_GPP_D_0 */
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.offset = 0x104,
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.mask = 0x0,
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@ -344,29 +344,29 @@ static struct init_nmi {
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.data = 0x1, /* Clear Status */
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},
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/* disable interrupts */
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/* Disable interrupts: */
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{ /* GPI_INT_EN_GPP_D_0 */
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.offset = 0x114,
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.mask = 0x1,
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.data = 0x0, /* disable interrupt generation */
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.data = 0x0, /* Disable interrupt generation */
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},
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{ /* GPI_GPE_EN_GPP_D_0 */
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.offset = 0x134,
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.mask = 0x1,
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.data = 0x0, /* disable interrupt generation */
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.data = 0x0, /* Disable interrupt generation */
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},
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{ /* GPI_SMI_EN_GPP_D_0 */
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.offset = 0x154,
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.mask = 0x1,
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.data = 0x0, /* disable interrupt generation */
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.data = 0x0, /* Disable interrupt generation */
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},
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{ /* GPI_NMI_EN_GPP_D_0 */
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.offset = 0x174,
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.mask = 0x1,
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.data = 0x0, /* disable interrupt generation */
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.data = 0x0, /* Disable interrupt generation */
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},
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/* setup GPP_D_0 Pad Config */
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/* Setup GPP_D_0 Pad Config: */
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{ /* PAD_CFG_DW0_GPP_D_0 */
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.offset = 0x4c0,
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.mask = 0xffffffff,
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@ -444,7 +444,7 @@ static int uv_nmi_test_hubless(struct uv_hub_nmi_s *hub_nmi)
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return 0;
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*pstat = STS_GPP_D_0_MASK; /* Is a UV NMI: clear GPP_D_0 status */
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(void)*pstat; /* flush write */
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(void)*pstat; /* Flush write */
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return 1;
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}
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@ -461,8 +461,8 @@ static int uv_test_nmi(struct uv_hub_nmi_s *hub_nmi)
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}
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/*
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* If first cpu in on this hub, set hub_nmi "in_nmi" and "owner" values and
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* return true. If first cpu in on the system, set global "in_nmi" flag.
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* If first CPU in on this hub, set hub_nmi "in_nmi" and "owner" values and
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* return true. If first CPU in on the system, set global "in_nmi" flag.
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*/
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static int uv_set_in_nmi(int cpu, struct uv_hub_nmi_s *hub_nmi)
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{
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@ -496,7 +496,7 @@ static int uv_check_nmi(struct uv_hub_nmi_s *hub_nmi)
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if (raw_spin_trylock(&hub_nmi->nmi_lock)) {
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nmi_detected = uv_test_nmi(hub_nmi);
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/* check flag for UV external NMI */
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/* Check flag for UV external NMI */
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if (nmi_detected > 0) {
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uv_set_in_nmi(cpu, hub_nmi);
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nmi = 1;
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@ -516,7 +516,7 @@ static int uv_check_nmi(struct uv_hub_nmi_s *hub_nmi)
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slave_wait: cpu_relax();
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udelay(uv_nmi_slave_delay);
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/* re-check hub in_nmi flag */
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/* Re-check hub in_nmi flag */
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nmi = atomic_read(&hub_nmi->in_nmi);
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if (nmi)
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break;
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@ -560,7 +560,7 @@ static inline void uv_clear_nmi(int cpu)
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}
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}
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/* Ping non-responding cpus attemping to force them into the NMI handler */
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/* Ping non-responding CPU's attemping to force them into the NMI handler */
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static void uv_nmi_nr_cpus_ping(void)
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{
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int cpu;
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@ -571,7 +571,7 @@ static void uv_nmi_nr_cpus_ping(void)
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apic->send_IPI_mask(uv_nmi_cpu_mask, APIC_DM_NMI);
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}
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/* Clean up flags for cpus that ignored both NMI and ping */
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/* Clean up flags for CPU's that ignored both NMI and ping */
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static void uv_nmi_cleanup_mask(void)
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{
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int cpu;
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@ -583,7 +583,7 @@ static void uv_nmi_cleanup_mask(void)
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}
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}
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/* Loop waiting as cpus enter NMI handler */
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/* Loop waiting as CPU's enter NMI handler */
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static int uv_nmi_wait_cpus(int first)
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{
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int i, j, k, n = num_online_cpus();
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@ -597,7 +597,7 @@ static int uv_nmi_wait_cpus(int first)
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k = n - cpumask_weight(uv_nmi_cpu_mask);
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}
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/* PCH NMI causes only one cpu to respond */
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/* PCH NMI causes only one CPU to respond */
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if (first && uv_pch_intr_now_enabled) {
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cpumask_clear_cpu(cpu, uv_nmi_cpu_mask);
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return n - k - 1;
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@ -618,13 +618,13 @@ static int uv_nmi_wait_cpus(int first)
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k = n;
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break;
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}
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if (last_k != k) { /* abort if no new cpus coming in */
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if (last_k != k) { /* abort if no new CPU's coming in */
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last_k = k;
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waiting = 0;
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} else if (++waiting > uv_nmi_wait_count)
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break;
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/* extend delay if waiting only for cpu 0 */
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/* Extend delay if waiting only for CPU 0: */
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if (waiting && (n - k) == 1 &&
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cpumask_test_cpu(0, uv_nmi_cpu_mask))
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loop_delay *= 100;
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@ -635,29 +635,29 @@ static int uv_nmi_wait_cpus(int first)
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return n - k;
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}
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/* Wait until all slave cpus have entered UV NMI handler */
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/* Wait until all slave CPU's have entered UV NMI handler */
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static void uv_nmi_wait(int master)
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{
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/* indicate this cpu is in */
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/* Indicate this CPU is in: */
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this_cpu_write(uv_cpu_nmi.state, UV_NMI_STATE_IN);
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/* if not the first cpu in (the master), then we are a slave cpu */
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/* If not the first CPU in (the master), then we are a slave CPU */
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if (!master)
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return;
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do {
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/* wait for all other cpus to gather here */
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/* Wait for all other CPU's to gather here */
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if (!uv_nmi_wait_cpus(1))
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break;
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/* if not all made it in, send IPI NMI to them */
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/* If not all made it in, send IPI NMI to them */
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pr_alert("UV: Sending NMI IPI to %d CPUs: %*pbl\n",
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cpumask_weight(uv_nmi_cpu_mask),
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cpumask_pr_args(uv_nmi_cpu_mask));
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uv_nmi_nr_cpus_ping();
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/* if all cpus are in, then done */
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/* If all CPU's are in, then done */
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if (!uv_nmi_wait_cpus(0))
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break;
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@ -709,7 +709,7 @@ static void uv_nmi_dump_state_cpu(int cpu, struct pt_regs *regs)
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this_cpu_write(uv_cpu_nmi.state, UV_NMI_STATE_DUMP_DONE);
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}
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/* Trigger a slave cpu to dump it's state */
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/* Trigger a slave CPU to dump it's state */
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static void uv_nmi_trigger_dump(int cpu)
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{
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int retry = uv_nmi_trigger_delay;
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@ -730,7 +730,7 @@ static void uv_nmi_trigger_dump(int cpu)
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uv_cpu_nmi_per(cpu).state = UV_NMI_STATE_DUMP_DONE;
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}
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/* Wait until all cpus ready to exit */
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/* Wait until all CPU's ready to exit */
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static void uv_nmi_sync_exit(int master)
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{
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atomic_dec(&uv_nmi_cpus_in_nmi);
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@ -760,7 +760,7 @@ static void uv_nmi_action_health(int cpu, struct pt_regs *regs, int master)
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uv_nmi_sync_exit(master);
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}
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/* Walk through cpu list and dump state of each */
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/* Walk through CPU list and dump state of each */
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static void uv_nmi_dump_state(int cpu, struct pt_regs *regs, int master)
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{
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if (master) {
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@ -872,7 +872,7 @@ static void uv_call_kgdb_kdb(int cpu, struct pt_regs *regs, int master)
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if (reason < 0)
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return;
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/* call KGDB NMI handler as MASTER */
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/* Call KGDB NMI handler as MASTER */
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ret = kgdb_nmicallin(cpu, X86_TRAP_NMI, regs, reason,
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&uv_nmi_slave_continue);
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if (ret) {
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@ -880,7 +880,7 @@ static void uv_call_kgdb_kdb(int cpu, struct pt_regs *regs, int master)
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atomic_set(&uv_nmi_slave_continue, SLAVE_EXIT);
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}
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} else {
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/* wait for KGDB signal that it's ready for slaves to enter */
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/* Wait for KGDB signal that it's ready for slaves to enter */
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int sig;
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do {
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@ -888,7 +888,7 @@ static void uv_call_kgdb_kdb(int cpu, struct pt_regs *regs, int master)
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sig = atomic_read(&uv_nmi_slave_continue);
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} while (!sig);
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/* call KGDB as slave */
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/* Call KGDB as slave */
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if (sig == SLAVE_CONTINUE)
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kgdb_nmicallback(cpu, regs);
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}
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@ -932,7 +932,7 @@ int uv_handle_nmi(unsigned int reason, struct pt_regs *regs)
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strncpy(uv_nmi_action, "dump", strlen(uv_nmi_action));
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}
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/* Pause as all cpus enter the NMI handler */
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/* Pause as all CPU's enter the NMI handler */
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uv_nmi_wait(master);
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/* Process actions other than "kdump": */
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@ -972,7 +972,7 @@ int uv_handle_nmi(unsigned int reason, struct pt_regs *regs)
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}
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/*
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* NMI handler for pulling in CPUs when perf events are grabbing our NMI
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* NMI handler for pulling in CPU's when perf events are grabbing our NMI
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*/
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static int uv_handle_nmi_ping(unsigned int reason, struct pt_regs *regs)
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{
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@ -1005,7 +1005,7 @@ void uv_nmi_init(void)
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unsigned int value;
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/*
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* Unmask NMI on all cpus
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* Unmask NMI on all CPU's
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*/
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value = apic_read(APIC_LVT1) | APIC_DM_NMI;
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value &= ~APIC_LVT_MASKED;
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