Merge branches 'clk-qcom-gdsc-warn', 'clk-ingenic', 'clk-qcom-qcs404-reset', 'clk-xgene-limit' and 'clk-meson' into clk-next
* clk-qcom-gdsc-warn: clk: qcom: gdsc: WARN when failing to toggle * clk-ingenic: MIPS: Remove dead code clk: ingenic: Remove unused functions MIPS: jz4740: PM: Let CGU driver suspend clocks and set sleep mode clk: ingenic: Handle setting the Low-Power Mode bit clk: ingenic: Add missing header in cgu.h clk: ingenic/jz4725b: Fix "pll half" divider not read/written properly clk: ingenic/jz4725b: Fix incorrect dividers for main clocks clk: ingenic/jz4770: Fix incorrect dividers for main clocks clk: ingenic/jz4740: Fix incorrect dividers for main clocks clk: ingenic: Add support for divider tables * clk-qcom-qcs404-reset: clk: gcc-qcs404: Add PCIe resets * clk-xgene-limit: clk: xgene: Don't build COMMON_CLK_XGENE by default * clk-meson: clk: meson: g12a: mark fclk_div3 as critical clk: meson: g12a: Add support for G12B CPUB clocks dt-bindings: clk: meson: add g12b periph clock controller bindings clk: meson-g12a: add temperature sensor clocks dt-bindings: clk: g12a-clkc: add Temperature Sensor clock IDs clk: meson: meson8b: add the cts_i958 clock clk: meson: meson8b: add the cts_mclk_i958 clocks clk: meson: meson8b: add the cts_amclk clocks dt-bindings: clock: meson8b: add the audio clocks clk: meson: g12a: add controller register init clk: meson: eeclk: add init regs clk: meson: g12a: add mpll register init sequences clk: meson: mpll: add init callback and regs clk: meson: axg: spread spectrum is on mpll2 clk: meson: gxbb: no spread spectrum on mpll0 clk: meson: mpll: properly handle spread spectrum clk: meson: meson8b: fix a typo in the VPU parent names array variable clk: meson: fix MPLL 50M binding id typo
This commit is contained in:
Stephen Boyd
commit
1f5d580cab
|
|
@ -10,6 +10,7 @@ Required Properties:
|
|||
"amlogic,gxl-clkc" for GXL and GXM SoC,
|
||||
"amlogic,axg-clkc" for AXG SoC.
|
||||
"amlogic,g12a-clkc" for G12A SoC.
|
||||
"amlogic,g12b-clkc" for G12B SoC.
|
||||
- clocks : list of clock phandle, one for each entry clock-names.
|
||||
- clock-names : should contain the following:
|
||||
* "xtal": the platform xtal
|
||||
|
|
|
|||
|
|
@ -1,31 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __ASM_JZ4740_CLOCK_H__
|
||||
#define __ASM_JZ4740_CLOCK_H__
|
||||
|
||||
enum jz4740_wait_mode {
|
||||
JZ4740_WAIT_MODE_IDLE,
|
||||
JZ4740_WAIT_MODE_SLEEP,
|
||||
};
|
||||
|
||||
void jz4740_clock_set_wait_mode(enum jz4740_wait_mode mode);
|
||||
|
||||
void jz4740_clock_suspend(void);
|
||||
void jz4740_clock_resume(void);
|
||||
|
||||
void jz4740_clock_udc_enable_auto_suspend(void);
|
||||
void jz4740_clock_udc_disable_auto_suspend(void);
|
||||
|
||||
#endif
|
||||
|
|
@ -40,8 +40,6 @@
|
|||
|
||||
#include <asm/mach-jz4740/platform.h>
|
||||
|
||||
#include "clock.h"
|
||||
|
||||
/* GPIOs */
|
||||
#define QI_LB60_GPIO_KEYOUT(x) (JZ_GPIO_PORTC(10) + (x))
|
||||
#define QI_LB60_GPIO_KEYIN(x) (JZ_GPIO_PORTD(18) + (x))
|
||||
|
|
|
|||
|
|
@ -30,8 +30,6 @@
|
|||
#include <linux/serial_core.h>
|
||||
#include <linux/serial_8250.h>
|
||||
|
||||
#include "clock.h"
|
||||
|
||||
/* USB Device Controller */
|
||||
struct platform_device jz4740_udc_xceiv_device = {
|
||||
.name = "usb_phy_generic",
|
||||
|
|
|
|||
|
|
@ -18,21 +18,13 @@
|
|||
#include <linux/delay.h>
|
||||
#include <linux/suspend.h>
|
||||
|
||||
#include <asm/mach-jz4740/clock.h>
|
||||
|
||||
static int jz4740_pm_enter(suspend_state_t state)
|
||||
{
|
||||
jz4740_clock_suspend();
|
||||
|
||||
jz4740_clock_set_wait_mode(JZ4740_WAIT_MODE_SLEEP);
|
||||
|
||||
__asm__(".set\tmips3\n\t"
|
||||
"wait\n\t"
|
||||
".set\tmips0");
|
||||
|
||||
jz4740_clock_set_wait_mode(JZ4740_WAIT_MODE_IDLE);
|
||||
|
||||
jz4740_clock_resume();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -22,13 +22,10 @@
|
|||
#include <linux/clockchips.h>
|
||||
#include <linux/sched_clock.h>
|
||||
|
||||
#include <asm/mach-jz4740/clock.h>
|
||||
#include <asm/mach-jz4740/irq.h>
|
||||
#include <asm/mach-jz4740/timer.h>
|
||||
#include <asm/time.h>
|
||||
|
||||
#include "clock.h"
|
||||
|
||||
#define TIMER_CLOCKEVENT 0
|
||||
#define TIMER_CLOCKSOURCE 1
|
||||
|
||||
|
|
|
|||
|
|
@ -215,7 +215,7 @@ config CLK_QORIQ
|
|||
|
||||
config COMMON_CLK_XGENE
|
||||
bool "Clock driver for APM XGene SoC"
|
||||
default y
|
||||
default ARCH_XGENE
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
---help---
|
||||
Sypport for the APM X-Gene SoC reference, PLL, and device clocks.
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
obj-$(CONFIG_INGENIC_CGU_COMMON) += cgu.o
|
||||
obj-$(CONFIG_INGENIC_CGU_COMMON) += cgu.o pm.o
|
||||
obj-$(CONFIG_INGENIC_CGU_JZ4740) += jz4740-cgu.o
|
||||
obj-$(CONFIG_INGENIC_CGU_JZ4725B) += jz4725b-cgu.o
|
||||
obj-$(CONFIG_INGENIC_CGU_JZ4770) += jz4770-cgu.o
|
||||
|
|
|
|||
|
|
@ -384,8 +384,11 @@ ingenic_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
|
|||
div_reg = readl(cgu->base + clk_info->div.reg);
|
||||
div = (div_reg >> clk_info->div.shift) &
|
||||
GENMASK(clk_info->div.bits - 1, 0);
|
||||
div += 1;
|
||||
div *= clk_info->div.div;
|
||||
|
||||
if (clk_info->div.div_table)
|
||||
div = clk_info->div.div_table[div];
|
||||
else
|
||||
div = (div + 1) * clk_info->div.div;
|
||||
|
||||
rate /= div;
|
||||
} else if (clk_info->type & CGU_CLK_FIXDIV) {
|
||||
|
|
@ -395,16 +398,37 @@ ingenic_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
|
|||
return rate;
|
||||
}
|
||||
|
||||
static unsigned int
|
||||
ingenic_clk_calc_hw_div(const struct ingenic_cgu_clk_info *clk_info,
|
||||
unsigned int div)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < (1 << clk_info->div.bits)
|
||||
&& clk_info->div.div_table[i]; i++) {
|
||||
if (clk_info->div.div_table[i] >= div)
|
||||
return i;
|
||||
}
|
||||
|
||||
return i - 1;
|
||||
}
|
||||
|
||||
static unsigned
|
||||
ingenic_clk_calc_div(const struct ingenic_cgu_clk_info *clk_info,
|
||||
unsigned long parent_rate, unsigned long req_rate)
|
||||
{
|
||||
unsigned div;
|
||||
unsigned int div, hw_div;
|
||||
|
||||
/* calculate the divide */
|
||||
div = DIV_ROUND_UP(parent_rate, req_rate);
|
||||
|
||||
/* and impose hardware constraints */
|
||||
if (clk_info->div.div_table) {
|
||||
hw_div = ingenic_clk_calc_hw_div(clk_info, div);
|
||||
|
||||
return clk_info->div.div_table[hw_div];
|
||||
}
|
||||
|
||||
/* Impose hardware constraints */
|
||||
div = min_t(unsigned, div, 1 << clk_info->div.bits);
|
||||
div = max_t(unsigned, div, 1);
|
||||
|
||||
|
|
@ -447,7 +471,7 @@ ingenic_clk_set_rate(struct clk_hw *hw, unsigned long req_rate,
|
|||
const struct ingenic_cgu_clk_info *clk_info;
|
||||
const unsigned timeout = 100;
|
||||
unsigned long rate, flags;
|
||||
unsigned div, i;
|
||||
unsigned int hw_div, div, i;
|
||||
u32 reg, mask;
|
||||
int ret = 0;
|
||||
|
||||
|
|
@ -460,13 +484,18 @@ ingenic_clk_set_rate(struct clk_hw *hw, unsigned long req_rate,
|
|||
if (rate != req_rate)
|
||||
return -EINVAL;
|
||||
|
||||
if (clk_info->div.div_table)
|
||||
hw_div = ingenic_clk_calc_hw_div(clk_info, div);
|
||||
else
|
||||
hw_div = ((div / clk_info->div.div) - 1);
|
||||
|
||||
spin_lock_irqsave(&cgu->lock, flags);
|
||||
reg = readl(cgu->base + clk_info->div.reg);
|
||||
|
||||
/* update the divide */
|
||||
mask = GENMASK(clk_info->div.bits - 1, 0);
|
||||
reg &= ~(mask << clk_info->div.shift);
|
||||
reg |= ((div / clk_info->div.div) - 1) << clk_info->div.shift;
|
||||
reg |= hw_div << clk_info->div.shift;
|
||||
|
||||
/* clear the stop bit */
|
||||
if (clk_info->div.stop_bit != -1)
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@
|
|||
#define __DRIVERS_CLK_INGENIC_CGU_H__
|
||||
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
|
|
@ -88,6 +89,8 @@ struct ingenic_cgu_mux_info {
|
|||
* isn't one
|
||||
* @busy_bit: the index of the busy bit within reg, or -1 if there isn't one
|
||||
* @stop_bit: the index of the stop bit within reg, or -1 if there isn't one
|
||||
* @div_table: optional table to map the value read from the register to the
|
||||
* actual divider value
|
||||
*/
|
||||
struct ingenic_cgu_div_info {
|
||||
unsigned reg;
|
||||
|
|
@ -97,6 +100,7 @@ struct ingenic_cgu_div_info {
|
|||
s8 ce_bit;
|
||||
s8 busy_bit;
|
||||
s8 stop_bit;
|
||||
const u8 *div_table;
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@
|
|||
#include <linux/of.h>
|
||||
#include <dt-bindings/clock/jz4725b-cgu.h>
|
||||
#include "cgu.h"
|
||||
#include "pm.h"
|
||||
|
||||
/* CGU register offsets */
|
||||
#define CGU_REG_CPCCR 0x00
|
||||
|
|
@ -33,6 +34,14 @@ static const s8 pll_od_encoding[4] = {
|
|||
0x0, 0x1, -1, 0x3,
|
||||
};
|
||||
|
||||
static const u8 jz4725b_cgu_cpccr_div_table[] = {
|
||||
1, 2, 3, 4, 6, 8,
|
||||
};
|
||||
|
||||
static const u8 jz4725b_cgu_pll_half_div_table[] = {
|
||||
2, 1,
|
||||
};
|
||||
|
||||
static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = {
|
||||
|
||||
/* External clocks */
|
||||
|
|
@ -66,37 +75,55 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = {
|
|||
[JZ4725B_CLK_PLL_HALF] = {
|
||||
"pll half", CGU_CLK_DIV,
|
||||
.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
|
||||
.div = { CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1 },
|
||||
.div = {
|
||||
CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1,
|
||||
jz4725b_cgu_pll_half_div_table,
|
||||
},
|
||||
},
|
||||
|
||||
[JZ4725B_CLK_CCLK] = {
|
||||
"cclk", CGU_CLK_DIV,
|
||||
.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
|
||||
.div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 },
|
||||
.div = {
|
||||
CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1,
|
||||
jz4725b_cgu_cpccr_div_table,
|
||||
},
|
||||
},
|
||||
|
||||
[JZ4725B_CLK_HCLK] = {
|
||||
"hclk", CGU_CLK_DIV,
|
||||
.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
|
||||
.div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 },
|
||||
.div = {
|
||||
CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1,
|
||||
jz4725b_cgu_cpccr_div_table,
|
||||
},
|
||||
},
|
||||
|
||||
[JZ4725B_CLK_PCLK] = {
|
||||
"pclk", CGU_CLK_DIV,
|
||||
.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
|
||||
.div = { CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1 },
|
||||
.div = {
|
||||
CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1,
|
||||
jz4725b_cgu_cpccr_div_table,
|
||||
},
|
||||
},
|
||||
|
||||
[JZ4725B_CLK_MCLK] = {
|
||||
"mclk", CGU_CLK_DIV,
|
||||
.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
|
||||
.div = { CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1 },
|
||||
.div = {
|
||||
CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1,
|
||||
jz4725b_cgu_cpccr_div_table,
|
||||
},
|
||||
},
|
||||
|
||||
[JZ4725B_CLK_IPU] = {
|
||||
"ipu", CGU_CLK_DIV | CGU_CLK_GATE,
|
||||
.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
|
||||
.div = { CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1 },
|
||||
.div = {
|
||||
CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1,
|
||||
jz4725b_cgu_cpccr_div_table,
|
||||
},
|
||||
.gate = { CGU_REG_CLKGR, 13 },
|
||||
},
|
||||
|
||||
|
|
@ -227,5 +254,7 @@ static void __init jz4725b_cgu_init(struct device_node *np)
|
|||
retval = ingenic_cgu_register_clocks(cgu);
|
||||
if (retval)
|
||||
pr_err("%s: failed to register CGU Clocks\n", __func__);
|
||||
|
||||
ingenic_cgu_register_syscore_ops(cgu);
|
||||
}
|
||||
CLK_OF_DECLARE(jz4725b_cgu, "ingenic,jz4725b-cgu", jz4725b_cgu_init);
|
||||
|
|
|
|||
|
|
@ -20,8 +20,8 @@
|
|||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
#include <dt-bindings/clock/jz4740-cgu.h>
|
||||
#include <asm/mach-jz4740/clock.h>
|
||||
#include "cgu.h"
|
||||
#include "pm.h"
|
||||
|
||||
/* CGU register offsets */
|
||||
#define CGU_REG_CPCCR 0x00
|
||||
|
|
@ -58,6 +58,10 @@ static const s8 pll_od_encoding[4] = {
|
|||
0x0, 0x1, -1, 0x3,
|
||||
};
|
||||
|
||||
static const u8 jz4740_cgu_cpccr_div_table[] = {
|
||||
1, 2, 3, 4, 6, 8, 12, 16, 24, 32,
|
||||
};
|
||||
|
||||
static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
|
||||
|
||||
/* External clocks */
|
||||
|
|
@ -97,31 +101,46 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
|
|||
[JZ4740_CLK_CCLK] = {
|
||||
"cclk", CGU_CLK_DIV,
|
||||
.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
|
||||
.div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 },
|
||||
.div = {
|
||||
CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1,
|
||||
jz4740_cgu_cpccr_div_table,
|
||||
},
|
||||
},
|
||||
|
||||
[JZ4740_CLK_HCLK] = {
|
||||
"hclk", CGU_CLK_DIV,
|
||||
.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
|
||||
.div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 },
|
||||
.div = {
|
||||
CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1,
|
||||
jz4740_cgu_cpccr_div_table,
|
||||
},
|
||||
},
|
||||
|
||||
[JZ4740_CLK_PCLK] = {
|
||||
"pclk", CGU_CLK_DIV,
|
||||
.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
|
||||
.div = { CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1 },
|
||||
.div = {
|
||||
CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1,
|
||||
jz4740_cgu_cpccr_div_table,
|
||||
},
|
||||
},
|
||||
|
||||
[JZ4740_CLK_MCLK] = {
|
||||
"mclk", CGU_CLK_DIV,
|
||||
.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
|
||||
.div = { CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1 },
|
||||
.div = {
|
||||
CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1,
|
||||
jz4740_cgu_cpccr_div_table,
|
||||
},
|
||||
},
|
||||
|
||||
[JZ4740_CLK_LCD] = {
|
||||
"lcd", CGU_CLK_DIV | CGU_CLK_GATE,
|
||||
.parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
|
||||
.div = { CGU_REG_CPCCR, 16, 1, 5, 22, -1, -1 },
|
||||
.div = {
|
||||
CGU_REG_CPCCR, 16, 1, 5, 22, -1, -1,
|
||||
jz4740_cgu_cpccr_div_table,
|
||||
},
|
||||
.gate = { CGU_REG_CLKGR, 10 },
|
||||
},
|
||||
|
||||
|
|
@ -228,77 +247,7 @@ static void __init jz4740_cgu_init(struct device_node *np)
|
|||
retval = ingenic_cgu_register_clocks(cgu);
|
||||
if (retval)
|
||||
pr_err("%s: failed to register CGU Clocks\n", __func__);
|
||||
|
||||
ingenic_cgu_register_syscore_ops(cgu);
|
||||
}
|
||||
CLK_OF_DECLARE(jz4740_cgu, "ingenic,jz4740-cgu", jz4740_cgu_init);
|
||||
|
||||
void jz4740_clock_set_wait_mode(enum jz4740_wait_mode mode)
|
||||
{
|
||||
uint32_t lcr = readl(cgu->base + CGU_REG_LCR);
|
||||
|
||||
switch (mode) {
|
||||
case JZ4740_WAIT_MODE_IDLE:
|
||||
lcr &= ~LCR_SLEEP;
|
||||
break;
|
||||
|
||||
case JZ4740_WAIT_MODE_SLEEP:
|
||||
lcr |= LCR_SLEEP;
|
||||
break;
|
||||
}
|
||||
|
||||
writel(lcr, cgu->base + CGU_REG_LCR);
|
||||
}
|
||||
|
||||
void jz4740_clock_udc_disable_auto_suspend(void)
|
||||
{
|
||||
uint32_t clkgr = readl(cgu->base + CGU_REG_CLKGR);
|
||||
|
||||
clkgr &= ~CLKGR_UDC;
|
||||
writel(clkgr, cgu->base + CGU_REG_CLKGR);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(jz4740_clock_udc_disable_auto_suspend);
|
||||
|
||||
void jz4740_clock_udc_enable_auto_suspend(void)
|
||||
{
|
||||
uint32_t clkgr = readl(cgu->base + CGU_REG_CLKGR);
|
||||
|
||||
clkgr |= CLKGR_UDC;
|
||||
writel(clkgr, cgu->base + CGU_REG_CLKGR);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(jz4740_clock_udc_enable_auto_suspend);
|
||||
|
||||
#define JZ_CLOCK_GATE_UART0 BIT(0)
|
||||
#define JZ_CLOCK_GATE_TCU BIT(1)
|
||||
#define JZ_CLOCK_GATE_DMAC BIT(12)
|
||||
|
||||
void jz4740_clock_suspend(void)
|
||||
{
|
||||
uint32_t clkgr, cppcr;
|
||||
|
||||
clkgr = readl(cgu->base + CGU_REG_CLKGR);
|
||||
clkgr |= JZ_CLOCK_GATE_TCU | JZ_CLOCK_GATE_DMAC | JZ_CLOCK_GATE_UART0;
|
||||
writel(clkgr, cgu->base + CGU_REG_CLKGR);
|
||||
|
||||
cppcr = readl(cgu->base + CGU_REG_CPPCR);
|
||||
cppcr &= ~BIT(jz4740_cgu_clocks[JZ4740_CLK_PLL].pll.enable_bit);
|
||||
writel(cppcr, cgu->base + CGU_REG_CPPCR);
|
||||
}
|
||||
|
||||
void jz4740_clock_resume(void)
|
||||
{
|
||||
uint32_t clkgr, cppcr, stable;
|
||||
|
||||
cppcr = readl(cgu->base + CGU_REG_CPPCR);
|
||||
cppcr |= BIT(jz4740_cgu_clocks[JZ4740_CLK_PLL].pll.enable_bit);
|
||||
writel(cppcr, cgu->base + CGU_REG_CPPCR);
|
||||
|
||||
stable = BIT(jz4740_cgu_clocks[JZ4740_CLK_PLL].pll.stable_bit);
|
||||
do {
|
||||
cppcr = readl(cgu->base + CGU_REG_CPPCR);
|
||||
} while (!(cppcr & stable));
|
||||
|
||||
clkgr = readl(cgu->base + CGU_REG_CLKGR);
|
||||
clkgr &= ~JZ_CLOCK_GATE_TCU;
|
||||
clkgr &= ~JZ_CLOCK_GATE_DMAC;
|
||||
clkgr &= ~JZ_CLOCK_GATE_UART0;
|
||||
writel(clkgr, cgu->base + CGU_REG_CLKGR);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -9,9 +9,9 @@
|
|||
#include <linux/delay.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/syscore_ops.h>
|
||||
#include <dt-bindings/clock/jz4770-cgu.h>
|
||||
#include "cgu.h"
|
||||
#include "pm.h"
|
||||
|
||||
/*
|
||||
* CPM registers offset address definition
|
||||
|
|
@ -38,9 +38,6 @@
|
|||
#define CGU_REG_MSC2CDR 0xA8
|
||||
#define CGU_REG_BCHCDR 0xAC
|
||||
|
||||
/* bits within the LCR register */
|
||||
#define LCR_LPM BIT(0) /* Low Power Mode */
|
||||
|
||||
/* bits within the OPCR register */
|
||||
#define OPCR_SPENDH BIT(5) /* UHC PHY suspend */
|
||||
|
||||
|
|
@ -87,6 +84,10 @@ static const s8 pll_od_encoding[8] = {
|
|||
0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3,
|
||||
};
|
||||
|
||||
static const u8 jz4770_cgu_cpccr_div_table[] = {
|
||||
1, 2, 3, 4, 6, 8, 12,
|
||||
};
|
||||
|
||||
static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
|
||||
|
||||
/* External clocks */
|
||||
|
|
@ -144,34 +145,52 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
|
|||
[JZ4770_CLK_CCLK] = {
|
||||
"cclk", CGU_CLK_DIV,
|
||||
.parents = { JZ4770_CLK_PLL0, },
|
||||
.div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 },
|
||||
.div = {
|
||||
CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1,
|
||||
jz4770_cgu_cpccr_div_table,
|
||||
},
|
||||
},
|
||||
[JZ4770_CLK_H0CLK] = {
|
||||
"h0clk", CGU_CLK_DIV,
|
||||
.parents = { JZ4770_CLK_PLL0, },
|
||||
.div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 },
|
||||
.div = {
|
||||
CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1,
|
||||
jz4770_cgu_cpccr_div_table,
|
||||
},
|
||||
},
|
||||
[JZ4770_CLK_H1CLK] = {
|
||||
"h1clk", CGU_CLK_DIV | CGU_CLK_GATE,
|
||||
.parents = { JZ4770_CLK_PLL0, },
|
||||
.div = { CGU_REG_CPCCR, 24, 1, 4, 22, -1, -1 },
|
||||
.div = {
|
||||
CGU_REG_CPCCR, 24, 1, 4, 22, -1, -1,
|
||||
jz4770_cgu_cpccr_div_table,
|
||||
},
|
||||
.gate = { CGU_REG_CLKGR1, 7 },
|
||||
},
|
||||
[JZ4770_CLK_H2CLK] = {
|
||||
"h2clk", CGU_CLK_DIV,
|
||||
.parents = { JZ4770_CLK_PLL0, },
|
||||
.div = { CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1 },
|
||||
.div = {
|
||||
CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1,
|
||||
jz4770_cgu_cpccr_div_table,
|
||||
},
|
||||
},
|
||||
[JZ4770_CLK_C1CLK] = {
|
||||
"c1clk", CGU_CLK_DIV | CGU_CLK_GATE,
|
||||
.parents = { JZ4770_CLK_PLL0, },
|
||||
.div = { CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1 },
|
||||
.div = {
|
||||
CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1,
|
||||
jz4770_cgu_cpccr_div_table,
|
||||
},
|
||||
.gate = { CGU_REG_OPCR, 31, true }, // disable CCLK stop on idle
|
||||
},
|
||||
[JZ4770_CLK_PCLK] = {
|
||||
"pclk", CGU_CLK_DIV,
|
||||
.parents = { JZ4770_CLK_PLL0, },
|
||||
.div = { CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1 },
|
||||
.div = {
|
||||
CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1,
|
||||
jz4770_cgu_cpccr_div_table,
|
||||
},
|
||||
},
|
||||
|
||||
/* Those divided clocks can connect to PLL0 or PLL1 */
|
||||
|
|
@ -407,30 +426,6 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
|
|||
},
|
||||
};
|
||||
|
||||
#if IS_ENABLED(CONFIG_PM_SLEEP)
|
||||
static int jz4770_cgu_pm_suspend(void)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
val = readl(cgu->base + CGU_REG_LCR);
|
||||
writel(val | LCR_LPM, cgu->base + CGU_REG_LCR);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void jz4770_cgu_pm_resume(void)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
val = readl(cgu->base + CGU_REG_LCR);
|
||||
writel(val & ~LCR_LPM, cgu->base + CGU_REG_LCR);
|
||||
}
|
||||
|
||||
static struct syscore_ops jz4770_cgu_pm_ops = {
|
||||
.suspend = jz4770_cgu_pm_suspend,
|
||||
.resume = jz4770_cgu_pm_resume,
|
||||
};
|
||||
#endif /* CONFIG_PM_SLEEP */
|
||||
|
||||
static void __init jz4770_cgu_init(struct device_node *np)
|
||||
{
|
||||
int retval;
|
||||
|
|
@ -444,9 +439,7 @@ static void __init jz4770_cgu_init(struct device_node *np)
|
|||
if (retval)
|
||||
pr_err("%s: failed to register CGU Clocks\n", __func__);
|
||||
|
||||
#if IS_ENABLED(CONFIG_PM_SLEEP)
|
||||
register_syscore_ops(&jz4770_cgu_pm_ops);
|
||||
#endif
|
||||
ingenic_cgu_register_syscore_ops(cgu);
|
||||
}
|
||||
|
||||
/* We only probe via devicetree, no need for a platform driver */
|
||||
|
|
|
|||
|
|
@ -21,6 +21,7 @@
|
|||
#include <linux/of.h>
|
||||
#include <dt-bindings/clock/jz4780-cgu.h>
|
||||
#include "cgu.h"
|
||||
#include "pm.h"
|
||||
|
||||
/* CGU register offsets */
|
||||
#define CGU_REG_CLOCKCONTROL 0x00
|
||||
|
|
@ -730,5 +731,7 @@ static void __init jz4780_cgu_init(struct device_node *np)
|
|||
pr_err("%s: failed to register CGU Clocks\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
ingenic_cgu_register_syscore_ops(cgu);
|
||||
}
|
||||
CLK_OF_DECLARE(jz4780_cgu, "ingenic,jz4780-cgu", jz4780_cgu_init);
|
||||
|
|
|
|||
|
|
@ -0,0 +1,45 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2019 Paul Cercueil <paul@crapouillou.net>
|
||||
*/
|
||||
|
||||
#include "cgu.h"
|
||||
#include "pm.h"
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <linux/syscore_ops.h>
|
||||
|
||||
#define CGU_REG_LCR 0x04
|
||||
|
||||
#define LCR_LOW_POWER_MODE BIT(0)
|
||||
|
||||
static void __iomem * __maybe_unused ingenic_cgu_base;
|
||||
|
||||
static int __maybe_unused ingenic_cgu_pm_suspend(void)
|
||||
{
|
||||
u32 val = readl(ingenic_cgu_base + CGU_REG_LCR);
|
||||
|
||||
writel(val | LCR_LOW_POWER_MODE, ingenic_cgu_base + CGU_REG_LCR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __maybe_unused ingenic_cgu_pm_resume(void)
|
||||
{
|
||||
u32 val = readl(ingenic_cgu_base + CGU_REG_LCR);
|
||||
|
||||
writel(val & ~LCR_LOW_POWER_MODE, ingenic_cgu_base + CGU_REG_LCR);
|
||||
}
|
||||
|
||||
static struct syscore_ops __maybe_unused ingenic_cgu_pm_ops = {
|
||||
.suspend = ingenic_cgu_pm_suspend,
|
||||
.resume = ingenic_cgu_pm_resume,
|
||||
};
|
||||
|
||||
void ingenic_cgu_register_syscore_ops(struct ingenic_cgu *cgu)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_PM_SLEEP)) {
|
||||
ingenic_cgu_base = cgu->base;
|
||||
register_syscore_ops(&ingenic_cgu_pm_ops);
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2019 Paul Cercueil <paul@crapouillou.net>
|
||||
*/
|
||||
#ifndef DRIVERS_CLK_INGENIC_PM_H
|
||||
#define DRIVERS_CLK_INGENIC_PM_H
|
||||
|
||||
struct ingenic_cgu;
|
||||
|
||||
void ingenic_cgu_register_syscore_ops(struct ingenic_cgu *cgu);
|
||||
|
||||
#endif /* DRIVERS_CLK_INGENIC_PM_H */
|
||||
|
|
@ -469,11 +469,6 @@ static struct clk_regmap axg_mpll0_div = {
|
|||
.shift = 16,
|
||||
.width = 9,
|
||||
},
|
||||
.ssen = {
|
||||
.reg_off = HHI_MPLL_CNTL,
|
||||
.shift = 25,
|
||||
.width = 1,
|
||||
},
|
||||
.misc = {
|
||||
.reg_off = HHI_PLL_TOP_MISC,
|
||||
.shift = 0,
|
||||
|
|
@ -568,6 +563,11 @@ static struct clk_regmap axg_mpll2_div = {
|
|||
.shift = 16,
|
||||
.width = 9,
|
||||
},
|
||||
.ssen = {
|
||||
.reg_off = HHI_MPLL_CNTL,
|
||||
.shift = 25,
|
||||
.width = 1,
|
||||
},
|
||||
.misc = {
|
||||
.reg_off = HHI_PLL_TOP_MISC,
|
||||
.shift = 2,
|
||||
|
|
|
|||
|
|
@ -115,21 +115,12 @@ static int mpll_set_rate(struct clk_hw *hw,
|
|||
else
|
||||
__acquire(mpll->lock);
|
||||
|
||||
/* Enable and set the fractional part */
|
||||
/* Set the fractional part */
|
||||
meson_parm_write(clk->map, &mpll->sdm, sdm);
|
||||
meson_parm_write(clk->map, &mpll->sdm_en, 1);
|
||||
|
||||
/* Set additional fractional part enable if required */
|
||||
if (MESON_PARM_APPLICABLE(&mpll->ssen))
|
||||
meson_parm_write(clk->map, &mpll->ssen, 1);
|
||||
|
||||
/* Set the integer divider part */
|
||||
meson_parm_write(clk->map, &mpll->n2, n2);
|
||||
|
||||
/* Set the magic misc bit if required */
|
||||
if (MESON_PARM_APPLICABLE(&mpll->misc))
|
||||
meson_parm_write(clk->map, &mpll->misc, 1);
|
||||
|
||||
if (mpll->lock)
|
||||
spin_unlock_irqrestore(mpll->lock, flags);
|
||||
else
|
||||
|
|
@ -138,6 +129,30 @@ static int mpll_set_rate(struct clk_hw *hw,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static void mpll_init(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_regmap *clk = to_clk_regmap(hw);
|
||||
struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk);
|
||||
|
||||
if (mpll->init_count)
|
||||
regmap_multi_reg_write(clk->map, mpll->init_regs,
|
||||
mpll->init_count);
|
||||
|
||||
/* Enable the fractional part */
|
||||
meson_parm_write(clk->map, &mpll->sdm_en, 1);
|
||||
|
||||
/* Set spread spectrum if possible */
|
||||
if (MESON_PARM_APPLICABLE(&mpll->ssen)) {
|
||||
unsigned int ss =
|
||||
mpll->flags & CLK_MESON_MPLL_SPREAD_SPECTRUM ? 1 : 0;
|
||||
meson_parm_write(clk->map, &mpll->ssen, ss);
|
||||
}
|
||||
|
||||
/* Set the magic misc bit if required */
|
||||
if (MESON_PARM_APPLICABLE(&mpll->misc))
|
||||
meson_parm_write(clk->map, &mpll->misc, 1);
|
||||
}
|
||||
|
||||
const struct clk_ops meson_clk_mpll_ro_ops = {
|
||||
.recalc_rate = mpll_recalc_rate,
|
||||
.round_rate = mpll_round_rate,
|
||||
|
|
@ -148,6 +163,7 @@ const struct clk_ops meson_clk_mpll_ops = {
|
|||
.recalc_rate = mpll_recalc_rate,
|
||||
.round_rate = mpll_round_rate,
|
||||
.set_rate = mpll_set_rate,
|
||||
.init = mpll_init,
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(meson_clk_mpll_ops);
|
||||
|
||||
|
|
|
|||
|
|
@ -18,11 +18,14 @@ struct meson_clk_mpll_data {
|
|||
struct parm n2;
|
||||
struct parm ssen;
|
||||
struct parm misc;
|
||||
const struct reg_sequence *init_regs;
|
||||
unsigned int init_count;
|
||||
spinlock_t *lock;
|
||||
u8 flags;
|
||||
};
|
||||
|
||||
#define CLK_MESON_MPLL_ROUND_CLOSEST BIT(0)
|
||||
#define CLK_MESON_MPLL_SPREAD_SPECTRUM BIT(1)
|
||||
|
||||
extern const struct clk_ops meson_clk_mpll_ro_ops;
|
||||
extern const struct clk_ops meson_clk_mpll_ops;
|
||||
|
|
|
|||
|
|
@ -150,6 +150,57 @@ static struct clk_regmap g12a_sys_pll = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap g12b_sys1_pll_dco = {
|
||||
.data = &(struct meson_clk_pll_data){
|
||||
.en = {
|
||||
.reg_off = HHI_SYS1_PLL_CNTL0,
|
||||
.shift = 28,
|
||||
.width = 1,
|
||||
},
|
||||
.m = {
|
||||
.reg_off = HHI_SYS1_PLL_CNTL0,
|
||||
.shift = 0,
|
||||
.width = 8,
|
||||
},
|
||||
.n = {
|
||||
.reg_off = HHI_SYS1_PLL_CNTL0,
|
||||
.shift = 10,
|
||||
.width = 5,
|
||||
},
|
||||
.l = {
|
||||
.reg_off = HHI_SYS1_PLL_CNTL0,
|
||||
.shift = 31,
|
||||
.width = 1,
|
||||
},
|
||||
.rst = {
|
||||
.reg_off = HHI_SYS1_PLL_CNTL0,
|
||||
.shift = 29,
|
||||
.width = 1,
|
||||
},
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "sys1_pll_dco",
|
||||
.ops = &meson_clk_pll_ro_ops,
|
||||
.parent_names = (const char *[]){ IN_PREFIX "xtal" },
|
||||
.num_parents = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap g12b_sys1_pll = {
|
||||
.data = &(struct clk_regmap_div_data){
|
||||
.offset = HHI_SYS1_PLL_CNTL0,
|
||||
.shift = 16,
|
||||
.width = 3,
|
||||
.flags = CLK_DIVIDER_POWER_OF_TWO,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "sys1_pll",
|
||||
.ops = &clk_regmap_divider_ro_ops,
|
||||
.parent_names = (const char *[]){ "sys1_pll_dco" },
|
||||
.num_parents = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap g12a_sys_pll_div16_en = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_SYS_CPU_CLK_CNTL1,
|
||||
|
|
@ -167,6 +218,23 @@ static struct clk_regmap g12a_sys_pll_div16_en = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap g12b_sys1_pll_div16_en = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_SYS_CPUB_CLK_CNTL1,
|
||||
.bit_idx = 24,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "sys1_pll_div16_en",
|
||||
.ops = &clk_regmap_gate_ro_ops,
|
||||
.parent_names = (const char *[]){ "sys1_pll" },
|
||||
.num_parents = 1,
|
||||
/*
|
||||
* This clock is used to debug the sys_pll range
|
||||
* Linux should not change it at runtime
|
||||
*/
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_fixed_factor g12a_sys_pll_div16 = {
|
||||
.mult = 1,
|
||||
.div = 16,
|
||||
|
|
@ -178,6 +246,17 @@ static struct clk_fixed_factor g12a_sys_pll_div16 = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct clk_fixed_factor g12b_sys1_pll_div16 = {
|
||||
.mult = 1,
|
||||
.div = 16,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "sys1_pll_div16",
|
||||
.ops = &clk_fixed_factor_ops,
|
||||
.parent_names = (const char *[]){ "sys1_pll_div16_en" },
|
||||
.num_parents = 1,
|
||||
},
|
||||
};
|
||||
|
||||
/* Datasheet names this field as "premux0" */
|
||||
static struct clk_regmap g12a_cpu_clk_premux0 = {
|
||||
.data = &(struct clk_regmap_mux_data){
|
||||
|
|
@ -306,6 +385,150 @@ static struct clk_regmap g12a_cpu_clk = {
|
|||
},
|
||||
};
|
||||
|
||||
/* Datasheet names this field as "Final_mux_sel" */
|
||||
static struct clk_regmap g12b_cpu_clk = {
|
||||
.data = &(struct clk_regmap_mux_data){
|
||||
.offset = HHI_SYS_CPU_CLK_CNTL0,
|
||||
.mask = 0x1,
|
||||
.shift = 11,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cpu_clk",
|
||||
.ops = &clk_regmap_mux_ro_ops,
|
||||
.parent_names = (const char *[]){ "cpu_clk_dyn",
|
||||
"sys1_pll" },
|
||||
.num_parents = 2,
|
||||
},
|
||||
};
|
||||
|
||||
/* Datasheet names this field as "premux0" */
|
||||
static struct clk_regmap g12b_cpub_clk_premux0 = {
|
||||
.data = &(struct clk_regmap_mux_data){
|
||||
.offset = HHI_SYS_CPUB_CLK_CNTL,
|
||||
.mask = 0x3,
|
||||
.shift = 0,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cpub_clk_dyn0_sel",
|
||||
.ops = &clk_regmap_mux_ro_ops,
|
||||
.parent_names = (const char *[]){ IN_PREFIX "xtal",
|
||||
"fclk_div2",
|
||||
"fclk_div3" },
|
||||
.num_parents = 3,
|
||||
},
|
||||
};
|
||||
|
||||
/* Datasheet names this field as "mux0_divn_tcnt" */
|
||||
static struct clk_regmap g12b_cpub_clk_mux0_div = {
|
||||
.data = &(struct clk_regmap_div_data){
|
||||
.offset = HHI_SYS_CPUB_CLK_CNTL,
|
||||
.shift = 4,
|
||||
.width = 6,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cpub_clk_dyn0_div",
|
||||
.ops = &clk_regmap_divider_ro_ops,
|
||||
.parent_names = (const char *[]){ "cpub_clk_dyn0_sel" },
|
||||
.num_parents = 1,
|
||||
},
|
||||
};
|
||||
|
||||
/* Datasheet names this field as "postmux0" */
|
||||
static struct clk_regmap g12b_cpub_clk_postmux0 = {
|
||||
.data = &(struct clk_regmap_mux_data){
|
||||
.offset = HHI_SYS_CPUB_CLK_CNTL,
|
||||
.mask = 0x1,
|
||||
.shift = 2,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cpub_clk_dyn0",
|
||||
.ops = &clk_regmap_mux_ro_ops,
|
||||
.parent_names = (const char *[]){ "cpub_clk_dyn0_sel",
|
||||
"cpub_clk_dyn0_div" },
|
||||
.num_parents = 2,
|
||||
},
|
||||
};
|
||||
|
||||
/* Datasheet names this field as "premux1" */
|
||||
static struct clk_regmap g12b_cpub_clk_premux1 = {
|
||||
.data = &(struct clk_regmap_mux_data){
|
||||
.offset = HHI_SYS_CPUB_CLK_CNTL,
|
||||
.mask = 0x3,
|
||||
.shift = 16,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cpub_clk_dyn1_sel",
|
||||
.ops = &clk_regmap_mux_ro_ops,
|
||||
.parent_names = (const char *[]){ IN_PREFIX "xtal",
|
||||
"fclk_div2",
|
||||
"fclk_div3" },
|
||||
.num_parents = 3,
|
||||
},
|
||||
};
|
||||
|
||||
/* Datasheet names this field as "Mux1_divn_tcnt" */
|
||||
static struct clk_regmap g12b_cpub_clk_mux1_div = {
|
||||
.data = &(struct clk_regmap_div_data){
|
||||
.offset = HHI_SYS_CPUB_CLK_CNTL,
|
||||
.shift = 20,
|
||||
.width = 6,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cpub_clk_dyn1_div",
|
||||
.ops = &clk_regmap_divider_ro_ops,
|
||||
.parent_names = (const char *[]){ "cpub_clk_dyn1_sel" },
|
||||
.num_parents = 1,
|
||||
},
|
||||
};
|
||||
|
||||
/* Datasheet names this field as "postmux1" */
|
||||
static struct clk_regmap g12b_cpub_clk_postmux1 = {
|
||||
.data = &(struct clk_regmap_mux_data){
|
||||
.offset = HHI_SYS_CPUB_CLK_CNTL,
|
||||
.mask = 0x1,
|
||||
.shift = 18,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cpub_clk_dyn1",
|
||||
.ops = &clk_regmap_mux_ro_ops,
|
||||
.parent_names = (const char *[]){ "cpub_clk_dyn1_sel",
|
||||
"cpub_clk_dyn1_div" },
|
||||
.num_parents = 2,
|
||||
},
|
||||
};
|
||||
|
||||
/* Datasheet names this field as "Final_dyn_mux_sel" */
|
||||
static struct clk_regmap g12b_cpub_clk_dyn = {
|
||||
.data = &(struct clk_regmap_mux_data){
|
||||
.offset = HHI_SYS_CPUB_CLK_CNTL,
|
||||
.mask = 0x1,
|
||||
.shift = 10,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cpub_clk_dyn",
|
||||
.ops = &clk_regmap_mux_ro_ops,
|
||||
.parent_names = (const char *[]){ "cpub_clk_dyn0",
|
||||
"cpub_clk_dyn1" },
|
||||
.num_parents = 2,
|
||||
},
|
||||
};
|
||||
|
||||
/* Datasheet names this field as "Final_mux_sel" */
|
||||
static struct clk_regmap g12b_cpub_clk = {
|
||||
.data = &(struct clk_regmap_mux_data){
|
||||
.offset = HHI_SYS_CPUB_CLK_CNTL,
|
||||
.mask = 0x1,
|
||||
.shift = 11,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cpub_clk",
|
||||
.ops = &clk_regmap_mux_ro_ops,
|
||||
.parent_names = (const char *[]){ "cpub_clk_dyn",
|
||||
"sys_pll" },
|
||||
.num_parents = 2,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap g12a_cpu_clk_div16_en = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_SYS_CPU_CLK_CNTL1,
|
||||
|
|
@ -323,6 +546,23 @@ static struct clk_regmap g12a_cpu_clk_div16_en = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap g12b_cpub_clk_div16_en = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_SYS_CPUB_CLK_CNTL1,
|
||||
.bit_idx = 1,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "cpub_clk_div16_en",
|
||||
.ops = &clk_regmap_gate_ro_ops,
|
||||
.parent_names = (const char *[]){ "cpub_clk" },
|
||||
.num_parents = 1,
|
||||
/*
|
||||
* This clock is used to debug the cpu_clk range
|
||||
* Linux should not change it at runtime
|
||||
*/
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_fixed_factor g12a_cpu_clk_div16 = {
|
||||
.mult = 1,
|
||||
.div = 16,
|
||||
|
|
@ -334,6 +574,17 @@ static struct clk_fixed_factor g12a_cpu_clk_div16 = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct clk_fixed_factor g12b_cpub_clk_div16 = {
|
||||
.mult = 1,
|
||||
.div = 16,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cpub_clk_div16",
|
||||
.ops = &clk_fixed_factor_ops,
|
||||
.parent_names = (const char *[]){ "cpub_clk_div16_en" },
|
||||
.num_parents = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap g12a_cpu_clk_apb_div = {
|
||||
.data = &(struct clk_regmap_div_data){
|
||||
.offset = HHI_SYS_CPU_CLK_CNTL1,
|
||||
|
|
@ -462,6 +713,240 @@ static struct clk_regmap g12a_cpu_clk_trace = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct clk_fixed_factor g12b_cpub_clk_div2 = {
|
||||
.mult = 1,
|
||||
.div = 2,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cpub_clk_div2",
|
||||
.ops = &clk_fixed_factor_ops,
|
||||
.parent_names = (const char *[]){ "cpub_clk" },
|
||||
.num_parents = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_fixed_factor g12b_cpub_clk_div3 = {
|
||||
.mult = 1,
|
||||
.div = 3,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cpub_clk_div3",
|
||||
.ops = &clk_fixed_factor_ops,
|
||||
.parent_names = (const char *[]){ "cpub_clk" },
|
||||
.num_parents = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_fixed_factor g12b_cpub_clk_div4 = {
|
||||
.mult = 1,
|
||||
.div = 4,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cpub_clk_div4",
|
||||
.ops = &clk_fixed_factor_ops,
|
||||
.parent_names = (const char *[]){ "cpub_clk" },
|
||||
.num_parents = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_fixed_factor g12b_cpub_clk_div5 = {
|
||||
.mult = 1,
|
||||
.div = 5,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cpub_clk_div5",
|
||||
.ops = &clk_fixed_factor_ops,
|
||||
.parent_names = (const char *[]){ "cpub_clk" },
|
||||
.num_parents = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_fixed_factor g12b_cpub_clk_div6 = {
|
||||
.mult = 1,
|
||||
.div = 6,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cpub_clk_div6",
|
||||
.ops = &clk_fixed_factor_ops,
|
||||
.parent_names = (const char *[]){ "cpub_clk" },
|
||||
.num_parents = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_fixed_factor g12b_cpub_clk_div7 = {
|
||||
.mult = 1,
|
||||
.div = 7,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cpub_clk_div7",
|
||||
.ops = &clk_fixed_factor_ops,
|
||||
.parent_names = (const char *[]){ "cpub_clk" },
|
||||
.num_parents = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_fixed_factor g12b_cpub_clk_div8 = {
|
||||
.mult = 1,
|
||||
.div = 8,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cpub_clk_div8",
|
||||
.ops = &clk_fixed_factor_ops,
|
||||
.parent_names = (const char *[]){ "cpub_clk" },
|
||||
.num_parents = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static u32 mux_table_cpub[] = { 1, 2, 3, 4, 5, 6, 7 };
|
||||
static struct clk_regmap g12b_cpub_clk_apb_sel = {
|
||||
.data = &(struct clk_regmap_mux_data){
|
||||
.offset = HHI_SYS_CPUB_CLK_CNTL1,
|
||||
.mask = 7,
|
||||
.shift = 3,
|
||||
.table = mux_table_cpub,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cpub_clk_apb_sel",
|
||||
.ops = &clk_regmap_mux_ro_ops,
|
||||
.parent_names = (const char *[]){ "cpub_clk_div2",
|
||||
"cpub_clk_div3",
|
||||
"cpub_clk_div4",
|
||||
"cpub_clk_div5",
|
||||
"cpub_clk_div6",
|
||||
"cpub_clk_div7",
|
||||
"cpub_clk_div8" },
|
||||
.num_parents = 7,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap g12b_cpub_clk_apb = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_SYS_CPUB_CLK_CNTL1,
|
||||
.bit_idx = 16,
|
||||
.flags = CLK_GATE_SET_TO_DISABLE,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "cpub_clk_apb",
|
||||
.ops = &clk_regmap_gate_ro_ops,
|
||||
.parent_names = (const char *[]){ "cpub_clk_apb_sel" },
|
||||
.num_parents = 1,
|
||||
/*
|
||||
* This clock is set by the ROM monitor code,
|
||||
* Linux should not change it at runtime
|
||||
*/
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap g12b_cpub_clk_atb_sel = {
|
||||
.data = &(struct clk_regmap_mux_data){
|
||||
.offset = HHI_SYS_CPUB_CLK_CNTL1,
|
||||
.mask = 7,
|
||||
.shift = 6,
|
||||
.table = mux_table_cpub,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cpub_clk_atb_sel",
|
||||
.ops = &clk_regmap_mux_ro_ops,
|
||||
.parent_names = (const char *[]){ "cpub_clk_div2",
|
||||
"cpub_clk_div3",
|
||||
"cpub_clk_div4",
|
||||
"cpub_clk_div5",
|
||||
"cpub_clk_div6",
|
||||
"cpub_clk_div7",
|
||||
"cpub_clk_div8" },
|
||||
.num_parents = 7,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap g12b_cpub_clk_atb = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_SYS_CPUB_CLK_CNTL1,
|
||||
.bit_idx = 17,
|
||||
.flags = CLK_GATE_SET_TO_DISABLE,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "cpub_clk_atb",
|
||||
.ops = &clk_regmap_gate_ro_ops,
|
||||
.parent_names = (const char *[]){ "cpub_clk_atb_sel" },
|
||||
.num_parents = 1,
|
||||
/*
|
||||
* This clock is set by the ROM monitor code,
|
||||
* Linux should not change it at runtime
|
||||
*/
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap g12b_cpub_clk_axi_sel = {
|
||||
.data = &(struct clk_regmap_mux_data){
|
||||
.offset = HHI_SYS_CPUB_CLK_CNTL1,
|
||||
.mask = 7,
|
||||
.shift = 9,
|
||||
.table = mux_table_cpub,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cpub_clk_axi_sel",
|
||||
.ops = &clk_regmap_mux_ro_ops,
|
||||
.parent_names = (const char *[]){ "cpub_clk_div2",
|
||||
"cpub_clk_div3",
|
||||
"cpub_clk_div4",
|
||||
"cpub_clk_div5",
|
||||
"cpub_clk_div6",
|
||||
"cpub_clk_div7",
|
||||
"cpub_clk_div8" },
|
||||
.num_parents = 7,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap g12b_cpub_clk_axi = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_SYS_CPUB_CLK_CNTL1,
|
||||
.bit_idx = 18,
|
||||
.flags = CLK_GATE_SET_TO_DISABLE,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "cpub_clk_axi",
|
||||
.ops = &clk_regmap_gate_ro_ops,
|
||||
.parent_names = (const char *[]){ "cpub_clk_axi_sel" },
|
||||
.num_parents = 1,
|
||||
/*
|
||||
* This clock is set by the ROM monitor code,
|
||||
* Linux should not change it at runtime
|
||||
*/
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap g12b_cpub_clk_trace_sel = {
|
||||
.data = &(struct clk_regmap_mux_data){
|
||||
.offset = HHI_SYS_CPUB_CLK_CNTL1,
|
||||
.mask = 7,
|
||||
.shift = 20,
|
||||
.table = mux_table_cpub,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cpub_clk_trace_sel",
|
||||
.ops = &clk_regmap_mux_ro_ops,
|
||||
.parent_names = (const char *[]){ "cpub_clk_div2",
|
||||
"cpub_clk_div3",
|
||||
"cpub_clk_div4",
|
||||
"cpub_clk_div5",
|
||||
"cpub_clk_div6",
|
||||
"cpub_clk_div7",
|
||||
"cpub_clk_div8" },
|
||||
.num_parents = 7,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap g12b_cpub_clk_trace = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_SYS_CPUB_CLK_CNTL1,
|
||||
.bit_idx = 23,
|
||||
.flags = CLK_GATE_SET_TO_DISABLE,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "cpub_clk_trace",
|
||||
.ops = &clk_regmap_gate_ro_ops,
|
||||
.parent_names = (const char *[]){ "cpub_clk_trace_sel" },
|
||||
.num_parents = 1,
|
||||
/*
|
||||
* This clock is set by the ROM monitor code,
|
||||
* Linux should not change it at runtime
|
||||
*/
|
||||
},
|
||||
};
|
||||
|
||||
static const struct pll_mult_range g12a_gp0_pll_mult_range = {
|
||||
.min = 55,
|
||||
.max = 255,
|
||||
|
|
@ -865,6 +1350,16 @@ static struct clk_regmap g12a_fclk_div3 = {
|
|||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_names = (const char *[]){ "fclk_div3_div" },
|
||||
.num_parents = 1,
|
||||
/*
|
||||
* This clock is used by the resident firmware and is required
|
||||
* by the platform to operate correctly.
|
||||
* Until the following condition are met, we need this clock to
|
||||
* be marked as critical:
|
||||
* a) Mark the clock used by a firmware resource, if possible
|
||||
* b) CCF has a clock hand-off mechanism to make the sure the
|
||||
* clock stays on until the proper driver comes along
|
||||
*/
|
||||
.flags = CLK_IS_CRITICAL,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -1001,6 +1496,10 @@ static struct clk_fixed_factor g12a_mpll_prediv = {
|
|||
},
|
||||
};
|
||||
|
||||
static const struct reg_sequence g12a_mpll0_init_regs[] = {
|
||||
{ .reg = HHI_MPLL_CNTL2, .def = 0x40000033 },
|
||||
};
|
||||
|
||||
static struct clk_regmap g12a_mpll0_div = {
|
||||
.data = &(struct meson_clk_mpll_data){
|
||||
.sdm = {
|
||||
|
|
@ -1024,6 +1523,8 @@ static struct clk_regmap g12a_mpll0_div = {
|
|||
.width = 1,
|
||||
},
|
||||
.lock = &meson_clk_lock,
|
||||
.init_regs = g12a_mpll0_init_regs,
|
||||
.init_count = ARRAY_SIZE(g12a_mpll0_init_regs),
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "mpll0_div",
|
||||
|
|
@ -1047,6 +1548,10 @@ static struct clk_regmap g12a_mpll0 = {
|
|||
},
|
||||
};
|
||||
|
||||
static const struct reg_sequence g12a_mpll1_init_regs[] = {
|
||||
{ .reg = HHI_MPLL_CNTL4, .def = 0x40000033 },
|
||||
};
|
||||
|
||||
static struct clk_regmap g12a_mpll1_div = {
|
||||
.data = &(struct meson_clk_mpll_data){
|
||||
.sdm = {
|
||||
|
|
@ -1070,6 +1575,8 @@ static struct clk_regmap g12a_mpll1_div = {
|
|||
.width = 1,
|
||||
},
|
||||
.lock = &meson_clk_lock,
|
||||
.init_regs = g12a_mpll1_init_regs,
|
||||
.init_count = ARRAY_SIZE(g12a_mpll1_init_regs),
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "mpll1_div",
|
||||
|
|
@ -1093,6 +1600,10 @@ static struct clk_regmap g12a_mpll1 = {
|
|||
},
|
||||
};
|
||||
|
||||
static const struct reg_sequence g12a_mpll2_init_regs[] = {
|
||||
{ .reg = HHI_MPLL_CNTL6, .def = 0x40000033 },
|
||||
};
|
||||
|
||||
static struct clk_regmap g12a_mpll2_div = {
|
||||
.data = &(struct meson_clk_mpll_data){
|
||||
.sdm = {
|
||||
|
|
@ -1116,6 +1627,8 @@ static struct clk_regmap g12a_mpll2_div = {
|
|||
.width = 1,
|
||||
},
|
||||
.lock = &meson_clk_lock,
|
||||
.init_regs = g12a_mpll2_init_regs,
|
||||
.init_count = ARRAY_SIZE(g12a_mpll2_init_regs),
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "mpll2_div",
|
||||
|
|
@ -1139,6 +1652,10 @@ static struct clk_regmap g12a_mpll2 = {
|
|||
},
|
||||
};
|
||||
|
||||
static const struct reg_sequence g12a_mpll3_init_regs[] = {
|
||||
{ .reg = HHI_MPLL_CNTL8, .def = 0x40000033 },
|
||||
};
|
||||
|
||||
static struct clk_regmap g12a_mpll3_div = {
|
||||
.data = &(struct meson_clk_mpll_data){
|
||||
.sdm = {
|
||||
|
|
@ -1162,6 +1679,8 @@ static struct clk_regmap g12a_mpll3_div = {
|
|||
.width = 1,
|
||||
},
|
||||
.lock = &meson_clk_lock,
|
||||
.init_regs = g12a_mpll3_init_regs,
|
||||
.init_count = ARRAY_SIZE(g12a_mpll3_init_regs),
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "mpll3_div",
|
||||
|
|
@ -2480,6 +2999,33 @@ static struct clk_regmap g12a_mali = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap g12a_ts_div = {
|
||||
.data = &(struct clk_regmap_div_data){
|
||||
.offset = HHI_TS_CLK_CNTL,
|
||||
.shift = 0,
|
||||
.width = 8,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "ts_div",
|
||||
.ops = &clk_regmap_divider_ro_ops,
|
||||
.parent_names = (const char *[]){ "xtal" },
|
||||
.num_parents = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap g12a_ts = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_TS_CLK_CNTL,
|
||||
.bit_idx = 8,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "ts",
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_names = (const char *[]){ "ts_div" },
|
||||
.num_parents = 1,
|
||||
},
|
||||
};
|
||||
|
||||
/* Everything Else (EE) domain gates */
|
||||
static MESON_GATE(g12a_ddr, HHI_GCLK_MPEG0, 0);
|
||||
static MESON_GATE(g12a_dos, HHI_GCLK_MPEG0, 1);
|
||||
|
|
@ -2734,8 +3280,8 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = {
|
|||
[CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
|
||||
[CLKID_MALI_1] = &g12a_mali_1.hw,
|
||||
[CLKID_MALI] = &g12a_mali.hw,
|
||||
[CLKID_MPLL_5OM_DIV] = &g12a_mpll_50m_div.hw,
|
||||
[CLKID_MPLL_5OM] = &g12a_mpll_50m.hw,
|
||||
[CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
|
||||
[CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
|
||||
[CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
|
||||
[CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
|
||||
[CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
|
||||
|
|
@ -2769,6 +3315,257 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = {
|
|||
[CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
|
||||
[CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
|
||||
[CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
|
||||
[CLKID_TS_DIV] = &g12a_ts_div.hw,
|
||||
[CLKID_TS] = &g12a_ts.hw,
|
||||
[NR_CLKS] = NULL,
|
||||
},
|
||||
.num = NR_CLKS,
|
||||
};
|
||||
|
||||
static struct clk_hw_onecell_data g12b_hw_onecell_data = {
|
||||
.hws = {
|
||||
[CLKID_SYS_PLL] = &g12a_sys_pll.hw,
|
||||
[CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
|
||||
[CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
|
||||
[CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
|
||||
[CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
|
||||
[CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
|
||||
[CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
|
||||
[CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
|
||||
[CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
|
||||
[CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
|
||||
[CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
|
||||
[CLKID_CLK81] = &g12a_clk81.hw,
|
||||
[CLKID_MPLL0] = &g12a_mpll0.hw,
|
||||
[CLKID_MPLL1] = &g12a_mpll1.hw,
|
||||
[CLKID_MPLL2] = &g12a_mpll2.hw,
|
||||
[CLKID_MPLL3] = &g12a_mpll3.hw,
|
||||
[CLKID_DDR] = &g12a_ddr.hw,
|
||||
[CLKID_DOS] = &g12a_dos.hw,
|
||||
[CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
|
||||
[CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
|
||||
[CLKID_ETH_PHY] = &g12a_eth_phy.hw,
|
||||
[CLKID_ISA] = &g12a_isa.hw,
|
||||
[CLKID_PL301] = &g12a_pl301.hw,
|
||||
[CLKID_PERIPHS] = &g12a_periphs.hw,
|
||||
[CLKID_SPICC0] = &g12a_spicc_0.hw,
|
||||
[CLKID_I2C] = &g12a_i2c.hw,
|
||||
[CLKID_SANA] = &g12a_sana.hw,
|
||||
[CLKID_SD] = &g12a_sd.hw,
|
||||
[CLKID_RNG0] = &g12a_rng0.hw,
|
||||
[CLKID_UART0] = &g12a_uart0.hw,
|
||||
[CLKID_SPICC1] = &g12a_spicc_1.hw,
|
||||
[CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
|
||||
[CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
|
||||
[CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
|
||||
[CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
|
||||
[CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
|
||||
[CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
|
||||
[CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
|
||||
[CLKID_AUDIO] = &g12a_audio.hw,
|
||||
[CLKID_ETH] = &g12a_eth_core.hw,
|
||||
[CLKID_DEMUX] = &g12a_demux.hw,
|
||||
[CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
|
||||
[CLKID_ADC] = &g12a_adc.hw,
|
||||
[CLKID_UART1] = &g12a_uart1.hw,
|
||||
[CLKID_G2D] = &g12a_g2d.hw,
|
||||
[CLKID_RESET] = &g12a_reset.hw,
|
||||
[CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
|
||||
[CLKID_PARSER] = &g12a_parser.hw,
|
||||
[CLKID_USB] = &g12a_usb_general.hw,
|
||||
[CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
|
||||
[CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
|
||||
[CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
|
||||
[CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
|
||||
[CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
|
||||
[CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
|
||||
[CLKID_BT656] = &g12a_bt656.hw,
|
||||
[CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
|
||||
[CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
|
||||
[CLKID_UART2] = &g12a_uart2.hw,
|
||||
[CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
|
||||
[CLKID_GIC] = &g12a_gic.hw,
|
||||
[CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
|
||||
[CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
|
||||
[CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
|
||||
[CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
|
||||
[CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
|
||||
[CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
|
||||
[CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
|
||||
[CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
|
||||
[CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
|
||||
[CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
|
||||
[CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
|
||||
[CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
|
||||
[CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
|
||||
[CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
|
||||
[CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
|
||||
[CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
|
||||
[CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
|
||||
[CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
|
||||
[CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
|
||||
[CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
|
||||
[CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
|
||||
[CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
|
||||
[CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
|
||||
[CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
|
||||
[CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
|
||||
[CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
|
||||
[CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
|
||||
[CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
|
||||
[CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
|
||||
[CLKID_DAC_CLK] = &g12a_dac_clk.hw,
|
||||
[CLKID_AOCLK] = &g12a_aoclk_gate.hw,
|
||||
[CLKID_IEC958] = &g12a_iec958_gate.hw,
|
||||
[CLKID_ENC480P] = &g12a_enc480p.hw,
|
||||
[CLKID_RNG1] = &g12a_rng1.hw,
|
||||
[CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
|
||||
[CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
|
||||
[CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
|
||||
[CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
|
||||
[CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
|
||||
[CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
|
||||
[CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
|
||||
[CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
|
||||
[CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
|
||||
[CLKID_DMA] = &g12a_dma.hw,
|
||||
[CLKID_EFUSE] = &g12a_efuse.hw,
|
||||
[CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
|
||||
[CLKID_RESET_SEC] = &g12a_reset_sec.hw,
|
||||
[CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
|
||||
[CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
|
||||
[CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
|
||||
[CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
|
||||
[CLKID_VPU_0] = &g12a_vpu_0.hw,
|
||||
[CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
|
||||
[CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
|
||||
[CLKID_VPU_1] = &g12a_vpu_1.hw,
|
||||
[CLKID_VPU] = &g12a_vpu.hw,
|
||||
[CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
|
||||
[CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
|
||||
[CLKID_VAPB_0] = &g12a_vapb_0.hw,
|
||||
[CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
|
||||
[CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
|
||||
[CLKID_VAPB_1] = &g12a_vapb_1.hw,
|
||||
[CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
|
||||
[CLKID_VAPB] = &g12a_vapb.hw,
|
||||
[CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
|
||||
[CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
|
||||
[CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
|
||||
[CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
|
||||
[CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
|
||||
[CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
|
||||
[CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
|
||||
[CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
|
||||
[CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
|
||||
[CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
|
||||
[CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
|
||||
[CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
|
||||
[CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
|
||||
[CLKID_VCLK] = &g12a_vclk.hw,
|
||||
[CLKID_VCLK2] = &g12a_vclk2.hw,
|
||||
[CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
|
||||
[CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
|
||||
[CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
|
||||
[CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
|
||||
[CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
|
||||
[CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
|
||||
[CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
|
||||
[CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
|
||||
[CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
|
||||
[CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
|
||||
[CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
|
||||
[CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
|
||||
[CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
|
||||
[CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
|
||||
[CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
|
||||
[CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
|
||||
[CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
|
||||
[CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
|
||||
[CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
|
||||
[CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
|
||||
[CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
|
||||
[CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
|
||||
[CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
|
||||
[CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
|
||||
[CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
|
||||
[CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
|
||||
[CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
|
||||
[CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
|
||||
[CLKID_HDMI] = &g12a_hdmi.hw,
|
||||
[CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
|
||||
[CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
|
||||
[CLKID_MALI_0] = &g12a_mali_0.hw,
|
||||
[CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
|
||||
[CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
|
||||
[CLKID_MALI_1] = &g12a_mali_1.hw,
|
||||
[CLKID_MALI] = &g12a_mali.hw,
|
||||
[CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
|
||||
[CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
|
||||
[CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
|
||||
[CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
|
||||
[CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
|
||||
[CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
|
||||
[CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
|
||||
[CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
|
||||
[CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
|
||||
[CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
|
||||
[CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
|
||||
[CLKID_CPU_CLK] = &g12b_cpu_clk.hw,
|
||||
[CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
|
||||
[CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
|
||||
[CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
|
||||
[CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
|
||||
[CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
|
||||
[CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
|
||||
[CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
|
||||
[CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
|
||||
[CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
|
||||
[CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
|
||||
[CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
|
||||
[CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
|
||||
[CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
|
||||
[CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
|
||||
[CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
|
||||
[CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
|
||||
[CLKID_VDEC_1] = &g12a_vdec_1.hw,
|
||||
[CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
|
||||
[CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
|
||||
[CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
|
||||
[CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
|
||||
[CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
|
||||
[CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
|
||||
[CLKID_TS_DIV] = &g12a_ts_div.hw,
|
||||
[CLKID_TS] = &g12a_ts.hw,
|
||||
[CLKID_SYS1_PLL_DCO] = &g12b_sys1_pll_dco.hw,
|
||||
[CLKID_SYS1_PLL] = &g12b_sys1_pll.hw,
|
||||
[CLKID_SYS1_PLL_DIV16_EN] = &g12b_sys1_pll_div16_en.hw,
|
||||
[CLKID_SYS1_PLL_DIV16] = &g12b_sys1_pll_div16.hw,
|
||||
[CLKID_CPUB_CLK_DYN0_SEL] = &g12b_cpub_clk_premux0.hw,
|
||||
[CLKID_CPUB_CLK_DYN0_DIV] = &g12b_cpub_clk_mux0_div.hw,
|
||||
[CLKID_CPUB_CLK_DYN0] = &g12b_cpub_clk_postmux0.hw,
|
||||
[CLKID_CPUB_CLK_DYN1_SEL] = &g12b_cpub_clk_premux1.hw,
|
||||
[CLKID_CPUB_CLK_DYN1_DIV] = &g12b_cpub_clk_mux1_div.hw,
|
||||
[CLKID_CPUB_CLK_DYN1] = &g12b_cpub_clk_postmux1.hw,
|
||||
[CLKID_CPUB_CLK_DYN] = &g12b_cpub_clk_dyn.hw,
|
||||
[CLKID_CPUB_CLK] = &g12b_cpub_clk.hw,
|
||||
[CLKID_CPUB_CLK_DIV16_EN] = &g12b_cpub_clk_div16_en.hw,
|
||||
[CLKID_CPUB_CLK_DIV16] = &g12b_cpub_clk_div16.hw,
|
||||
[CLKID_CPUB_CLK_DIV2] = &g12b_cpub_clk_div2.hw,
|
||||
[CLKID_CPUB_CLK_DIV3] = &g12b_cpub_clk_div3.hw,
|
||||
[CLKID_CPUB_CLK_DIV4] = &g12b_cpub_clk_div4.hw,
|
||||
[CLKID_CPUB_CLK_DIV5] = &g12b_cpub_clk_div5.hw,
|
||||
[CLKID_CPUB_CLK_DIV6] = &g12b_cpub_clk_div6.hw,
|
||||
[CLKID_CPUB_CLK_DIV7] = &g12b_cpub_clk_div7.hw,
|
||||
[CLKID_CPUB_CLK_DIV8] = &g12b_cpub_clk_div8.hw,
|
||||
[CLKID_CPUB_CLK_APB_SEL] = &g12b_cpub_clk_apb_sel.hw,
|
||||
[CLKID_CPUB_CLK_APB] = &g12b_cpub_clk_apb.hw,
|
||||
[CLKID_CPUB_CLK_ATB_SEL] = &g12b_cpub_clk_atb_sel.hw,
|
||||
[CLKID_CPUB_CLK_ATB] = &g12b_cpub_clk_atb.hw,
|
||||
[CLKID_CPUB_CLK_AXI_SEL] = &g12b_cpub_clk_axi_sel.hw,
|
||||
[CLKID_CPUB_CLK_AXI] = &g12b_cpub_clk_axi.hw,
|
||||
[CLKID_CPUB_CLK_TRACE_SEL] = &g12b_cpub_clk_trace_sel.hw,
|
||||
[CLKID_CPUB_CLK_TRACE] = &g12b_cpub_clk_trace.hw,
|
||||
[NR_CLKS] = NULL,
|
||||
},
|
||||
.num = NR_CLKS,
|
||||
|
|
@ -2966,16 +3763,52 @@ static struct clk_regmap *const g12a_clk_regmaps[] = {
|
|||
&g12a_vdec_hevcf_sel,
|
||||
&g12a_vdec_hevcf_div,
|
||||
&g12a_vdec_hevcf,
|
||||
&g12a_ts_div,
|
||||
&g12a_ts,
|
||||
&g12b_cpu_clk,
|
||||
&g12b_sys1_pll_dco,
|
||||
&g12b_sys1_pll,
|
||||
&g12b_sys1_pll_div16_en,
|
||||
&g12b_cpub_clk_premux0,
|
||||
&g12b_cpub_clk_mux0_div,
|
||||
&g12b_cpub_clk_postmux0,
|
||||
&g12b_cpub_clk_premux1,
|
||||
&g12b_cpub_clk_mux1_div,
|
||||
&g12b_cpub_clk_postmux1,
|
||||
&g12b_cpub_clk_dyn,
|
||||
&g12b_cpub_clk,
|
||||
&g12b_cpub_clk_div16_en,
|
||||
&g12b_cpub_clk_apb_sel,
|
||||
&g12b_cpub_clk_apb,
|
||||
&g12b_cpub_clk_atb_sel,
|
||||
&g12b_cpub_clk_atb,
|
||||
&g12b_cpub_clk_axi_sel,
|
||||
&g12b_cpub_clk_axi,
|
||||
&g12b_cpub_clk_trace_sel,
|
||||
&g12b_cpub_clk_trace,
|
||||
};
|
||||
|
||||
static const struct reg_sequence g12a_init_regs[] = {
|
||||
{ .reg = HHI_MPLL_CNTL0, .def = 0x00000543 },
|
||||
};
|
||||
|
||||
static const struct meson_eeclkc_data g12a_clkc_data = {
|
||||
.regmap_clks = g12a_clk_regmaps,
|
||||
.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
|
||||
.hw_onecell_data = &g12a_hw_onecell_data
|
||||
.hw_onecell_data = &g12a_hw_onecell_data,
|
||||
.init_regs = g12a_init_regs,
|
||||
.init_count = ARRAY_SIZE(g12a_init_regs),
|
||||
};
|
||||
|
||||
static const struct meson_eeclkc_data g12b_clkc_data = {
|
||||
.regmap_clks = g12a_clk_regmaps,
|
||||
.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
|
||||
.hw_onecell_data = &g12b_hw_onecell_data
|
||||
};
|
||||
|
||||
static const struct of_device_id clkc_match_table[] = {
|
||||
{ .compatible = "amlogic,g12a-clkc", .data = &g12a_clkc_data },
|
||||
{ .compatible = "amlogic,g12b-clkc", .data = &g12b_clkc_data },
|
||||
{}
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -69,6 +69,8 @@
|
|||
#define HHI_VDEC4_CLK_CNTL 0x1EC
|
||||
#define HHI_HDCP22_CLK_CNTL 0x1F0
|
||||
#define HHI_VAPBCLK_CNTL 0x1F4
|
||||
#define HHI_SYS_CPUB_CLK_CNTL1 0x200
|
||||
#define HHI_SYS_CPUB_CLK_CNTL 0x208
|
||||
#define HHI_VPU_CLKB_CNTL 0x20C
|
||||
#define HHI_GEN_CLK_CNTL 0x228
|
||||
#define HHI_VDIN_MEAS_CLK_CNTL 0x250
|
||||
|
|
@ -102,6 +104,13 @@
|
|||
#define HHI_HDMI_PLL_CNTL5 0x334
|
||||
#define HHI_HDMI_PLL_CNTL6 0x338
|
||||
#define HHI_SPICC_CLK_CNTL 0x3dc
|
||||
#define HHI_SYS1_PLL_CNTL0 0x380
|
||||
#define HHI_SYS1_PLL_CNTL1 0x384
|
||||
#define HHI_SYS1_PLL_CNTL2 0x388
|
||||
#define HHI_SYS1_PLL_CNTL3 0x38c
|
||||
#define HHI_SYS1_PLL_CNTL4 0x390
|
||||
#define HHI_SYS1_PLL_CNTL5 0x394
|
||||
#define HHI_SYS1_PLL_CNTL6 0x398
|
||||
|
||||
/*
|
||||
* CLKID index values
|
||||
|
|
@ -166,7 +175,7 @@
|
|||
#define CLKID_HDMI_DIV 167
|
||||
#define CLKID_MALI_0_DIV 170
|
||||
#define CLKID_MALI_1_DIV 173
|
||||
#define CLKID_MPLL_5OM_DIV 176
|
||||
#define CLKID_MPLL_50M_DIV 176
|
||||
#define CLKID_SYS_PLL_DIV16_EN 178
|
||||
#define CLKID_SYS_PLL_DIV16 179
|
||||
#define CLKID_CPU_CLK_DYN0_SEL 180
|
||||
|
|
@ -195,8 +204,38 @@
|
|||
#define CLKID_VDEC_HEVC_DIV 206
|
||||
#define CLKID_VDEC_HEVCF_SEL 208
|
||||
#define CLKID_VDEC_HEVCF_DIV 209
|
||||
#define CLKID_TS_DIV 211
|
||||
#define CLKID_SYS1_PLL_DCO 213
|
||||
#define CLKID_SYS1_PLL 214
|
||||
#define CLKID_SYS1_PLL_DIV16_EN 215
|
||||
#define CLKID_SYS1_PLL_DIV16 216
|
||||
#define CLKID_CPUB_CLK_DYN0_SEL 217
|
||||
#define CLKID_CPUB_CLK_DYN0_DIV 218
|
||||
#define CLKID_CPUB_CLK_DYN0 219
|
||||
#define CLKID_CPUB_CLK_DYN1_SEL 220
|
||||
#define CLKID_CPUB_CLK_DYN1_DIV 221
|
||||
#define CLKID_CPUB_CLK_DYN1 222
|
||||
#define CLKID_CPUB_CLK_DYN 223
|
||||
#define CLKID_CPUB_CLK 224
|
||||
#define CLKID_CPUB_CLK_DIV16_EN 225
|
||||
#define CLKID_CPUB_CLK_DIV16 226
|
||||
#define CLKID_CPUB_CLK_DIV2 227
|
||||
#define CLKID_CPUB_CLK_DIV3 228
|
||||
#define CLKID_CPUB_CLK_DIV4 229
|
||||
#define CLKID_CPUB_CLK_DIV5 230
|
||||
#define CLKID_CPUB_CLK_DIV6 231
|
||||
#define CLKID_CPUB_CLK_DIV7 232
|
||||
#define CLKID_CPUB_CLK_DIV8 233
|
||||
#define CLKID_CPUB_CLK_APB_SEL 234
|
||||
#define CLKID_CPUB_CLK_APB 235
|
||||
#define CLKID_CPUB_CLK_ATB_SEL 236
|
||||
#define CLKID_CPUB_CLK_ATB 237
|
||||
#define CLKID_CPUB_CLK_AXI_SEL 238
|
||||
#define CLKID_CPUB_CLK_AXI 239
|
||||
#define CLKID_CPUB_CLK_TRACE_SEL 240
|
||||
#define CLKID_CPUB_CLK_TRACE 241
|
||||
|
||||
#define NR_CLKS 211
|
||||
#define NR_CLKS 242
|
||||
|
||||
/* include the CLKIDs that have been made part of the DT binding */
|
||||
#include <dt-bindings/clock/g12a-clkc.h>
|
||||
|
|
|
|||
|
|
@ -679,11 +679,6 @@ static struct clk_regmap gxbb_mpll0_div = {
|
|||
.shift = 16,
|
||||
.width = 9,
|
||||
},
|
||||
.ssen = {
|
||||
.reg_off = HHI_MPLL_CNTL,
|
||||
.shift = 25,
|
||||
.width = 1,
|
||||
},
|
||||
.lock = &meson_clk_lock,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
|
|
|
|||
|
|
@ -34,6 +34,9 @@ int meson_eeclkc_probe(struct platform_device *pdev)
|
|||
return PTR_ERR(map);
|
||||
}
|
||||
|
||||
if (data->init_count)
|
||||
regmap_multi_reg_write(map, data->init_regs, data->init_count);
|
||||
|
||||
input = meson_clk_hw_register_input(dev, "xtal", IN_PREFIX "xtal", 0);
|
||||
if (IS_ERR(input)) {
|
||||
ret = PTR_ERR(input);
|
||||
|
|
|
|||
|
|
@ -17,6 +17,8 @@ struct platform_device;
|
|||
struct meson_eeclkc_data {
|
||||
struct clk_regmap *const *regmap_clks;
|
||||
unsigned int regmap_clk_num;
|
||||
const struct reg_sequence *init_regs;
|
||||
unsigned int init_count;
|
||||
struct clk_hw_onecell_data *hw_onecell_data;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -1761,7 +1761,7 @@ static struct clk_regmap meson8m2_gp_pll = {
|
|||
},
|
||||
};
|
||||
|
||||
static const char * const mmeson8b_vpu_0_1_parent_names[] = {
|
||||
static const char * const meson8b_vpu_0_1_parent_names[] = {
|
||||
"fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
|
||||
};
|
||||
|
||||
|
|
@ -1778,8 +1778,8 @@ static struct clk_regmap meson8b_vpu_0_sel = {
|
|||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vpu_0_sel",
|
||||
.ops = &clk_regmap_mux_ops,
|
||||
.parent_names = mmeson8b_vpu_0_1_parent_names,
|
||||
.num_parents = ARRAY_SIZE(mmeson8b_vpu_0_1_parent_names),
|
||||
.parent_names = meson8b_vpu_0_1_parent_names,
|
||||
.num_parents = ARRAY_SIZE(meson8b_vpu_0_1_parent_names),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
|
@ -1837,8 +1837,8 @@ static struct clk_regmap meson8b_vpu_1_sel = {
|
|||
.hw.init = &(struct clk_init_data){
|
||||
.name = "vpu_1_sel",
|
||||
.ops = &clk_regmap_mux_ops,
|
||||
.parent_names = mmeson8b_vpu_0_1_parent_names,
|
||||
.num_parents = ARRAY_SIZE(mmeson8b_vpu_0_1_parent_names),
|
||||
.parent_names = meson8b_vpu_0_1_parent_names,
|
||||
.num_parents = ARRAY_SIZE(meson8b_vpu_0_1_parent_names),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
|
@ -2153,6 +2153,132 @@ static struct clk_regmap meson8b_vdec_hevc = {
|
|||
},
|
||||
};
|
||||
|
||||
/* TODO: the clock at index 0 is "DDR_PLL" which we don't support yet */
|
||||
static const char * const meson8b_cts_amclk_parent_names[] = {
|
||||
"mpll0", "mpll1", "mpll2"
|
||||
};
|
||||
|
||||
static u32 meson8b_cts_amclk_mux_table[] = { 1, 2, 3 };
|
||||
|
||||
static struct clk_regmap meson8b_cts_amclk_sel = {
|
||||
.data = &(struct clk_regmap_mux_data){
|
||||
.offset = HHI_AUD_CLK_CNTL,
|
||||
.mask = 0x3,
|
||||
.shift = 9,
|
||||
.table = meson8b_cts_amclk_mux_table,
|
||||
.flags = CLK_MUX_ROUND_CLOSEST,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cts_amclk_sel",
|
||||
.ops = &clk_regmap_mux_ops,
|
||||
.parent_names = meson8b_cts_amclk_parent_names,
|
||||
.num_parents = ARRAY_SIZE(meson8b_cts_amclk_parent_names),
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap meson8b_cts_amclk_div = {
|
||||
.data = &(struct clk_regmap_div_data) {
|
||||
.offset = HHI_AUD_CLK_CNTL,
|
||||
.shift = 0,
|
||||
.width = 8,
|
||||
.flags = CLK_DIVIDER_ROUND_CLOSEST,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cts_amclk_div",
|
||||
.ops = &clk_regmap_divider_ops,
|
||||
.parent_names = (const char *[]){ "cts_amclk_sel" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap meson8b_cts_amclk = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_AUD_CLK_CNTL,
|
||||
.bit_idx = 8,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cts_amclk",
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_names = (const char *[]){ "cts_amclk_div" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
/* TODO: the clock at index 0 is "DDR_PLL" which we don't support yet */
|
||||
static const char * const meson8b_cts_mclk_i958_parent_names[] = {
|
||||
"mpll0", "mpll1", "mpll2"
|
||||
};
|
||||
|
||||
static u32 meson8b_cts_mclk_i958_mux_table[] = { 1, 2, 3 };
|
||||
|
||||
static struct clk_regmap meson8b_cts_mclk_i958_sel = {
|
||||
.data = &(struct clk_regmap_mux_data){
|
||||
.offset = HHI_AUD_CLK_CNTL2,
|
||||
.mask = 0x3,
|
||||
.shift = 25,
|
||||
.table = meson8b_cts_mclk_i958_mux_table,
|
||||
.flags = CLK_MUX_ROUND_CLOSEST,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "cts_mclk_i958_sel",
|
||||
.ops = &clk_regmap_mux_ops,
|
||||
.parent_names = meson8b_cts_mclk_i958_parent_names,
|
||||
.num_parents = ARRAY_SIZE(meson8b_cts_mclk_i958_parent_names),
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap meson8b_cts_mclk_i958_div = {
|
||||
.data = &(struct clk_regmap_div_data){
|
||||
.offset = HHI_AUD_CLK_CNTL2,
|
||||
.shift = 16,
|
||||
.width = 8,
|
||||
.flags = CLK_DIVIDER_ROUND_CLOSEST,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "cts_mclk_i958_div",
|
||||
.ops = &clk_regmap_divider_ops,
|
||||
.parent_names = (const char *[]){ "cts_mclk_i958_sel" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap meson8b_cts_mclk_i958 = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_AUD_CLK_CNTL2,
|
||||
.bit_idx = 24,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cts_mclk_i958",
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_names = (const char *[]){ "cts_mclk_i958_div" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap meson8b_cts_i958 = {
|
||||
.data = &(struct clk_regmap_mux_data){
|
||||
.offset = HHI_AUD_CLK_CNTL2,
|
||||
.mask = 0x1,
|
||||
.shift = 27,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cts_i958",
|
||||
.ops = &clk_regmap_mux_ops,
|
||||
.parent_names = (const char *[]){ "cts_amclk",
|
||||
"cts_mclk_i958" },
|
||||
.num_parents = 2,
|
||||
/*
|
||||
* The parent is specific to origin of the audio data. Let the
|
||||
* consumer choose the appropriate parent.
|
||||
*/
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
||||
},
|
||||
};
|
||||
|
||||
/* Everything Else (EE) domain gates */
|
||||
|
||||
static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0);
|
||||
|
|
@ -2432,6 +2558,13 @@ static struct clk_hw_onecell_data meson8_hw_onecell_data = {
|
|||
[CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw,
|
||||
[CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw,
|
||||
[CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw,
|
||||
[CLKID_CTS_AMCLK_SEL] = &meson8b_cts_amclk_sel.hw,
|
||||
[CLKID_CTS_AMCLK_DIV] = &meson8b_cts_amclk_div.hw,
|
||||
[CLKID_CTS_AMCLK] = &meson8b_cts_amclk.hw,
|
||||
[CLKID_CTS_MCLK_I958_SEL] = &meson8b_cts_mclk_i958_sel.hw,
|
||||
[CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw,
|
||||
[CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw,
|
||||
[CLKID_CTS_I958] = &meson8b_cts_i958.hw,
|
||||
[CLK_NR_CLKS] = NULL,
|
||||
},
|
||||
.num = CLK_NR_CLKS,
|
||||
|
|
@ -2641,6 +2774,13 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
|
|||
[CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw,
|
||||
[CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw,
|
||||
[CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw,
|
||||
[CLKID_CTS_AMCLK_SEL] = &meson8b_cts_amclk_sel.hw,
|
||||
[CLKID_CTS_AMCLK_DIV] = &meson8b_cts_amclk_div.hw,
|
||||
[CLKID_CTS_AMCLK] = &meson8b_cts_amclk.hw,
|
||||
[CLKID_CTS_MCLK_I958_SEL] = &meson8b_cts_mclk_i958_sel.hw,
|
||||
[CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw,
|
||||
[CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw,
|
||||
[CLKID_CTS_I958] = &meson8b_cts_i958.hw,
|
||||
[CLK_NR_CLKS] = NULL,
|
||||
},
|
||||
.num = CLK_NR_CLKS,
|
||||
|
|
@ -2852,6 +2992,13 @@ static struct clk_hw_onecell_data meson8m2_hw_onecell_data = {
|
|||
[CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw,
|
||||
[CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw,
|
||||
[CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw,
|
||||
[CLKID_CTS_AMCLK_SEL] = &meson8b_cts_amclk_sel.hw,
|
||||
[CLKID_CTS_AMCLK_DIV] = &meson8b_cts_amclk_div.hw,
|
||||
[CLKID_CTS_AMCLK] = &meson8b_cts_amclk.hw,
|
||||
[CLKID_CTS_MCLK_I958_SEL] = &meson8b_cts_mclk_i958_sel.hw,
|
||||
[CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw,
|
||||
[CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw,
|
||||
[CLKID_CTS_I958] = &meson8b_cts_i958.hw,
|
||||
[CLK_NR_CLKS] = NULL,
|
||||
},
|
||||
.num = CLK_NR_CLKS,
|
||||
|
|
@ -3041,6 +3188,13 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = {
|
|||
&meson8b_vdec_hevc_div,
|
||||
&meson8b_vdec_hevc_en,
|
||||
&meson8b_vdec_hevc,
|
||||
&meson8b_cts_amclk,
|
||||
&meson8b_cts_amclk_sel,
|
||||
&meson8b_cts_amclk_div,
|
||||
&meson8b_cts_mclk_i958_sel,
|
||||
&meson8b_cts_mclk_i958_div,
|
||||
&meson8b_cts_mclk_i958,
|
||||
&meson8b_cts_i958,
|
||||
};
|
||||
|
||||
static const struct meson8b_clk_reset_line {
|
||||
|
|
|
|||
|
|
@ -30,7 +30,9 @@
|
|||
#define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data sheet */
|
||||
#define HHI_VID_CLK_DIV 0x164 /* 0x59 offset in data sheet */
|
||||
#define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */
|
||||
#define HHI_AUD_CLK_CNTL 0x178 /* 0x5e offset in data sheet */
|
||||
#define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */
|
||||
#define HHI_AUD_CLK_CNTL2 0x190 /* 0x64 offset in data sheet */
|
||||
#define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */
|
||||
#define HHI_VID_DIVIDER_CNTL 0x198 /* 0x66 offset in data sheet */
|
||||
#define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */
|
||||
|
|
@ -171,8 +173,12 @@
|
|||
#define CLKID_VDEC_HEVC_SEL 203
|
||||
#define CLKID_VDEC_HEVC_DIV 204
|
||||
#define CLKID_VDEC_HEVC_EN 205
|
||||
#define CLKID_CTS_AMCLK_SEL 207
|
||||
#define CLKID_CTS_AMCLK_DIV 208
|
||||
#define CLKID_CTS_MCLK_I958_SEL 210
|
||||
#define CLKID_CTS_MCLK_I958_DIV 211
|
||||
|
||||
#define CLK_NR_CLKS 207
|
||||
#define CLK_NR_CLKS 214
|
||||
|
||||
/*
|
||||
* include the CLKID and RESETID that have
|
||||
|
|
|
|||
|
|
@ -2766,6 +2766,13 @@ static const struct qcom_reset_map gcc_qcs404_resets[] = {
|
|||
[GCC_PCIE_0_PHY_BCR] = { 0x3e004 },
|
||||
[GCC_PCIE_0_LINK_DOWN_BCR] = { 0x3e038 },
|
||||
[GCC_PCIEPHY_0_PHY_BCR] = { 0x3e03c },
|
||||
[GCC_PCIE_0_AXI_MASTER_STICKY_ARES] = { 0x3e040, 6},
|
||||
[GCC_PCIE_0_AHB_ARES] = { 0x3e040, 5 },
|
||||
[GCC_PCIE_0_AXI_SLAVE_ARES] = { 0x3e040, 4 },
|
||||
[GCC_PCIE_0_AXI_MASTER_ARES] = { 0x3e040, 3 },
|
||||
[GCC_PCIE_0_CORE_STICKY_ARES] = { 0x3e040, 2 },
|
||||
[GCC_PCIE_0_SLEEP_ARES] = { 0x3e040, 1 },
|
||||
[GCC_PCIE_0_PIPE_ARES] = { 0x3e040, 0 },
|
||||
[GCC_EMAC_BCR] = { 0x4e000 },
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -149,7 +149,9 @@ static int gdsc_toggle_logic(struct gdsc *sc, enum gdsc_status status)
|
|||
udelay(1);
|
||||
}
|
||||
|
||||
return gdsc_poll_status(sc, status);
|
||||
ret = gdsc_poll_status(sc, status);
|
||||
WARN(ret, "%s status stuck at 'o%s'", sc->pd.name, status ? "ff" : "n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
static inline int gdsc_deassert_reset(struct gdsc *sc)
|
||||
|
|
|
|||
|
|
@ -130,11 +130,12 @@
|
|||
#define CLKID_MALI_1_SEL 172
|
||||
#define CLKID_MALI_1 174
|
||||
#define CLKID_MALI 175
|
||||
#define CLKID_MPLL_5OM 177
|
||||
#define CLKID_MPLL_50M 177
|
||||
#define CLKID_CPU_CLK 187
|
||||
#define CLKID_PCIE_PLL 201
|
||||
#define CLKID_VDEC_1 204
|
||||
#define CLKID_VDEC_HEVC 207
|
||||
#define CLKID_VDEC_HEVCF 210
|
||||
#define CLKID_TS 212
|
||||
|
||||
#endif /* __G12A_CLKC_H */
|
||||
|
|
|
|||
|
|
@ -112,5 +112,8 @@
|
|||
#define CLKID_VDEC_HCODEC 199
|
||||
#define CLKID_VDEC_2 202
|
||||
#define CLKID_VDEC_HEVC 206
|
||||
#define CLKID_CTS_AMCLK 209
|
||||
#define CLKID_CTS_MCLK_I958 212
|
||||
#define CLKID_CTS_I958 213
|
||||
|
||||
#endif /* __MESON8B_CLKC_H */
|
||||
|
|
|
|||
|
|
@ -166,5 +166,12 @@
|
|||
#define GCC_PCIEPHY_0_PHY_BCR 12
|
||||
#define GCC_EMAC_BCR 13
|
||||
#define GCC_CDSP_RESTART 14
|
||||
#define GCC_PCIE_0_AXI_MASTER_STICKY_ARES 15
|
||||
#define GCC_PCIE_0_AHB_ARES 16
|
||||
#define GCC_PCIE_0_AXI_SLAVE_ARES 17
|
||||
#define GCC_PCIE_0_AXI_MASTER_ARES 18
|
||||
#define GCC_PCIE_0_CORE_STICKY_ARES 19
|
||||
#define GCC_PCIE_0_SLEEP_ARES 20
|
||||
#define GCC_PCIE_0_PIPE_ARES 21
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue