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ARM: SoC fixes 

I had queued up a batch of fixes that got a bit close to the release for
 sending in before the merge window opened, so I'm including them in the
 batch of pull requests instead. They're mostly smaller DT tweaks and
 fixes, the usual mix that we tend to have through the releases.
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Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC fixes from Olof Johansson:
 "I had queued up a batch of fixes that got a bit close to the release
  for sending in before the merge window opened, so I'm including them
  in the merge window batch instead.

  Mostly smaller DT tweaks and fixes, the usual mix that we tend to have
  through the releases"

* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
  ARM: dts: iwg20d-q7-common: Fix touch controller probe failure
  ARM: OMAP2+: Restore MPU power domain if cpu_cluster_pm_enter() fails
  ARM: dts: am33xx: modify AM33XX_IOPAD for #pinctrl-cells = 2
  soc: actions: include header to fix missing prototype
  arm64: dts: ti: k3-j721e: Rename mux header and update macro names
  soc: qcom: pdr: Fixup array type of get_domain_list_resp message
  arm64: dts: qcom: pm660: Fix missing pound sign in interrupt-cells
  arm64: dts: qcom: kitakami: Temporarily disable SDHCI1
  arm64: dts: sdm630: Temporarily disable SMMUs by default
  arm64: dts: sdm845: Fixup OPP table for all qup devices
  arm64: dts: allwinner: h5: remove Mali GPU PMU module
  ARM: dts: sun8i: r40: bananapi-m2-ultra: Fix dcdc1 regulator
  soc: xilinx: Fix error code in zynqmp_pm_probe()
This commit is contained in:
Linus Torvalds 2020-10-24 10:26:06 -07:00
parent f11901ed72 6869f774b1
commit 1f70935f63
16 changed files with 134 additions and 82 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
arch/arm/boot/dts/iwg20d-q7-common.dtsi
View File

@ -57,7 +57,7 @@
lvds-receiver {
compatible = "ti,ds90cf384a", "lvds-decoder";
powerdown-gpios = <&gpio7 25 GPIO_ACTIVE_LOW>;
power-supply = <&vcc_3v3_tft1>;
ports {
#address-cells = <1>;
@ -81,6 +81,7 @@
panel {
compatible = "edt,etm0700g0dh6";
backlight = <&lcd_backlight>;
power-supply = <&vcc_3v3_tft1>;
port {
panel_in: endpoint {
@ -113,6 +114,17 @@
};
};
vcc_3v3_tft1: regulator-panel {
compatible = "regulator-fixed";
regulator-name = "vcc-3v3-tft1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
startup-delay-us = <500>;
gpio = <&gpio7 25 GPIO_ACTIVE_HIGH>;
};
vcc_sdhi1: regulator-vcc-sdhi1 {
compatible = "regulator-fixed";
@ -207,6 +219,7 @@
reg = <0x38>;
interrupt-parent = <&gpio2>;
interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
vcc-supply = <&vcc_3v3_tft1>;
};
};

10
arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
View File

@ -223,16 +223,16 @@
};
&reg_dc1sw {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-gmac-phy";
};
&reg_dcdc1 {
regulator-always-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc-3v0";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-3v3";
};
&reg_dcdc2 {

4
arch/arm/mach-omap2/cpuidle44xx.c
View File

@ -174,8 +174,10 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev,
*/
if (mpuss_can_lose_context) {
error = cpu_cluster_pm_enter();
if (error)
if (error) {
omap_set_pwrdm_state(mpu_pd, PWRDM_POWER_ON);
goto cpu_cluster_pm_out;
}
}
}

6
arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
View File

@ -139,8 +139,7 @@
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "gp",
"gpmmu",
"pp",
@ -151,8 +150,7 @@
"pp2",
"ppmmu2",
"pp3",
"ppmmu3",
"pmu";
"ppmmu3";
clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
clock-names = "bus", "core";
resets = <&ccu RST_BUS_GPU>;

7
arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi
View File

@ -221,7 +221,12 @@
};
&sdhc1 {
status = "okay";
/* There is an issue with the eMMC causing permanent
* damage to the card if a quirk isn't addressed.
* Until it's fixed, disable the MMC so as not to brick
* devices.
*/
status = "disabled";
/* Downstream pushes 2.95V to the sdhci device,
* but upstream driver REALLY wants to make vmmc 1.8v

2
arch/arm64/boot/dts/qcom/pm660.dtsi
View File

@ -44,7 +44,7 @@
gpio-ranges = <&pm660_gpios 0 0 13>;
#gpio-cells = <2>;
interrupt-controller;
interrupt-cells =<2>;
#interrupt-cells = <2>;
};
};
};

8
arch/arm64/boot/dts/qcom/sdm630.dtsi
View File

@ -518,6 +518,8 @@
<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
tcsr_mutex_regs: syscon@1f40000 {
@ -749,6 +751,8 @@
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
lpass_smmu: iommu@5100000 {
@ -778,6 +782,8 @@
<GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
spmi_bus: spmi@800f000 {
@ -1074,6 +1080,8 @@
<GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
apcs_glb: mailbox@17911000 {

9
arch/arm64/boot/dts/qcom/sdm845.dtsi
View File

@ -1093,8 +1093,8 @@
qup_opp_table: qup-opp-table {
compatible = "operating-points-v2";
opp-19200000 {
opp-hz = /bits/ 64 <19200000>;
opp-50000000 {
opp-hz = /bits/ 64 <50000000>;
required-opps = <&rpmhpd_opp_min_svs>;
};
@ -1107,6 +1107,11 @@
opp-hz = /bits/ 64 <100000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-128000000 {
opp-hz = /bits/ 64 <128000000>;
required-opps = <&rpmhpd_opp_nom>;
};
};
qupv3_id_0: geniqup@8c0000 {

11
arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
View File

@ -404,11 +404,12 @@
};
&serdes_ln_ctrl {
idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>,
<SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>,
<SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>,
<SERDES3_LANE0_USB3_0_SWAP>, <SERDES3_LANE1_USB3_0>,
<SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>;
idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
<J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
<J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
<J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
<J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
<J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
};
&serdes_wiz3 {

13
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
View File

@ -6,7 +6,7 @@
*/
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/mux/mux.h>
#include <dt-bindings/mux/mux-j721e-wiz.h>
#include <dt-bindings/mux/ti-serdes.h>
&cbass_main {
msmc_ram: sram@70000000 {
@ -38,11 +38,12 @@
<0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
<0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
/* SERDES4 lane0/1/2/3 select */
idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>,
<SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>,
<SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>,
<MUX_IDLE_AS_IS>, <SERDES3_LANE1_USB3_0>,
<SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>;
idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
<J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
<J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
<MUX_IDLE_AS_IS>, <J721E_SERDES3_LANE1_USB3_0>,
<J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
<J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
};
usb_serdes_mux: mux-controller@4000 {

1
drivers/soc/actions/owl-sps-helper.c
View File

@ -10,6 +10,7 @@
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/soc/actions/owl-sps.h>
#define OWL_SPS_PG_CTL 0x0

2
drivers/soc/qcom/pdr_internal.h
View File

@ -185,7 +185,7 @@ struct qmi_elem_info servreg_get_domain_list_resp_ei[] = {
.data_type = QMI_STRUCT,
.elem_len = SERVREG_DOMAIN_LIST_LENGTH,
.elem_size = sizeof(struct servreg_location_entry),
.array_type = NO_ARRAY,
.array_type = VAR_LEN_ARRAY,
.tlv_type = 0x12,
.offset = offsetof(struct servreg_get_domain_list_resp,
domain_list),

2
drivers/soc/xilinx/zynqmp_power.c
View File

@ -205,7 +205,7 @@ static int zynqmp_pm_probe(struct platform_device *pdev)
rx_chan = mbox_request_channel_byname(client, "rx");
if (IS_ERR(rx_chan)) {
dev_err(&pdev->dev, "Failed to request rx channel\n");
return IS_ERR(rx_chan);
return PTR_ERR(rx_chan);
}
} else if (of_find_property(pdev->dev.of_node, "interrupts", NULL)) {
irq = platform_get_irq(pdev, 0);

53
include/dt-bindings/mux/mux-j721e-wiz.h
View File

@ -1,53 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* This header provides constants for J721E WIZ.
*/
#ifndef _DT_BINDINGS_J721E_WIZ
#define _DT_BINDINGS_J721E_WIZ
#define SERDES0_LANE0_QSGMII_LANE1 0x0
#define SERDES0_LANE0_PCIE0_LANE0 0x1
#define SERDES0_LANE0_USB3_0_SWAP 0x2
#define SERDES0_LANE1_QSGMII_LANE2 0x0
#define SERDES0_LANE1_PCIE0_LANE1 0x1
#define SERDES0_LANE1_USB3_0 0x2
#define SERDES1_LANE0_QSGMII_LANE3 0x0
#define SERDES1_LANE0_PCIE1_LANE0 0x1
#define SERDES1_LANE0_USB3_1_SWAP 0x2
#define SERDES1_LANE0_SGMII_LANE0 0x3
#define SERDES1_LANE1_QSGMII_LANE4 0x0
#define SERDES1_LANE1_PCIE1_LANE1 0x1
#define SERDES1_LANE1_USB3_1 0x2
#define SERDES1_LANE1_SGMII_LANE1 0x3
#define SERDES2_LANE0_PCIE2_LANE0 0x1
#define SERDES2_LANE0_SGMII_LANE0 0x3
#define SERDES2_LANE0_USB3_1_SWAP 0x2
#define SERDES2_LANE1_PCIE2_LANE1 0x1
#define SERDES2_LANE1_USB3_1 0x2
#define SERDES2_LANE1_SGMII_LANE1 0x3
#define SERDES3_LANE0_PCIE3_LANE0 0x1
#define SERDES3_LANE0_USB3_0_SWAP 0x2
#define SERDES3_LANE1_PCIE3_LANE1 0x1
#define SERDES3_LANE1_USB3_0 0x2
#define SERDES4_LANE0_EDP_LANE0 0x0
#define SERDES4_LANE0_QSGMII_LANE5 0x2
#define SERDES4_LANE1_EDP_LANE1 0x0
#define SERDES4_LANE1_QSGMII_LANE6 0x2
#define SERDES4_LANE2_EDP_LANE2 0x0
#define SERDES4_LANE2_QSGMII_LANE7 0x2
#define SERDES4_LANE3_EDP_LANE3 0x0
#define SERDES4_LANE3_QSGMII_LANE8 0x2
#endif /* _DT_BINDINGS_J721E_WIZ */

71
include/dt-bindings/mux/ti-serdes.h Normal file
View File

@ -0,0 +1,71 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* This header provides constants for SERDES MUX for TI SoCs
*/
#ifndef _DT_BINDINGS_MUX_TI_SERDES
#define _DT_BINDINGS_MUX_TI_SERDES
/* J721E */
#define J721E_SERDES0_LANE0_QSGMII_LANE1 0x0
#define J721E_SERDES0_LANE0_PCIE0_LANE0 0x1
#define J721E_SERDES0_LANE0_USB3_0_SWAP 0x2
#define J721E_SERDES0_LANE0_IP4_UNUSED 0x3
#define J721E_SERDES0_LANE1_QSGMII_LANE2 0x0
#define J721E_SERDES0_LANE1_PCIE0_LANE1 0x1
#define J721E_SERDES0_LANE1_USB3_0 0x2
#define J721E_SERDES0_LANE1_IP4_UNUSED 0x3
#define J721E_SERDES1_LANE0_QSGMII_LANE3 0x0
#define J721E_SERDES1_LANE0_PCIE1_LANE0 0x1
#define J721E_SERDES1_LANE0_USB3_1_SWAP 0x2
#define J721E_SERDES1_LANE0_SGMII_LANE0 0x3
#define J721E_SERDES1_LANE1_QSGMII_LANE4 0x0
#define J721E_SERDES1_LANE1_PCIE1_LANE1 0x1
#define J721E_SERDES1_LANE1_USB3_1 0x2
#define J721E_SERDES1_LANE1_SGMII_LANE1 0x3
#define J721E_SERDES2_LANE0_IP1_UNUSED 0x0
#define J721E_SERDES2_LANE0_PCIE2_LANE0 0x1
#define J721E_SERDES2_LANE0_USB3_1_SWAP 0x2
#define J721E_SERDES2_LANE0_SGMII_LANE0 0x3
#define J721E_SERDES2_LANE1_IP1_UNUSED 0x0
#define J721E_SERDES2_LANE1_PCIE2_LANE1 0x1
#define J721E_SERDES2_LANE1_USB3_1 0x2
#define J721E_SERDES2_LANE1_SGMII_LANE1 0x3
#define J721E_SERDES3_LANE0_IP1_UNUSED 0x0
#define J721E_SERDES3_LANE0_PCIE3_LANE0 0x1
#define J721E_SERDES3_LANE0_USB3_0_SWAP 0x2
#define J721E_SERDES3_LANE0_IP4_UNUSED 0x3
#define J721E_SERDES3_LANE1_IP1_UNUSED 0x0
#define J721E_SERDES3_LANE1_PCIE3_LANE1 0x1
#define J721E_SERDES3_LANE1_USB3_0 0x2
#define J721E_SERDES3_LANE1_IP4_UNUSED 0x3
#define J721E_SERDES4_LANE0_EDP_LANE0 0x0
#define J721E_SERDES4_LANE0_IP2_UNUSED 0x1
#define J721E_SERDES4_LANE0_QSGMII_LANE5 0x2
#define J721E_SERDES4_LANE0_IP4_UNUSED 0x3
#define J721E_SERDES4_LANE1_EDP_LANE1 0x0
#define J721E_SERDES4_LANE1_IP2_UNUSED 0x1
#define J721E_SERDES4_LANE1_QSGMII_LANE6 0x2
#define J721E_SERDES4_LANE1_IP4_UNUSED 0x3
#define J721E_SERDES4_LANE2_EDP_LANE2 0x0
#define J721E_SERDES4_LANE2_IP2_UNUSED 0x1
#define J721E_SERDES4_LANE2_QSGMII_LANE7 0x2
#define J721E_SERDES4_LANE2_IP4_UNUSED 0x3
#define J721E_SERDES4_LANE3_EDP_LANE3 0x0
#define J721E_SERDES4_LANE3_IP2_UNUSED 0x1
#define J721E_SERDES4_LANE3_QSGMII_LANE8 0x2
#define J721E_SERDES4_LANE3_IP4_UNUSED 0x3
#endif /* _DT_BINDINGS_MUX_TI_SERDES */

2
include/dt-bindings/pinctrl/omap.h
View File

@ -64,7 +64,7 @@
#define OMAP3_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2a00) (val)
#define DM814X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
#define DM816X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
#define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
#define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) (0)
#define AM33XX_PADCONF(pa, conf, mux) OMAP_IOPAD_OFFSET((pa), 0x0800) (conf) (mux)
/*