PCI/x86: don't assume prefetchable ranges are 64bit
We should not assign 64bit ranges to PCI devices that only take 32bit prefetchable addresses. Try to set IORESOURCE_MEM_64 in 64bit resource of pci_device/pci_bridge and make the bus resource only have that bit set when all devices under it support 64bit prefetchable memory. Use that flag to allocate resources from that range. Reported-by: Yannick <yannick.roehlly@free.fr> Reviewed-by: Ivan Kokshaysky <ink@jurassic.park.msu.ru> Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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@ -130,6 +130,7 @@ extern void pci_iommu_alloc(void);
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/* generic pci stuff */
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#include <asm-generic/pci.h>
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#define PCIBIOS_MAX_MEM_32 0xffffffff
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#ifdef CONFIG_NUMA
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/* Returns the node based on pci bus */
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@ -41,9 +41,14 @@ pci_bus_alloc_resource(struct pci_bus *bus, struct resource *res,
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void *alignf_data)
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{
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int i, ret = -ENOMEM;
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resource_size_t max = -1;
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type_mask |= IORESOURCE_IO | IORESOURCE_MEM;
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/* don't allocate too high if the pref mem doesn't support 64bit*/
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if (!(res->flags & IORESOURCE_MEM_64))
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max = PCIBIOS_MAX_MEM_32;
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for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
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struct resource *r = bus->resource[i];
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if (!r)
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@ -62,7 +67,7 @@ pci_bus_alloc_resource(struct pci_bus *bus, struct resource *res,
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/* Ok, try it out.. */
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ret = allocate_resource(r, res, size,
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r->start ? : min,
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-1, align,
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max, align,
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alignf, alignf_data);
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if (ret == 0)
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break;
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@ -193,7 +193,7 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
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res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN;
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if (type == pci_bar_io) {
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l &= PCI_BASE_ADDRESS_IO_MASK;
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mask = PCI_BASE_ADDRESS_IO_MASK & 0xffff;
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mask = PCI_BASE_ADDRESS_IO_MASK & IO_SPACE_LIMIT;
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} else {
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l &= PCI_BASE_ADDRESS_MEM_MASK;
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mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
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@ -237,6 +237,8 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
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dev_printk(KERN_DEBUG, &dev->dev,
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"reg %x 64bit mmio: %pR\n", pos, res);
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}
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res->flags |= IORESOURCE_MEM_64;
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} else {
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sz = pci_size(l, sz, mask);
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@ -362,7 +364,10 @@ void __devinit pci_read_bridge_bases(struct pci_bus *child)
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}
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}
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if (base <= limit) {
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res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH;
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res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
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IORESOURCE_MEM | IORESOURCE_PREFETCH;
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if (res->flags & PCI_PREF_RANGE_TYPE_64)
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res->flags |= IORESOURCE_MEM_64;
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res->start = base;
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res->end = limit + 0xfffff;
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dev_printk(KERN_DEBUG, &dev->dev, "bridge %sbit mmio pref: %pR\n",
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@ -143,6 +143,7 @@ static void pci_setup_bridge(struct pci_bus *bus)
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struct pci_dev *bridge = bus->self;
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struct pci_bus_region region;
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u32 l, bu, lu, io_upper16;
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int pref_mem64;
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if (pci_is_enabled(bridge))
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return;
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@ -198,16 +199,22 @@ static void pci_setup_bridge(struct pci_bus *bus)
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pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
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/* Set up PREF base/limit. */
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pref_mem64 = 0;
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bu = lu = 0;
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pcibios_resource_to_bus(bridge, ®ion, bus->resource[2]);
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if (bus->resource[2]->flags & IORESOURCE_PREFETCH) {
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int width = 8;
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l = (region.start >> 16) & 0xfff0;
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l |= region.end & 0xfff00000;
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if (bus->resource[2]->flags & IORESOURCE_MEM_64) {
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pref_mem64 = 1;
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bu = upper_32_bits(region.start);
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lu = upper_32_bits(region.end);
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dev_info(&bridge->dev, " PREFETCH window: %#016llx-%#016llx\n",
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(unsigned long long)region.start,
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(unsigned long long)region.end);
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width = 16;
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}
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dev_info(&bridge->dev, " PREFETCH window: %#0*llx-%#0*llx\n",
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width, (unsigned long long)region.start,
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width, (unsigned long long)region.end);
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}
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else {
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l = 0x0000fff0;
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@ -215,9 +222,11 @@ static void pci_setup_bridge(struct pci_bus *bus)
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}
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pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
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if (pref_mem64) {
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/* Set the upper 32 bits of PREF base & limit. */
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pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
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pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
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}
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pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
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}
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@ -255,8 +264,25 @@ static void pci_bridge_check_ranges(struct pci_bus *bus)
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pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
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pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
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}
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if (pmem)
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if (pmem) {
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b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
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if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64)
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b_res[2].flags |= IORESOURCE_MEM_64;
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}
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/* double check if bridge does support 64 bit pref */
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if (b_res[2].flags & IORESOURCE_MEM_64) {
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u32 mem_base_hi, tmp;
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pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32,
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&mem_base_hi);
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pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
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0xffffffff);
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pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
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if (!tmp)
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b_res[2].flags &= ~IORESOURCE_MEM_64;
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pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
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mem_base_hi);
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}
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}
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/* Helper function for sizing routines: find first available
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@ -336,6 +362,7 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, unsigned long
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resource_size_t aligns[12]; /* Alignments from 1Mb to 2Gb */
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int order, max_order;
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struct resource *b_res = find_free_bus_resource(bus, type);
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unsigned int mem64_mask = 0;
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if (!b_res)
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return 0;
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@ -344,6 +371,9 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, unsigned long
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max_order = 0;
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size = 0;
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mem64_mask = b_res->flags & IORESOURCE_MEM_64;
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b_res->flags &= ~IORESOURCE_MEM_64;
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list_for_each_entry(dev, &bus->devices, bus_list) {
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int i;
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@ -372,6 +402,7 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, unsigned long
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aligns[order] += align;
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if (order > max_order)
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max_order = order;
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mem64_mask &= r->flags & IORESOURCE_MEM_64;
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}
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}
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@ -396,6 +427,7 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, unsigned long
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b_res->start = min_align;
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b_res->end = size + min_align - 1;
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b_res->flags |= IORESOURCE_STARTALIGN;
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b_res->flags |= mem64_mask;
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return 1;
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}
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@ -49,6 +49,8 @@ struct resource_list {
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#define IORESOURCE_SIZEALIGN 0x00020000 /* size indicates alignment */
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#define IORESOURCE_STARTALIGN 0x00040000 /* start field is alignment */
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#define IORESOURCE_MEM_64 0x00100000
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#define IORESOURCE_EXCLUSIVE 0x08000000 /* Userland may not map this resource */
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#define IORESOURCE_DISABLED 0x10000000
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#define IORESOURCE_UNSET 0x20000000
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@ -1097,6 +1097,10 @@ static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
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#include <asm/pci.h>
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#ifndef PCIBIOS_MAX_MEM_32
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#define PCIBIOS_MAX_MEM_32 (-1)
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#endif
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/* these helpers provide future and backwards compatibility
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* for accessing popular PCI BAR info */
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#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
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