From e6d66c50b997a0c4035659d8a24a3d510c593cef Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Mon, 9 May 2016 17:06:15 +0800 Subject: [PATCH 1/7] arm64: dts: fsl: Update address-cells and reg properties of cpu nodes MPIDR_EL1[63:32] value is equal to 0 for the CPUs of the LS1043A and LS2080A SoCs. The ARM CPU binding allows #address-cells to be set to 1, since MPIDR_EL1[63:32] bits are not used for CPUs identification. Update the #address-cells and reg properties accordingly. Signed-off-by: Alison Wang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 10 +++++----- arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 18 +++++++++--------- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index de0323b48b1e..37614b5a8010 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -51,7 +51,7 @@ #size-cells = <2>; cpus { - #address-cells = <2>; + #address-cells = <1>; #size-cells = <0>; /* @@ -63,28 +63,28 @@ cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; + reg = <0x0>; clocks = <&clockgen 1 0>; }; cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; + reg = <0x1>; clocks = <&clockgen 1 0>; }; cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a53"; - reg = <0x0 0x2>; + reg = <0x2>; clocks = <&clockgen 1 0>; }; cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a53"; - reg = <0x0 0x3>; + reg = <0x3>; clocks = <&clockgen 1 0>; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi index 3187c822afa3..25ff4a8f0b7a 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi @@ -51,7 +51,7 @@ #size-cells = <2>; cpus { - #address-cells = <2>; + #address-cells = <1>; #size-cells = <0>; /* @@ -65,56 +65,56 @@ cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a57"; - reg = <0x0 0x0>; + reg = <0x0>; clocks = <&clockgen 1 0>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a57"; - reg = <0x0 0x1>; + reg = <0x1>; clocks = <&clockgen 1 0>; }; cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a57"; - reg = <0x0 0x100>; + reg = <0x100>; clocks = <&clockgen 1 1>; }; cpu@101 { device_type = "cpu"; compatible = "arm,cortex-a57"; - reg = <0x0 0x101>; + reg = <0x101>; clocks = <&clockgen 1 1>; }; cpu@200 { device_type = "cpu"; compatible = "arm,cortex-a57"; - reg = <0x0 0x200>; + reg = <0x200>; clocks = <&clockgen 1 2>; }; cpu@201 { device_type = "cpu"; compatible = "arm,cortex-a57"; - reg = <0x0 0x201>; + reg = <0x201>; clocks = <&clockgen 1 2>; }; cpu@300 { device_type = "cpu"; compatible = "arm,cortex-a57"; - reg = <0x0 0x300>; + reg = <0x300>; clocks = <&clockgen 1 3>; }; cpu@301 { device_type = "cpu"; compatible = "arm,cortex-a57"; - reg = <0x0 0x301>; + reg = <0x301>; clocks = <&clockgen 1 3>; }; }; From 1cd78dd6bd252547012b16cdc56e7fb55b1800f9 Mon Sep 17 00:00:00 2001 From: Rajesh Bhagat Date: Fri, 10 Jun 2016 11:53:45 +0530 Subject: [PATCH 2/7] arm64: dts: ls2080a: Add dis_rxdet_inp3_quirk property to USB3 node Add "dis_rxdet_inp3_quirk" boolean property to USB3 node. This property is used to disable rx detection in P3 PHY mode. Signed-off-by: Rajesh Bhagat Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi index 25ff4a8f0b7a..e8a48f229fb6 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi @@ -672,6 +672,7 @@ interrupts = <0 80 0x4>; /* Level high type */ dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; + snps,dis_rxdet_inp3_quirk; }; usb1: usb3@3110000 { @@ -681,6 +682,7 @@ interrupts = <0 81 0x4>; /* Level high type */ dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; + snps,dis_rxdet_inp3_quirk; }; ccn@4000000 { From bf26225fc622d96f5ec0f40dca8a809d9685a604 Mon Sep 17 00:00:00 2001 From: Rajesh Bhagat Date: Fri, 10 Jun 2016 11:53:46 +0530 Subject: [PATCH 3/7] arm64: dts: ls1043a: Add dis_rxdet_inp3_quirk property to USB3 node Add "dis_rxdet_inp3_quirk" boolean property to USB3 node. This property is used to disable rx detection in P3 PHY mode. Signed-off-by: Rajesh Bhagat Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index 37614b5a8010..2c6832a12990 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -422,6 +422,7 @@ interrupts = <0 60 0x4>; dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; + snps,dis_rxdet_inp3_quirk; }; usb1: usb3@3000000 { @@ -430,6 +431,7 @@ interrupts = <0 61 0x4>; dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; + snps,dis_rxdet_inp3_quirk; }; usb2: usb3@3100000 { @@ -438,6 +440,7 @@ interrupts = <0 63 0x4>; dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; + snps,dis_rxdet_inp3_quirk; }; sata: sata@3200000 { From 2f082b13f2ef89548d5629d9bbf8795ed246a0ec Mon Sep 17 00:00:00 2001 From: Liu Gang Date: Tue, 7 Jun 2016 14:55:45 +0800 Subject: [PATCH 4/7] bindings: PCI: layerscape: Add 'dma-coherent' property Add 'dma-coherent' description for PCI nodes. The 'dma-coherent' indicates that the hardware IP block can ensure the coherency of the data transferred from/to the IP block. This can avoid the software cache flush/invalid actions, and improve the performance significantly. The PCI IP block of ls1043a has this capability, so adding this feature to improve the PCI performance. Signed-off-by: Liu Gang Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/pci/layerscape-pci.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index ef683b2fd23a..41e9f55a1467 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -24,6 +24,9 @@ Required properties: The first entry must be a link to the SCFG device node The second entry must be '0' or '1' based on physical PCIe controller index. This is used to get SCFG PEXN registers +- dma-coherent: Indicates that the hardware IP block can ensure the coherency + of the data transferred from/to the IP block. This can avoid the software + cache flush/invalid actions, and improve the performance significantly. Example: @@ -38,6 +41,7 @@ Example: #address-cells = <3>; #size-cells = <2>; device_type = "pci"; + dma-coherent; num-lanes = <4>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ From f8ed1d9b0f6758db7e2b65b6e88f8a923a3a22ab Mon Sep 17 00:00:00 2001 From: Liu Gang Date: Tue, 7 Jun 2016 14:55:46 +0800 Subject: [PATCH 5/7] arm64: dts: ls1043a: Add 'dma-coherent' for ls1043a PCI nodes The 'dma-coherent' indicates that the hardware IP block can ensure the coherency of the data transferred from/to the IP block. This can avoid the software cache flush/invalid actions, and improve the performance significantly. The PCI IP block of ls1043a has this capability, so adding this feature to improve the PCI performance. Signed-off-by: Liu Gang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index 2c6832a12990..c451b814ac74 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -482,6 +482,7 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; + dma-coherent; num-lanes = <4>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ @@ -506,6 +507,7 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; + dma-coherent; num-lanes = <2>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ @@ -530,6 +532,7 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; + dma-coherent; num-lanes = <2>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ From ec049f334872e98332dcf044943f3fa7cea742ee Mon Sep 17 00:00:00 2001 From: Li Yang Date: Thu, 16 Jun 2016 18:35:03 -0500 Subject: [PATCH 6/7] arm64: dts: ls1043a: Add cache nodes for cacheinfo support Adds the cache nodes and next-level-cache property for the cacheinfo to work. Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index c451b814ac74..19572d85c80d 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -65,6 +65,7 @@ compatible = "arm,cortex-a53"; reg = <0x0>; clocks = <&clockgen 1 0>; + next-level-cache = <&l2>; }; cpu1: cpu@1 { @@ -72,6 +73,7 @@ compatible = "arm,cortex-a53"; reg = <0x1>; clocks = <&clockgen 1 0>; + next-level-cache = <&l2>; }; cpu2: cpu@2 { @@ -79,6 +81,7 @@ compatible = "arm,cortex-a53"; reg = <0x2>; clocks = <&clockgen 1 0>; + next-level-cache = <&l2>; }; cpu3: cpu@3 { @@ -86,6 +89,11 @@ compatible = "arm,cortex-a53"; reg = <0x3>; clocks = <&clockgen 1 0>; + next-level-cache = <&l2>; + }; + + l2: l2-cache { + compatible = "cache"; }; }; From 2983e625bf2af422a6f55febb784fe34df834322 Mon Sep 17 00:00:00 2001 From: Li Yang Date: Thu, 16 Jun 2016 18:35:04 -0500 Subject: [PATCH 7/7] arm64: dts: ls2080a: Add cache nodes for cacheinfo support Adds the cache nodes and next-level-cache property for the cacheinfo to work. Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- .../arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi index e8a48f229fb6..21023a388c29 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi @@ -67,6 +67,7 @@ compatible = "arm,cortex-a57"; reg = <0x0>; clocks = <&clockgen 1 0>; + next-level-cache = <&cluster0_l2>; }; cpu@1 { @@ -74,6 +75,7 @@ compatible = "arm,cortex-a57"; reg = <0x1>; clocks = <&clockgen 1 0>; + next-level-cache = <&cluster0_l2>; }; cpu@100 { @@ -81,6 +83,7 @@ compatible = "arm,cortex-a57"; reg = <0x100>; clocks = <&clockgen 1 1>; + next-level-cache = <&cluster1_l2>; }; cpu@101 { @@ -88,6 +91,7 @@ compatible = "arm,cortex-a57"; reg = <0x101>; clocks = <&clockgen 1 1>; + next-level-cache = <&cluster1_l2>; }; cpu@200 { @@ -95,6 +99,7 @@ compatible = "arm,cortex-a57"; reg = <0x200>; clocks = <&clockgen 1 2>; + next-level-cache = <&cluster2_l2>; }; cpu@201 { @@ -102,6 +107,7 @@ compatible = "arm,cortex-a57"; reg = <0x201>; clocks = <&clockgen 1 2>; + next-level-cache = <&cluster2_l2>; }; cpu@300 { @@ -109,6 +115,7 @@ compatible = "arm,cortex-a57"; reg = <0x300>; clocks = <&clockgen 1 3>; + next-level-cache = <&cluster3_l2>; }; cpu@301 { @@ -116,6 +123,23 @@ compatible = "arm,cortex-a57"; reg = <0x301>; clocks = <&clockgen 1 3>; + next-level-cache = <&cluster3_l2>; + }; + + cluster0_l2: l2-cache0 { + compatible = "cache"; + }; + + cluster1_l2: l2-cache1 { + compatible = "cache"; + }; + + cluster2_l2: l2-cache2 { + compatible = "cache"; + }; + + cluster3_l2: l2-cache3 { + compatible = "cache"; }; };