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x86/cpu: Enable FSGSBASE on 64bit by default and add a chicken bit 

Now that FSGSBASE is fully supported, remove unsafe_fsgsbase, enable
FSGSBASE by default, and add nofsgsbase to disable it.

Signed-off-by: Andy Lutomirski <luto@kernel.org>
Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Cc: Ravi Shankar <ravi.v.shankar@intel.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Link: https://lkml.kernel.org/r/1557309753-24073-17-git-send-email-chang.seok.bae@intel.com
This commit is contained in:
Andy Lutomirski 2019-05-08 03:02:31 -07:00 committed by Thomas Gleixner
parent a87730cc3a
commit 2032f1f96e
2 changed files with 15 additions and 20 deletions
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3
Documentation/admin-guide/kernel-parameters.txt
View File

@ -2857,8 +2857,7 @@
no5lvl [X86-64] Disable 5-level paging mode. Forces
kernel to use 4-level paging instead.
unsafe_fsgsbase [X86] Allow FSGSBASE instructions. This will be
replaced with a nofsgsbase flag.
nofsgsbase [X86] Disables FSGSBASE instructions.
no_console_suspend
[HW] Never suspend the console

32
arch/x86/kernel/cpu/common.c
View File

@ -366,21 +366,21 @@ out:
cr4_clear_bits(X86_CR4_UMIP);
}
/*
* Temporary hack: FSGSBASE is unsafe until a few kernel code paths are
* updated. This allows us to get the kernel ready incrementally.
*
* Once all the pieces are in place, these will go away and be replaced with
* a nofsgsbase chicken flag.
*/
static bool unsafe_fsgsbase;
static __init int setup_unsafe_fsgsbase(char *arg)
static __init int x86_nofsgsbase_setup(char *arg)
{
unsafe_fsgsbase = true;
/* Require an exact match without trailing characters. */
if (strlen(arg))
return 0;
/* Do not emit a message if the feature is not present. */
if (!boot_cpu_has(X86_FEATURE_FSGSBASE))
return 1;
setup_clear_cpu_cap(X86_FEATURE_FSGSBASE);
pr_info("FSGSBASE disabled via kernel command line\n");
return 1;
}
__setup("unsafe_fsgsbase", setup_unsafe_fsgsbase);
__setup("nofsgsbase", x86_nofsgsbase_setup);
/*
* Protection Keys are not available in 32-bit mode.
@ -1387,12 +1387,8 @@ static void identify_cpu(struct cpuinfo_x86 *c)
setup_umip(c);
/* Enable FSGSBASE instructions if available. */
if (cpu_has(c, X86_FEATURE_FSGSBASE)) {
if (unsafe_fsgsbase)
cr4_set_bits(X86_CR4_FSGSBASE);
else
clear_cpu_cap(c, X86_FEATURE_FSGSBASE);
}
if (cpu_has(c, X86_FEATURE_FSGSBASE))
cr4_set_bits(X86_CR4_FSGSBASE);
/*
* The vendor-specific functions might have changed features.