ARM: 5888/1: arm: Update comments in cacheflush.h and remove unnecessary V6 and V7 comments
The comments in cacheflush.h should follow what's in struct cpu_cache_fns. The comments for V6 and V7 are unnecessary. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -154,16 +154,16 @@
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* Please note that the implementation of these, and the required
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* effects are cache-type (VIVT/VIPT/PIPT) specific.
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*
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* flush_cache_kern_all()
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* flush_kern_all()
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*
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* Unconditionally clean and invalidate the entire cache.
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*
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* flush_cache_user_mm(mm)
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* flush_user_all()
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*
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* Clean and invalidate all user space cache entries
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* before a change of page tables.
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*
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* flush_cache_user_range(start, end, flags)
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* flush_user_range(start, end, flags)
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*
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* Clean and invalidate a range of cache entries in the
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* specified address space before a change of page tables.
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@ -179,6 +179,20 @@
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* - start - virtual start address
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* - end - virtual end address
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*
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* coherent_user_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start, end. If you have non-snooping
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* Harvard caches, you need to implement this function.
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* - start - virtual start address
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* - end - virtual end address
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*
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* flush_kern_dcache_area(kaddr, size)
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*
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* Ensure that the data held in page is written back.
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* - kaddr - page address
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* - size - region size
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*
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* DMA Cache Coherency
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* ===================
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*
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@ -59,8 +59,6 @@ ENTRY(cpu_v6_proc_fin)
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* to what would be the reset vector.
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*
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* - loc - location to jump to for soft reset
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*
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* It is assumed that:
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*/
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.align 5
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ENTRY(cpu_v6_reset)
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@ -63,8 +63,6 @@ ENDPROC(cpu_v7_proc_fin)
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* to what would be the reset vector.
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*
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* - loc - location to jump to for soft reset
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*
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* It is assumed that:
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*/
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.align 5
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ENTRY(cpu_v7_reset)
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