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ux500: fix 5500 PER6 clock rate 

The DB5500 PER6 clock rate is the same as the DB8500 one, i.e. 133.33 MHz.

Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
This commit is contained in:
Rabin Vincent 2010-12-08 17:18:46 +05:30 committed by Linus Walleij
parent 22039b7cc5
commit 20e218a77f
1 changed files with 0 additions and 1 deletions
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arch/arm/mach-ux500/clock.c
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@ -578,7 +578,6 @@ int __init clk_init(void)
/* Clock tree for U5500 not implemented yet */
clk_prcc_ops.enable = clk_prcc_ops.disable = NULL;
clk_prcmu_ops.enable = clk_prcmu_ops.disable = NULL;
clk_per6clk.rate = 26000000;
clk_uartclk.rate = 36360000;
clk_sdmmcclk.rate = 99900000;
}