video: xilinxfb: Add support for little endian accesses
Dynamically detect endianess on IP and use ioread/iowrite functions instead of powerpc and microblaze specific out_be32. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
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a8f045aa07
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@ -117,6 +117,7 @@ static struct fb_var_screeninfo xilinx_fb_var = {
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#define BUS_ACCESS_FLAG 0x1 /* 1 = BUS, 0 = DCR */
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#define BUS_ACCESS_FLAG 0x1 /* 1 = BUS, 0 = DCR */
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#define LITTLE_ENDIAN_ACCESS 0x2 /* LITTLE ENDIAN IO functions */
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struct xilinxfb_drvdata {
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struct xilinxfb_drvdata {
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@ -153,14 +154,33 @@ struct xilinxfb_drvdata {
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static void xilinx_fb_out32(struct xilinxfb_drvdata *drvdata, u32 offset,
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static void xilinx_fb_out32(struct xilinxfb_drvdata *drvdata, u32 offset,
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u32 val)
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u32 val)
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{
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{
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if (drvdata->flags & BUS_ACCESS_FLAG)
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if (drvdata->flags & BUS_ACCESS_FLAG) {
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out_be32(drvdata->regs + (offset << 2), val);
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if (drvdata->flags & LITTLE_ENDIAN_ACCESS)
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iowrite32(val, drvdata->regs + (offset << 2));
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else
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iowrite32be(val, drvdata->regs + (offset << 2));
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}
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#ifdef CONFIG_PPC_DCR
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#ifdef CONFIG_PPC_DCR
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else
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else
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dcr_write(drvdata->dcr_host, offset, val);
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dcr_write(drvdata->dcr_host, offset, val);
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#endif
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#endif
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}
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}
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static u32 xilinx_fb_in32(struct xilinxfb_drvdata *drvdata, u32 offset)
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{
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if (drvdata->flags & BUS_ACCESS_FLAG) {
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if (drvdata->flags & LITTLE_ENDIAN_ACCESS)
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return ioread32(drvdata->regs + (offset << 2));
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else
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return ioread32be(drvdata->regs + (offset << 2));
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}
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#ifdef CONFIG_PPC_DCR
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else
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return dcr_read(drvdata->dcr_host, offset);
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#endif
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return 0;
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}
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static int
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static int
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xilinx_fb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue,
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xilinx_fb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue,
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unsigned transp, struct fb_info *fbi)
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unsigned transp, struct fb_info *fbi)
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@ -271,6 +291,12 @@ static int xilinxfb_assign(struct platform_device *pdev,
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/* Tell the hardware where the frame buffer is */
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/* Tell the hardware where the frame buffer is */
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xilinx_fb_out32(drvdata, REG_FB_ADDR, drvdata->fb_phys);
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xilinx_fb_out32(drvdata, REG_FB_ADDR, drvdata->fb_phys);
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rc = xilinx_fb_in32(drvdata, REG_FB_ADDR);
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/* Endianess detection */
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if (rc != drvdata->fb_phys) {
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drvdata->flags |= LITTLE_ENDIAN_ACCESS;
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xilinx_fb_out32(drvdata, REG_FB_ADDR, drvdata->fb_phys);
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}
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/* Turn on the display */
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/* Turn on the display */
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drvdata->reg_ctrl_default = REG_CTRL_ENABLE;
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drvdata->reg_ctrl_default = REG_CTRL_ENABLE;
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