diff --git a/Documentation/devicetree/bindings/arm/omap/ctrl.txt b/Documentation/devicetree/bindings/arm/omap/ctrl.txt new file mode 100644 index 000000000000..3a4e5901ce31 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/omap/ctrl.txt @@ -0,0 +1,79 @@ +OMAP Control Module bindings + +Control Module contains miscellaneous features under it based on SoC type. +Pincontrol is one common feature, and it has a specialized support +described in [1]. Typically some clock nodes are also under control module. +Syscon is used to share register level access to drivers external to +control module driver itself. + +See [2] for documentation about clock/clockdomain nodes. + +[1] Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt +[2] Documentation/devicetree/bindings/clock/ti/* + +Required properties: +- compatible: Must be one of: + "ti,am3-scm" + "ti,am4-scm" + "ti,dm814-scrm" + "ti,dm816-scrm" + "ti,omap2-scm" + "ti,omap3-scm" + "ti,omap4-scm-core" + "ti,omap4-scm-padconf-core" + "ti,omap5-scm-core" + "ti,omap5-scm-padconf-core" + "ti,dra7-scm-core" +- reg: Contains Control Module register address range + (base address and length) + +Optional properties: +- clocks: clocks for this module +- clockdomains: clockdomains for this module + +Examples: + +scm: scm@2000 { + compatible = "ti,omap3-scm", "simple-bus"; + reg = <0x2000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2000 0x2000>; + + omap3_pmx_core: pinmux@30 { + compatible = "ti,omap3-padconf", + "pinctrl-single"; + reg = <0x30 0x230>; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0xff1f>; + }; + + scm_conf: scm_conf@270 { + compatible = "syscon"; + reg = <0x270 0x330>; + #address-cells = <1>; + #size-cells = <1>; + + scm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + scm_clockdomains: clockdomains { + }; +} + +&scm_clocks { + mcbsp5_mux_fck: mcbsp5_mux_fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&core_96m_fck>, <&mcbsp_clks>; + ti,bit-shift = <4>; + reg = <0x02d8>; + }; +}; diff --git a/Documentation/devicetree/bindings/arm/omap/l4.txt b/Documentation/devicetree/bindings/arm/omap/l4.txt new file mode 100644 index 000000000000..b4f8a16e7e3b --- /dev/null +++ b/Documentation/devicetree/bindings/arm/omap/l4.txt @@ -0,0 +1,26 @@ +L4 interconnect bindings + +These bindings describe the OMAP SoCs L4 interconnect bus. + +Required properties: +- compatible : Should be "ti,omap2-l4" for OMAP2 family l4 core bus + Should be "ti,omap2-l4-wkup" for OMAP2 family l4 wkup bus + Should be "ti,omap3-l4-core" for OMAP3 family l4 core bus + Should be "ti,omap4-l4-cfg" for OMAP4 family l4 cfg bus + Should be "ti,omap4-l4-wkup" for OMAP4 family l4 wkup bus + Should be "ti,omap5-l4-cfg" for OMAP5 family l4 cfg bus + Should be "ti,omap5-l4-wkup" for OMAP5 family l4 wkup bus + Should be "ti,dra7-l4-cfg" for DRA7 family l4 cfg bus + Should be "ti,dra7-l4-wkup" for DRA7 family l4 wkup bus + Should be "ti,am3-l4-wkup" for AM33xx family l4 wkup bus + Should be "ti,am4-l4-wkup" for AM43xx family l4 wkup bus +- ranges : contains the IO map range for the bus + +Examples: + +l4: l4@48000000 { + compatible "ti,omap2-l4", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x48000000 0x100000>; +}; diff --git a/Documentation/devicetree/bindings/arm/omap/prcm.txt b/Documentation/devicetree/bindings/arm/omap/prcm.txt index 79074dac684a..3eb6d7afff14 100644 --- a/Documentation/devicetree/bindings/arm/omap/prcm.txt +++ b/Documentation/devicetree/bindings/arm/omap/prcm.txt @@ -10,14 +10,10 @@ documentation about the individual clock/clockdomain nodes. Required properties: - compatible: Must be one of: "ti,am3-prcm" - "ti,am3-scrm" "ti,am4-prcm" - "ti,am4-scrm" "ti,omap2-prcm" - "ti,omap2-scrm" "ti,omap3-prm" "ti,omap3-cm" - "ti,omap3-scrm" "ti,omap4-cm1" "ti,omap4-prm" "ti,omap4-cm2" @@ -29,6 +25,8 @@ Required properties: "ti,dra7-prm" "ti,dra7-cm-core-aon" "ti,dra7-cm-core" + "ti,dm814-prcm" + "ti,dm816-prcm" - reg: Contains PRCM module register address range (base address and length) - clocks: clocks for this module diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi index 712edce7d6fb..236c78a3c6ca 100644 --- a/arch/arm/boot/dts/am33xx-clocks.dtsi +++ b/arch/arm/boot/dts/am33xx-clocks.dtsi @@ -7,7 +7,7 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -&scrm_clocks { +&scm_clocks { sys_clkin_ck: sys_clkin_ck { #clock-cells = <0>; compatible = "ti,mux-clock"; diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index acd37057bca9..21fcc440fc1a 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -83,20 +83,6 @@ }; }; - am33xx_control_module: control_module@4a002000 { - compatible = "syscon"; - reg = <0x44e10000 0x7fc>; - }; - - am33xx_pinmux: pinmux@44e10800 { - compatible = "pinctrl-single"; - reg = <0x44e10800 0x0238>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x7f>; - }; - /* * XXX: Use a flat representation of the AM33XX interconnect. * The real AM33XX interconnect network is quite complex. Since @@ -111,35 +97,56 @@ ranges; ti,hwmods = "l3_main"; - prcm: prcm@44e00000 { - compatible = "ti,am3-prcm"; - reg = <0x44e00000 0x4000>; + l4_wkup: l4_wkup@44c00000 { + compatible = "ti,am3-l4-wkup", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x44c00000 0x280000>; - prcm_clocks: clocks { + prcm: prcm@200000 { + compatible = "ti,am3-prcm"; + reg = <0x200000 0x4000>; + + prcm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + prcm_clockdomains: clockdomains { + }; + }; + + scm: scm@210000 { + compatible = "ti,am3-scm", "simple-bus"; + reg = <0x210000 0x2000>; #address-cells = <1>; - #size-cells = <0>; + #size-cells = <1>; + ranges = <0 0x210000 0x2000>; + + am33xx_pinmux: pinmux@800 { + compatible = "pinctrl-single"; + reg = <0x800 0x238>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x7f>; + }; + + scm_conf: scm_conf@0 { + compatible = "syscon"; + reg = <0x0 0x800>; + #address-cells = <1>; + #size-cells = <1>; + + scm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + scm_clockdomains: clockdomains { + }; }; - - prcm_clockdomains: clockdomains { - }; - }; - - scrm: scrm@44e10000 { - compatible = "ti,am3-scrm"; - reg = <0x44e10000 0x2000>; - - scrm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - scrm_clockdomains: clockdomains { - }; - }; - - cm: syscon@44e10000 { - compatible = "ti,am33xx-controlmodule", "syscon"; - reg = <0x44e10000 0x800>; }; intc: interrupt-controller@48200000 { @@ -350,7 +357,7 @@ reg = <0x481cc000 0x2000>; clocks = <&dcan0_fck>; clock-names = "fck"; - syscon-raminit = <&am33xx_control_module 0x644 0>; + syscon-raminit = <&scm_conf 0x644 0>; interrupts = <52>; status = "disabled"; }; @@ -361,7 +368,7 @@ reg = <0x481d0000 0x2000>; clocks = <&dcan1_fck>; clock-names = "fck"; - syscon-raminit = <&am33xx_control_module 0x644 1>; + syscon-raminit = <&scm_conf 0x644 1>; interrupts = <55>; status = "disabled"; }; @@ -720,7 +727,7 @@ */ interrupts = <40 41 42 43>; ranges; - syscon = <&cm>; + syscon = <&scm_conf>; status = "disabled"; davinci_mdio: mdio@4a101000 { diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi index c90724bded10..f164dce08755 100644 --- a/arch/arm/boot/dts/am3517.dtsi +++ b/arch/arm/boot/dts/am3517.dtsi @@ -31,7 +31,7 @@ status = "disabled"; reg = <0x5c000000 0x30000>; interrupts = <67 68 69 70>; - syscon = <&omap3_scm_general>; + syscon = <&scm_conf>; ti,davinci-ctrl-reg-offset = <0x10000>; ti,davinci-ctrl-mod-reg-offset = <0>; ti,davinci-ctrl-ram-offset = <0x20000>; diff --git a/arch/arm/boot/dts/am35xx-clocks.dtsi b/arch/arm/boot/dts/am35xx-clocks.dtsi index df489d310b50..518b8fde88b0 100644 --- a/arch/arm/boot/dts/am35xx-clocks.dtsi +++ b/arch/arm/boot/dts/am35xx-clocks.dtsi @@ -7,7 +7,7 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -&scrm_clocks { +&scm_clocks { emac_ick: emac_ick { #clock-cells = <0>; compatible = "ti,am35xx-gate-clock"; diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index 286e31790e29..2f6f0c2040db 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -57,22 +57,6 @@ cache-level = <2>; }; - am43xx_control_module: control_module@4a002000 { - compatible = "syscon"; - reg = <0x44e10000 0x7f4>; - }; - - am43xx_pinmux: pinmux@44e10800 { - compatible = "ti,am437-padconf", "pinctrl-single"; - reg = <0x44e10800 0x31c>; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - ocp { compatible = "ti,am4372-l3-noc", "simple-bus"; #address-cells = <1>; @@ -84,29 +68,58 @@ interrupts = , ; - prcm: prcm@44df0000 { - compatible = "ti,am4-prcm"; - reg = <0x44df0000 0x11000>; + l4_wkup: l4_wkup@44c00000 { + compatible = "ti,am4-l4-wkup", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x44c00000 0x287000>; - prcm_clocks: clocks { + prcm: prcm@1f0000 { + compatible = "ti,am4-prcm"; + reg = <0x1f0000 0x11000>; + + prcm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + prcm_clockdomains: clockdomains { + }; + }; + + scm: scm@210000 { + compatible = "ti,am4-scm", "simple-bus"; + reg = <0x210000 0x4000>; #address-cells = <1>; - #size-cells = <0>; - }; + #size-cells = <1>; + ranges = <0 0x210000 0x4000>; - prcm_clockdomains: clockdomains { - }; - }; + am43xx_pinmux: pinmux@800 { + compatible = "ti,am437-padconf", + "pinctrl-single"; + reg = <0x800 0x31c>; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; - scrm: scrm@44e10000 { - compatible = "ti,am4-scrm"; - reg = <0x44e10000 0x2000>; + scm_conf: scm_conf@0 { + compatible = "syscon"; + reg = <0x0 0x800>; + #address-cells = <1>; + #size-cells = <1>; - scrm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; + scm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + }; - scrm_clockdomains: clockdomains { + scm_clockdomains: clockdomains { + }; }; }; @@ -933,7 +946,7 @@ clocks = <&dcan0_fck>; clock-names = "fck"; reg = <0x481cc000 0x2000>; - syscon-raminit = <&am43xx_control_module 0x644 0>; + syscon-raminit = <&scm_conf 0x644 0>; interrupts = ; status = "disabled"; }; @@ -944,7 +957,7 @@ clocks = <&dcan1_fck>; clock-names = "fck"; reg = <0x481d0000 0x2000>; - syscon-raminit = <&am43xx_control_module 0x644 1>; + syscon-raminit = <&scm_conf 0x644 1>; interrupts = ; status = "disabled"; }; diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index 257c099c347e..72f01bb5d61c 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -69,7 +69,48 @@ }; }; - am43xx_pinmux: pinmux@44e10800 { + matrix_keypad: matrix_keypad@0 { + compatible = "gpio-matrix-keypad"; + debounce-delay-ms = <5>; + col-scan-delay-us = <2>; + + row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12 */ + &gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13 */ + &gpio0 14 GPIO_ACTIVE_HIGH /* Bank0, pin14 */ + &gpio0 15 GPIO_ACTIVE_HIGH>; /* Bank0, pin15 */ + + col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH /* Bank3, pin9 */ + &gpio3 10 GPIO_ACTIVE_HIGH /* Bank3, pin10 */ + &gpio2 18 GPIO_ACTIVE_HIGH /* Bank2, pin18 */ + &gpio2 19 GPIO_ACTIVE_HIGH>; /* Bank2, pin19 */ + + linux,keymap = <0x00000201 /* P1 */ + 0x01000204 /* P4 */ + 0x02000207 /* P7 */ + 0x0300020a /* NUMERIC_STAR */ + 0x00010202 /* P2 */ + 0x01010205 /* P5 */ + 0x02010208 /* P8 */ + 0x03010200 /* P0 */ + 0x00020203 /* P3 */ + 0x01020206 /* P6 */ + 0x02020209 /* P9 */ + 0x0302020b /* NUMERIC_POUND */ + 0x00030067 /* UP */ + 0x0103006a /* RIGHT */ + 0x0203006c /* DOWN */ + 0x03030069>; /* LEFT */ + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 51 53 56 62 75 101 152 255>; + default-brightness-level = <8>; + }; +}; + +&am43xx_pinmux { cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1 */ @@ -279,47 +320,6 @@ 0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) >; }; - }; - - matrix_keypad: matrix_keypad@0 { - compatible = "gpio-matrix-keypad"; - debounce-delay-ms = <5>; - col-scan-delay-us = <2>; - - row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12 */ - &gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13 */ - &gpio0 14 GPIO_ACTIVE_HIGH /* Bank0, pin14 */ - &gpio0 15 GPIO_ACTIVE_HIGH>; /* Bank0, pin15 */ - - col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH /* Bank3, pin9 */ - &gpio3 10 GPIO_ACTIVE_HIGH /* Bank3, pin10 */ - &gpio2 18 GPIO_ACTIVE_HIGH /* Bank2, pin18 */ - &gpio2 19 GPIO_ACTIVE_HIGH>; /* Bank2, pin19 */ - - linux,keymap = <0x00000201 /* P1 */ - 0x01000204 /* P4 */ - 0x02000207 /* P7 */ - 0x0300020a /* NUMERIC_STAR */ - 0x00010202 /* P2 */ - 0x01010205 /* P5 */ - 0x02010208 /* P8 */ - 0x03010200 /* P0 */ - 0x00020203 /* P3 */ - 0x01020206 /* P6 */ - 0x02020209 /* P9 */ - 0x0302020b /* NUMERIC_POUND */ - 0x00030067 /* UP */ - 0x0103006a /* RIGHT */ - 0x0203006c /* DOWN */ - 0x03030069>; /* LEFT */ - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 51 53 56 62 75 101 152 255>; - default-brightness-level = <8>; - }; }; &mmc1 { diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi index c7dc9dab93a4..44869aa72642 100644 --- a/arch/arm/boot/dts/am43xx-clocks.dtsi +++ b/arch/arm/boot/dts/am43xx-clocks.dtsi @@ -7,7 +7,7 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -&scrm_clocks { +&scm_clocks { sys_clkin_ck: sys_clkin_ck { #clock-cells = <0>; compatible = "ti,mux-clock"; diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 098916f93811..a4dec49d0278 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -94,17 +94,101 @@ interrupts = , ; - prm: prm@4ae06000 { - compatible = "ti,dra7-prm"; - reg = <0x4ae06000 0x3000>; - interrupts = ; + l4_cfg: l4@4a000000 { + compatible = "ti,dra7-l4-cfg", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4a000000 0x22c000>; - prm_clocks: clocks { + scm: scm@2000 { + compatible = "ti,dra7-scm-core", "simple-bus"; + reg = <0x2000 0x2000>; #address-cells = <1>; - #size-cells = <0>; + #size-cells = <1>; + ranges = <0 0x2000 0x2000>; + + scm_conf: scm_conf@0 { + compatible = "syscon"; + reg = <0x0 0x1400>; + #address-cells = <1>; + #size-cells = <1>; + + pbias_regulator: pbias_regulator { + compatible = "ti,pbias-omap"; + reg = <0xe00 0x4>; + syscon = <&scm_conf>; + pbias_mmc_reg: pbias_mmc_omap5 { + regulator-name = "pbias_mmc_omap5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + }; + }; + }; + + dra7_pmx_core: pinmux@1400 { + compatible = "ti,dra7-padconf", + "pinctrl-single"; + reg = <0x1400 0x0464>; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x3fffffff>; + }; }; - prm_clockdomains: clockdomains { + cm_core_aon: cm_core_aon@5000 { + compatible = "ti,dra7-cm-core-aon"; + reg = <0x5000 0x2000>; + + cm_core_aon_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + cm_core_aon_clockdomains: clockdomains { + }; + }; + + cm_core: cm_core@8000 { + compatible = "ti,dra7-cm-core"; + reg = <0x8000 0x3000>; + + cm_core_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + cm_core_clockdomains: clockdomains { + }; + }; + }; + + l4_wkup: l4@4ae00000 { + compatible = "ti,dra7-l4-wkup", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4ae00000 0x3f000>; + + counter32k: counter@4000 { + compatible = "ti,omap-counter32k"; + reg = <0x4000 0x40>; + ti,hwmods = "counter_32k"; + }; + + prm: prm@6000 { + compatible = "ti,dra7-prm"; + reg = <0x6000 0x3000>; + interrupts = ; + + prm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + prm_clockdomains: clockdomains { + }; }; }; @@ -189,38 +273,6 @@ #thermal-sensor-cells = <1>; }; - cm_core_aon: cm_core_aon@4a005000 { - compatible = "ti,dra7-cm-core-aon"; - reg = <0x4a005000 0x2000>; - - cm_core_aon_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - cm_core_aon_clockdomains: clockdomains { - }; - }; - - cm_core: cm_core@4a008000 { - compatible = "ti,dra7-cm-core"; - reg = <0x4a008000 0x3000>; - - cm_core_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - cm_core_clockdomains: clockdomains { - }; - }; - - counter32k: counter@4ae04000 { - compatible = "ti,omap-counter32k"; - reg = <0x4ae04000 0x40>; - ti,hwmods = "counter_32k"; - }; - dra7_ctrl_core: ctrl_core@4a002000 { compatible = "syscon"; reg = <0x4a002000 0x6d0>; @@ -231,28 +283,6 @@ reg = <0x4a002e00 0x7c>; }; - pbias_regulator: pbias_regulator { - compatible = "ti,pbias-omap"; - reg = <0 0x4>; - syscon = <&dra7_ctrl_general>; - pbias_mmc_reg: pbias_mmc_omap5 { - regulator-name = "pbias_mmc_omap5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - }; - }; - - dra7_pmx_core: pinmux@4a003400 { - compatible = "ti,dra7-padconf", "pinctrl-single"; - reg = <0x4a003400 0x0464>; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x3fffffff>; - }; - sdma: dma-controller@4a056000 { compatible = "ti,omap4430-sdma"; reg = <0x4a056000 0x1000>; @@ -1422,7 +1452,7 @@ compatible = "ti,dra7-d_can"; ti,hwmods = "dcan1"; reg = <0x4ae3c000 0x2000>; - syscon-raminit = <&dra7_ctrl_core 0x558 0>; + syscon-raminit = <&scm_conf 0x558 0>; interrupts = ; clocks = <&dcan1_sys_clk_mux>; status = "disabled"; @@ -1432,7 +1462,7 @@ compatible = "ti,dra7-d_can"; ti,hwmods = "dcan2"; reg = <0x48480000 0x2000>; - syscon-raminit = <&dra7_ctrl_core 0x558 1>; + syscon-raminit = <&scm_conf 0x558 1>; interrupts = ; clocks = <&sys_clkin1>; status = "disabled"; diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi index e2b2e93d7b61..5b9a376cc31e 100644 --- a/arch/arm/boot/dts/omap2420.dtsi +++ b/arch/arm/boot/dts/omap2420.dtsi @@ -14,45 +14,63 @@ compatible = "ti,omap2420", "ti,omap2"; ocp { - prcm: prcm@48008000 { - compatible = "ti,omap2-prcm"; - reg = <0x48008000 0x1000>; - - prcm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - prcm_clockdomains: clockdomains { - }; - }; - - scrm: scrm@48000000 { - compatible = "ti,omap2-scrm"; - reg = <0x48000000 0x1000>; - - scrm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - scrm_clockdomains: clockdomains { - }; - }; - - counter32k: counter@48004000 { - compatible = "ti,omap-counter32k"; - reg = <0x48004000 0x20>; - ti,hwmods = "counter_32k"; - }; - - omap2420_pmx: pinmux@48000030 { - compatible = "ti,omap2420-padconf", "pinctrl-single"; - reg = <0x48000030 0x0113>; + l4: l4@48000000 { + compatible = "ti,omap2-l4", "simple-bus"; #address-cells = <1>; - #size-cells = <0>; - pinctrl-single,register-width = <8>; - pinctrl-single,function-mask = <0x3f>; + #size-cells = <1>; + ranges = <0 0x48000000 0x100000>; + + prcm: prcm@8000 { + compatible = "ti,omap2-prcm"; + reg = <0x8000 0x1000>; + + prcm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + prcm_clockdomains: clockdomains { + }; + }; + + scm: scm@0 { + compatible = "ti,omap2-scm", "simple-bus"; + reg = <0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x1000>; + + omap2420_pmx: pinmux@30 { + compatible = "ti,omap2420-padconf", + "pinctrl-single"; + reg = <0x30 0x0113>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-single,register-width = <8>; + pinctrl-single,function-mask = <0x3f>; + }; + + scm_conf: scm_conf@270 { + compatible = "syscon"; + reg = <0x270 0x100>; + #address-cells = <1>; + #size-cells = <1>; + + scm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + scm_clockdomains: clockdomains { + }; + }; + + counter32k: counter@4000 { + compatible = "ti,omap-counter32k"; + reg = <0x4000 0x20>; + ti,hwmods = "counter_32k"; + }; }; gpio1: gpio@48018000 { diff --git a/arch/arm/boot/dts/omap2430-clocks.dtsi b/arch/arm/boot/dts/omap2430-clocks.dtsi index 805f75df1cf2..93fed68839b9 100644 --- a/arch/arm/boot/dts/omap2430-clocks.dtsi +++ b/arch/arm/boot/dts/omap2430-clocks.dtsi @@ -8,12 +8,12 @@ * published by the Free Software Foundation. */ -&scrm_clocks { +&scm_clocks { mcbsp3_mux_fck: mcbsp3_mux_fck { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&func_96m_ck>, <&mcbsp_clks>; - reg = <0x02e8>; + reg = <0x78>; }; mcbsp3_fck: mcbsp3_fck { @@ -27,7 +27,7 @@ compatible = "ti,composite-mux-clock"; clocks = <&func_96m_ck>, <&mcbsp_clks>; ti,bit-shift = <2>; - reg = <0x02e8>; + reg = <0x78>; }; mcbsp4_fck: mcbsp4_fck { @@ -41,7 +41,7 @@ compatible = "ti,composite-mux-clock"; clocks = <&func_96m_ck>, <&mcbsp_clks>; ti,bit-shift = <4>; - reg = <0x02e8>; + reg = <0x78>; }; mcbsp5_fck: mcbsp5_fck { diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi index 0dc8de2782b1..11a7963be003 100644 --- a/arch/arm/boot/dts/omap2430.dtsi +++ b/arch/arm/boot/dts/omap2430.dtsi @@ -14,60 +14,73 @@ compatible = "ti,omap2430", "ti,omap2"; ocp { - prcm: prcm@49006000 { - compatible = "ti,omap2-prcm"; - reg = <0x49006000 0x1000>; - - prcm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - prcm_clockdomains: clockdomains { - }; - }; - - scrm: scrm@49002000 { - compatible = "ti,omap2-scrm"; - reg = <0x49002000 0x1000>; - - scrm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - scrm_clockdomains: clockdomains { - }; - }; - - counter32k: counter@49020000 { - compatible = "ti,omap-counter32k"; - reg = <0x49020000 0x20>; - ti,hwmods = "counter_32k"; - }; - - omap2430_pmx: pinmux@49002030 { - compatible = "ti,omap2430-padconf", "pinctrl-single"; - reg = <0x49002030 0x0154>; + l4_wkup: l4_wkup@49000000 { + compatible = "ti,omap2-l4-wkup", "simple-bus"; #address-cells = <1>; - #size-cells = <0>; - pinctrl-single,register-width = <8>; - pinctrl-single,function-mask = <0x3f>; - }; + #size-cells = <1>; + ranges = <0 0x49000000 0x31000>; - omap2_scm_general: tisyscon@49002270 { - compatible = "syscon"; - reg = <0x49002270 0x240>; - }; + prcm: prcm@6000 { + compatible = "ti,omap2-prcm"; + reg = <0x6000 0x1000>; - pbias_regulator: pbias_regulator { - compatible = "ti,pbias-omap"; - reg = <0x230 0x4>; - syscon = <&omap2_scm_general>; - pbias_mmc_reg: pbias_mmc_omap2430 { - regulator-name = "pbias_mmc_omap2430"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; + prcm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + prcm_clockdomains: clockdomains { + }; + }; + + scm: scm@2000 { + compatible = "ti,omap2-scm", "simple-bus"; + reg = <0x2000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2000 0x1000>; + + omap2430_pmx: pinmux@30 { + compatible = "ti,omap2430-padconf", + "pinctrl-single"; + reg = <0x30 0x0154>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-single,register-width = <8>; + pinctrl-single,function-mask = <0x3f>; + }; + + scm_conf: scm_conf@270 { + compatible = "syscon"; + reg = <0x270 0x240>; + #address-cells = <1>; + #size-cells = <1>; + + scm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + pbias_regulator: pbias_regulator { + compatible = "ti,pbias-omap"; + reg = <0x230 0x4>; + syscon = <&scm_conf>; + pbias_mmc_reg: pbias_mmc_omap2430 { + regulator-name = "pbias_mmc_omap2430"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + }; + }; + }; + + scm_clockdomains: clockdomains { + }; + }; + + counter32k: counter@20000 { + compatible = "ti,omap-counter32k"; + reg = <0x20000 0x20>; + ti,hwmods = "counter_32k"; }; }; diff --git a/arch/arm/boot/dts/omap24xx-clocks.dtsi b/arch/arm/boot/dts/omap24xx-clocks.dtsi index a1365ca926eb..63965b876973 100644 --- a/arch/arm/boot/dts/omap24xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap24xx-clocks.dtsi @@ -7,13 +7,13 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -&scrm_clocks { +&scm_clocks { mcbsp1_mux_fck: mcbsp1_mux_fck { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&func_96m_ck>, <&mcbsp_clks>; ti,bit-shift = <2>; - reg = <0x0274>; + reg = <0x4>; }; mcbsp1_fck: mcbsp1_fck { @@ -27,7 +27,7 @@ compatible = "ti,composite-mux-clock"; clocks = <&func_96m_ck>, <&mcbsp_clks>; ti,bit-shift = <6>; - reg = <0x0274>; + reg = <0x4>; }; mcbsp2_fck: mcbsp2_fck { diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index 01b71111bd55..b28791ade27a 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -87,6 +87,60 @@ ranges; ti,hwmods = "l3_main"; + l4_core: l4@48000000 { + compatible = "ti,omap3-l4-core", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x48000000 0x1000000>; + + scm: scm@2000 { + compatible = "ti,omap3-scm", "simple-bus"; + reg = <0x2000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2000 0x2000>; + + omap3_pmx_core: pinmux@30 { + compatible = "ti,omap3-padconf", + "pinctrl-single"; + reg = <0x30 0x238>; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0xff1f>; + }; + + scm_conf: scm_conf@270 { + compatible = "syscon"; + reg = <0x270 0x330>; + #address-cells = <1>; + #size-cells = <1>; + + scm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + scm_clockdomains: clockdomains { + }; + + omap3_pmx_wkup: pinmux@a00 { + compatible = "ti,omap3-padconf", + "pinctrl-single"; + reg = <0xa00 0x5c>; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0xff1f>; + }; + }; + }; + aes: aes@480c5000 { compatible = "ti,omap3-aes"; ti,hwmods = "aes"; @@ -121,19 +175,6 @@ }; }; - scrm: scrm@48002000 { - compatible = "ti,omap3-scrm"; - reg = <0x48002000 0x2000>; - - scrm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - scrm_clockdomains: clockdomains { - }; - }; - counter32k: counter@48320000 { compatible = "ti,omap-counter32k"; reg = <0x48320000 0x20>; @@ -159,37 +200,10 @@ #dma-requests = <96>; }; - omap3_pmx_core: pinmux@48002030 { - compatible = "ti,omap3-padconf", "pinctrl-single"; - reg = <0x48002030 0x0238>; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0xff1f>; - }; - - omap3_pmx_wkup: pinmux@48002a00 { - compatible = "ti,omap3-padconf", "pinctrl-single"; - reg = <0x48002a00 0x5c>; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0xff1f>; - }; - - omap3_scm_general: tisyscon@48002270 { - compatible = "syscon"; - reg = <0x48002270 0x2f0>; - }; - pbias_regulator: pbias_regulator { compatible = "ti,pbias-omap"; reg = <0x2b0 0x4>; - syscon = <&omap3_scm_general>; + syscon = <&scm_conf>; pbias_mmc_reg: pbias_mmc_omap2430 { regulator-name = "pbias_mmc_omap2430"; regulator-min-microvolt = <1800000>; diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi index 5c375003bad1..bbba5bdc4bc9 100644 --- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi +++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi @@ -79,13 +79,14 @@ clock-div = <1>; }; }; -&scrm_clocks { + +&scm_clocks { mcbsp5_mux_fck: mcbsp5_mux_fck { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&core_96m_fck>, <&mcbsp_clks>; ti,bit-shift = <4>; - reg = <0x02d8>; + reg = <0x68>; }; mcbsp5_fck: mcbsp5_fck { @@ -99,7 +100,7 @@ compatible = "ti,composite-mux-clock"; clocks = <&core_96m_fck>, <&mcbsp_clks>; ti,bit-shift = <2>; - reg = <0x0274>; + reg = <0x04>; }; mcbsp1_fck: mcbsp1_fck { @@ -113,7 +114,7 @@ compatible = "ti,composite-mux-clock"; clocks = <&per_96m_fck>, <&mcbsp_clks>; ti,bit-shift = <6>; - reg = <0x0274>; + reg = <0x04>; }; mcbsp2_fck: mcbsp2_fck { @@ -126,7 +127,7 @@ #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&per_96m_fck>, <&mcbsp_clks>; - reg = <0x02d8>; + reg = <0x68>; }; mcbsp3_fck: mcbsp3_fck { @@ -140,7 +141,7 @@ compatible = "ti,composite-mux-clock"; clocks = <&per_96m_fck>, <&mcbsp_clks>; ti,bit-shift = <2>; - reg = <0x02d8>; + reg = <0x68>; }; mcbsp4_fck: mcbsp4_fck { diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 074147cebae4..546681a9cb65 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -114,99 +114,141 @@ interrupts = , ; - cm1: cm1@4a004000 { - compatible = "ti,omap4-cm1"; - reg = <0x4a004000 0x2000>; - - cm1_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - cm1_clockdomains: clockdomains { - }; - }; - - prm: prm@4a306000 { - compatible = "ti,omap4-prm"; - reg = <0x4a306000 0x3000>; - interrupts = ; - - prm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - prm_clockdomains: clockdomains { - }; - }; - - cm2: cm2@4a008000 { - compatible = "ti,omap4-cm2"; - reg = <0x4a008000 0x3000>; - - cm2_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - cm2_clockdomains: clockdomains { - }; - }; - - scrm: scrm@4a30a000 { - compatible = "ti,omap4-scrm"; - reg = <0x4a30a000 0x2000>; - - scrm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - scrm_clockdomains: clockdomains { - }; - }; - - counter32k: counter@4a304000 { - compatible = "ti,omap-counter32k"; - reg = <0x4a304000 0x20>; - ti,hwmods = "counter_32k"; - }; - - omap4_pmx_core: pinmux@4a100040 { - compatible = "ti,omap4-padconf", "pinctrl-single"; - reg = <0x4a100040 0x0196>; + l4_cfg: l4@4a000000 { + compatible = "ti,omap4-l4-cfg", "simple-bus"; #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0x7fff>; - }; - omap4_pmx_wkup: pinmux@4a31e040 { - compatible = "ti,omap4-padconf", "pinctrl-single"; - reg = <0x4a31e040 0x0038>; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0x7fff>; - }; + #size-cells = <1>; + ranges = <0 0x4a000000 0x1000000>; - omap4_padconf_global: tisyscon@4a1005a0 { - compatible = "syscon"; - reg = <0x4a1005a0 0x170>; - }; + cm1: cm1@4000 { + compatible = "ti,omap4-cm1"; + reg = <0x4000 0x2000>; - pbias_regulator: pbias_regulator { - compatible = "ti,pbias-omap"; - reg = <0x60 0x4>; - syscon = <&omap4_padconf_global>; - pbias_mmc_reg: pbias_mmc_omap4 { - regulator-name = "pbias_mmc_omap4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; + cm1_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + cm1_clockdomains: clockdomains { + }; + }; + + cm2: cm2@8000 { + compatible = "ti,omap4-cm2"; + reg = <0x8000 0x3000>; + + cm2_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + cm2_clockdomains: clockdomains { + }; + }; + + omap4_scm_core: scm@2000 { + compatible = "ti,omap4-scm-core", "simple-bus"; + reg = <0x2000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2000 0x1000>; + + scm_conf: scm_conf@0 { + compatible = "syscon"; + reg = <0x0 0x800>; + #address-cells = <1>; + #size-cells = <1>; + }; + }; + + omap4_padconf_core: scm@100000 { + compatible = "ti,omap4-scm-padconf-core", + "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x100000 0x1000>; + + omap4_pmx_core: pinmux@40 { + compatible = "ti,omap4-padconf", + "pinctrl-single"; + reg = <0x40 0x0196>; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0x7fff>; + }; + + omap4_padconf_global: omap4_padconf_global@5a0 { + compatible = "syscon"; + reg = <0x5a0 0x170>; + #address-cells = <1>; + #size-cells = <1>; + + pbias_regulator: pbias_regulator { + compatible = "ti,pbias-omap"; + reg = <0x60 0x4>; + syscon = <&omap4_padconf_global>; + pbias_mmc_reg: pbias_mmc_omap4 { + regulator-name = "pbias_mmc_omap4"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + }; + }; + }; + }; + + l4_wkup: l4@300000 { + compatible = "ti,omap4-l4-wkup", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x300000 0x40000>; + + counter32k: counter@4000 { + compatible = "ti,omap-counter32k"; + reg = <0x4000 0x20>; + ti,hwmods = "counter_32k"; + }; + + prm: prm@6000 { + compatible = "ti,omap4-prm"; + reg = <0x6000 0x3000>; + interrupts = ; + + prm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + prm_clockdomains: clockdomains { + }; + }; + + scrm: scrm@a000 { + compatible = "ti,omap4-scrm"; + reg = <0xa000 0x2000>; + + scrm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + scrm_clockdomains: clockdomains { + }; + }; + + omap4_pmx_wkup: pinmux@1e040 { + compatible = "ti,omap4-padconf", + "pinctrl-single"; + reg = <0x1e040 0x0038>; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0x7fff>; + }; }; }; diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index b321fdf42c9f..326a429dcce4 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -129,99 +129,141 @@ interrupts = , ; - prm: prm@4ae06000 { - compatible = "ti,omap5-prm"; - reg = <0x4ae06000 0x3000>; - interrupts = ; - - prm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - prm_clockdomains: clockdomains { - }; - }; - - cm_core_aon: cm_core_aon@4a004000 { - compatible = "ti,omap5-cm-core-aon"; - reg = <0x4a004000 0x2000>; - - cm_core_aon_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - cm_core_aon_clockdomains: clockdomains { - }; - }; - - scrm: scrm@4ae0a000 { - compatible = "ti,omap5-scrm"; - reg = <0x4ae0a000 0x2000>; - - scrm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - scrm_clockdomains: clockdomains { - }; - }; - - cm_core: cm_core@4a008000 { - compatible = "ti,omap5-cm-core"; - reg = <0x4a008000 0x3000>; - - cm_core_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - cm_core_clockdomains: clockdomains { - }; - }; - - counter32k: counter@4ae04000 { - compatible = "ti,omap-counter32k"; - reg = <0x4ae04000 0x40>; - ti,hwmods = "counter_32k"; - }; - - omap5_pmx_core: pinmux@4a002840 { - compatible = "ti,omap5-padconf", "pinctrl-single"; - reg = <0x4a002840 0x01b6>; + l4_cfg: l4@4a000000 { + compatible = "ti,omap5-l4-cfg", "simple-bus"; #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0x7fff>; + #size-cells = <1>; + ranges = <0 0x4a000000 0x22a000>; + + scm_core: scm@2000 { + compatible = "ti,omap5-scm-core", "simple-bus"; + reg = <0x2000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2000 0x800>; + + scm_conf: scm_conf@0 { + compatible = "syscon"; + reg = <0x0 0x800>; + #address-cells = <1>; + #size-cells = <1>; + }; + }; + + scm_padconf_core: scm@2800 { + compatible = "ti,omap5-scm-padconf-core", + "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2800 0x800>; + + omap5_pmx_core: pinmux@40 { + compatible = "ti,omap5-padconf", + "pinctrl-single"; + reg = <0x40 0x01b6>; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0x7fff>; + }; + + omap5_padconf_global: omap5_padconf_global@5a0 { + compatible = "syscon"; + reg = <0x5a0 0xec>; + #address-cells = <1>; + #size-cells = <1>; + + pbias_regulator: pbias_regulator { + compatible = "ti,pbias-omap"; + reg = <0x60 0x4>; + syscon = <&omap5_padconf_global>; + pbias_mmc_reg: pbias_mmc_omap5 { + regulator-name = "pbias_mmc_omap5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + }; + }; + }; + }; + + cm_core_aon: cm_core_aon@4000 { + compatible = "ti,omap5-cm-core-aon"; + reg = <0x4000 0x2000>; + + cm_core_aon_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + cm_core_aon_clockdomains: clockdomains { + }; + }; + + cm_core: cm_core@8000 { + compatible = "ti,omap5-cm-core"; + reg = <0x8000 0x3000>; + + cm_core_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + cm_core_clockdomains: clockdomains { + }; + }; }; - omap5_pmx_wkup: pinmux@4ae0c840 { - compatible = "ti,omap5-padconf", "pinctrl-single"; - reg = <0x4ae0c840 0x0038>; + + l4_wkup: l4@4ae00000 { + compatible = "ti,omap5-l4-wkup", "simple-bus"; #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0x7fff>; - }; + #size-cells = <1>; + ranges = <0 0x4ae00000 0x2b000>; - omap5_padconf_global: tisyscon@4a002da0 { - compatible = "syscon"; - reg = <0x4A002da0 0xec>; - }; + counter32k: counter@4000 { + compatible = "ti,omap-counter32k"; + reg = <0x4000 0x40>; + ti,hwmods = "counter_32k"; + }; - pbias_regulator: pbias_regulator { - compatible = "ti,pbias-omap"; - reg = <0x60 0x4>; - syscon = <&omap5_padconf_global>; - pbias_mmc_reg: pbias_mmc_omap5 { - regulator-name = "pbias_mmc_omap5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; + prm: prm@6000 { + compatible = "ti,omap5-prm"; + reg = <0x6000 0x3000>; + interrupts = ; + + prm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + prm_clockdomains: clockdomains { + }; + }; + + scrm: scrm@a000 { + compatible = "ti,omap5-scrm"; + reg = <0xa000 0x2000>; + + scrm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + scrm_clockdomains: clockdomains { + }; + }; + + omap5_pmx_wkup: pinmux@c840 { + compatible = "ti,omap5-padconf", + "pinctrl-single"; + reg = <0xc840 0x0038>; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0x7fff>; }; }; diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 6124db5c37ae..a699d7169307 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -23,6 +23,9 @@ #include #include #include +#include +#include +#include #include #include @@ -72,30 +75,110 @@ struct ti_clk_features ti_clk_features; static bool clkdm_control = true; static LIST_HEAD(clk_hw_omap_clocks); -void __iomem *clk_memmaps[CLK_MAX_MEMMAPS]; + +struct clk_iomap { + struct regmap *regmap; + void __iomem *mem; +}; + +static struct clk_iomap *clk_memmaps[CLK_MAX_MEMMAPS]; + +static void clk_memmap_writel(u32 val, void __iomem *reg) +{ + struct clk_omap_reg *r = (struct clk_omap_reg *)® + struct clk_iomap *io = clk_memmaps[r->index]; + + if (io->regmap) + regmap_write(io->regmap, r->offset, val); + else + writel_relaxed(val, io->mem + r->offset); +} + +static u32 clk_memmap_readl(void __iomem *reg) +{ + u32 val; + struct clk_omap_reg *r = (struct clk_omap_reg *)® + struct clk_iomap *io = clk_memmaps[r->index]; + + if (io->regmap) + regmap_read(io->regmap, r->offset, &val); + else + val = readl_relaxed(io->mem + r->offset); + + return val; +} void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg) { - if (clk->flags & MEMMAP_ADDRESSING) { - struct clk_omap_reg *r = (struct clk_omap_reg *)® - writel_relaxed(val, clk_memmaps[r->index] + r->offset); - } else { + if (WARN_ON_ONCE(!(clk->flags & MEMMAP_ADDRESSING))) writel_relaxed(val, reg); - } + else + clk_memmap_writel(val, reg); } u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg) { - u32 val; + if (WARN_ON_ONCE(!(clk->flags & MEMMAP_ADDRESSING))) + return readl_relaxed(reg); + else + return clk_memmap_readl(reg); +} - if (clk->flags & MEMMAP_ADDRESSING) { - struct clk_omap_reg *r = (struct clk_omap_reg *)® - val = readl_relaxed(clk_memmaps[r->index] + r->offset); - } else { - val = readl_relaxed(reg); - } +static struct ti_clk_ll_ops omap_clk_ll_ops = { + .clk_readl = clk_memmap_readl, + .clk_writel = clk_memmap_writel, +}; - return val; +/** + * omap2_clk_provider_init - initialize a clock provider + * @match_table: DT device table to match for devices to init + * @np: device node pointer for the this clock provider + * @index: index for the clock provider + + @syscon: syscon regmap pointer + * @mem: iomem pointer for the clock provider memory area, only used if + * syscon is not provided + * + * Initializes a clock provider module (CM/PRM etc.), registering + * the memory mapping at specified index and initializing the + * low level driver infrastructure. Returns 0 in success. + */ +int __init omap2_clk_provider_init(struct device_node *np, int index, + struct regmap *syscon, void __iomem *mem) +{ + struct clk_iomap *io; + + ti_clk_ll_ops = &omap_clk_ll_ops; + + io = kzalloc(sizeof(*io), GFP_KERNEL); + + io->regmap = syscon; + io->mem = mem; + + clk_memmaps[index] = io; + + ti_dt_clk_init_provider(np, index); + + return 0; +} + +/** + * omap2_clk_legacy_provider_init - initialize a legacy clock provider + * @index: index for the clock provider + * @mem: iomem pointer for the clock provider memory area + * + * Initializes a legacy clock provider memory mapping. + */ +void __init omap2_clk_legacy_provider_init(int index, void __iomem *mem) +{ + struct clk_iomap *io; + + ti_clk_ll_ops = &omap_clk_ll_ops; + + io = memblock_virt_alloc(sizeof(*io), 0); + + io->mem = mem; + + clk_memmaps[index] = io; } /* diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index a56742f96000..652ed0ab86ec 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -271,10 +271,14 @@ extern const struct clksel_rate div_1_3_rates[]; extern const struct clksel_rate div_1_4_rates[]; extern const struct clksel_rate div31_1to31_rates[]; -extern void __iomem *clk_memmaps[]; - extern int omap2_clkops_enable_clkdm(struct clk_hw *hw); extern void omap2_clkops_disable_clkdm(struct clk_hw *hw); +struct regmap; + +int __init omap2_clk_provider_init(struct device_node *np, int index, + struct regmap *syscon, void __iomem *mem); +void __init omap2_clk_legacy_provider_init(int index, void __iomem *mem); + void __init ti_clk_init_features(void); #endif diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h index 6222e87a79b6..1fe3e6b833d2 100644 --- a/arch/arm/mach-omap2/cm.h +++ b/arch/arm/mach-omap2/cm.h @@ -70,6 +70,8 @@ int omap_cm_module_enable(u8 mode, u8 part, u16 inst, u16 clkctrl_offs); int omap_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs); extern int cm_register(struct cm_ll_data *cld); extern int cm_unregister(struct cm_ll_data *cld); +int omap_cm_init(void); +int omap2_cm_base_init(void); # endif diff --git a/arch/arm/mach-omap2/cm2xxx.c b/arch/arm/mach-omap2/cm2xxx.c index ef62ac9dcd05..3e5fd3587eb1 100644 --- a/arch/arm/mach-omap2/cm2xxx.c +++ b/arch/arm/mach-omap2/cm2xxx.c @@ -393,7 +393,7 @@ static struct cm_ll_data omap2xxx_cm_ll_data = { .wait_module_ready = &omap2xxx_cm_wait_module_ready, }; -int __init omap2xxx_cm_init(void) +int __init omap2xxx_cm_init(const struct omap_prcm_init_data *data) { return cm_register(&omap2xxx_cm_ll_data); } diff --git a/arch/arm/mach-omap2/cm2xxx.h b/arch/arm/mach-omap2/cm2xxx.h index 83b6c597b0e1..7b8c79c0ce27 100644 --- a/arch/arm/mach-omap2/cm2xxx.h +++ b/arch/arm/mach-omap2/cm2xxx.h @@ -63,7 +63,7 @@ extern u32 omap2xxx_cm_get_core_pll_config(void); extern void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core, u32 mdm); -extern int __init omap2xxx_cm_init(void); +int __init omap2xxx_cm_init(const struct omap_prcm_init_data *data); #endif diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c index cc5aac784278..7b181f929525 100644 --- a/arch/arm/mach-omap2/cm33xx.c +++ b/arch/arm/mach-omap2/cm33xx.c @@ -352,7 +352,7 @@ static struct cm_ll_data am33xx_cm_ll_data = { .module_disable = &am33xx_cm_module_disable, }; -int __init am33xx_cm_init(void) +int __init am33xx_cm_init(const struct omap_prcm_init_data *data) { return cm_register(&am33xx_cm_ll_data); } diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h index 046b4b2bc9d9..a91f7d282455 100644 --- a/arch/arm/mach-omap2/cm33xx.h +++ b/arch/arm/mach-omap2/cm33xx.h @@ -19,6 +19,7 @@ #include "cm.h" #include "cm-regbits-33xx.h" +#include "prcm-common.h" /* CM base address */ #define AM33XX_CM_BASE 0x44e00000 @@ -374,6 +375,6 @@ #ifndef __ASSEMBLER__ -int am33xx_cm_init(void); +int am33xx_cm_init(const struct omap_prcm_init_data *data); #endif /* ASSEMBLER */ #endif diff --git a/arch/arm/mach-omap2/cm3xxx.c b/arch/arm/mach-omap2/cm3xxx.c index ebead8f035f9..187fa4386718 100644 --- a/arch/arm/mach-omap2/cm3xxx.c +++ b/arch/arm/mach-omap2/cm3xxx.c @@ -671,8 +671,9 @@ static struct cm_ll_data omap3xxx_cm_ll_data = { .wait_module_ready = &omap3xxx_cm_wait_module_ready, }; -int __init omap3xxx_cm_init(void) +int __init omap3xxx_cm_init(const struct omap_prcm_init_data *data) { + omap2_clk_legacy_provider_init(TI_CLKM_CM, cm_base + OMAP3430_IVA2_MOD); return cm_register(&omap3xxx_cm_ll_data); } diff --git a/arch/arm/mach-omap2/cm3xxx.h b/arch/arm/mach-omap2/cm3xxx.h index 734a8581c0c4..bc444e2080a1 100644 --- a/arch/arm/mach-omap2/cm3xxx.h +++ b/arch/arm/mach-omap2/cm3xxx.h @@ -72,7 +72,7 @@ extern void omap3_cm_save_context(void); extern void omap3_cm_restore_context(void); extern void omap3_cm_save_scratchpad_contents(u32 *ptr); -extern int __init omap3xxx_cm_init(void); +int __init omap3xxx_cm_init(const struct omap_prcm_init_data *data); #endif diff --git a/arch/arm/mach-omap2/cm44xx.h b/arch/arm/mach-omap2/cm44xx.h index 728d06a4af19..309a4c913448 100644 --- a/arch/arm/mach-omap2/cm44xx.h +++ b/arch/arm/mach-omap2/cm44xx.h @@ -23,7 +23,6 @@ #define OMAP4_CM_CLKSTCTRL 0x0000 #define OMAP4_CM_STATICDEP 0x0004 -void omap_cm_base_init(void); -int omap4_cm_init(void); +int omap4_cm_init(const struct omap_prcm_init_data *data); #endif diff --git a/arch/arm/mach-omap2/cm_common.c b/arch/arm/mach-omap2/cm_common.c index 8fe02fcedc48..23e8bcec34e3 100644 --- a/arch/arm/mach-omap2/cm_common.c +++ b/arch/arm/mach-omap2/cm_common.c @@ -15,10 +15,14 @@ #include #include #include +#include +#include #include "cm2xxx.h" #include "cm3xxx.h" +#include "cm33xx.h" #include "cm44xx.h" +#include "clock.h" /* * cm_ll_data: function pointers to SoC-specific implementations of @@ -33,6 +37,9 @@ void __iomem *cm_base; /* cm2_base: base virtual address of the CM2 IP block (OMAP44xx only) */ void __iomem *cm2_base; +#define CM_NO_CLOCKS 0x1 +#define CM_SINGLE_INSTANCE 0x2 + /** * omap2_set_globals_cm - set the CM/CM2 base addresses (for early use) * @cm: CM base virtual address @@ -212,3 +219,152 @@ int cm_unregister(struct cm_ll_data *cld) return 0; } + +#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ + defined(CONFIG_SOC_DRA7XX) +static struct omap_prcm_init_data cm_data __initdata = { + .index = TI_CLKM_CM, + .init = omap4_cm_init, +}; + +static struct omap_prcm_init_data cm2_data __initdata = { + .index = TI_CLKM_CM2, + .init = omap4_cm_init, +}; +#endif + +#ifdef CONFIG_ARCH_OMAP2 +static struct omap_prcm_init_data omap2_prcm_data __initdata = { + .index = TI_CLKM_CM, + .init = omap2xxx_cm_init, + .flags = CM_NO_CLOCKS | CM_SINGLE_INSTANCE, +}; +#endif + +#ifdef CONFIG_ARCH_OMAP3 +static struct omap_prcm_init_data omap3_cm_data __initdata = { + .index = TI_CLKM_CM, + .init = omap3xxx_cm_init, + .flags = CM_SINGLE_INSTANCE, + + /* + * IVA2 offset is a negative value, must offset the cm_base address + * by this to get it to positive side on the iomap + */ + .offset = -OMAP3430_IVA2_MOD, +}; +#endif + +#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_TI81XX) +static struct omap_prcm_init_data am3_prcm_data __initdata = { + .index = TI_CLKM_CM, + .flags = CM_NO_CLOCKS | CM_SINGLE_INSTANCE, + .init = am33xx_cm_init, +}; +#endif + +#ifdef CONFIG_SOC_AM43XX +static struct omap_prcm_init_data am4_prcm_data __initdata = { + .index = TI_CLKM_CM, + .flags = CM_NO_CLOCKS | CM_SINGLE_INSTANCE, + .init = omap4_cm_init, +}; +#endif + +static const struct of_device_id omap_cm_dt_match_table[] __initconst = { +#ifdef CONFIG_ARCH_OMAP2 + { .compatible = "ti,omap2-prcm", .data = &omap2_prcm_data }, +#endif +#ifdef CONFIG_ARCH_OMAP3 + { .compatible = "ti,omap3-cm", .data = &omap3_cm_data }, +#endif +#ifdef CONFIG_ARCH_OMAP4 + { .compatible = "ti,omap4-cm1", .data = &cm_data }, + { .compatible = "ti,omap4-cm2", .data = &cm2_data }, +#endif +#ifdef CONFIG_SOC_OMAP5 + { .compatible = "ti,omap5-cm-core-aon", .data = &cm_data }, + { .compatible = "ti,omap5-cm-core", .data = &cm2_data }, +#endif +#ifdef CONFIG_SOC_DRA7XX + { .compatible = "ti,dra7-cm-core-aon", .data = &cm_data }, + { .compatible = "ti,dra7-cm-core", .data = &cm2_data }, +#endif +#ifdef CONFIG_SOC_AM33XX + { .compatible = "ti,am3-prcm", .data = &am3_prcm_data }, +#endif +#ifdef CONFIG_SOC_AM43XX + { .compatible = "ti,am4-prcm", .data = &am4_prcm_data }, +#endif +#ifdef CONFIG_SOC_TI81XX + { .compatible = "ti,dm814-prcm", .data = &am3_prcm_data }, + { .compatible = "ti,dm816-prcm", .data = &am3_prcm_data }, +#endif + { } +}; + +/** + * omap2_cm_base_init - initialize iomappings for the CM drivers + * + * Detects and initializes the iomappings for the CM driver, based + * on the DT data. Returns 0 in success, negative error value + * otherwise. + */ +int __init omap2_cm_base_init(void) +{ + struct device_node *np; + const struct of_device_id *match; + struct omap_prcm_init_data *data; + void __iomem *mem; + + for_each_matching_node_and_match(np, omap_cm_dt_match_table, &match) { + data = (struct omap_prcm_init_data *)match->data; + + mem = of_iomap(np, 0); + if (!mem) + return -ENOMEM; + + if (data->index == TI_CLKM_CM) + cm_base = mem + data->offset; + + if (data->index == TI_CLKM_CM2) + cm2_base = mem + data->offset; + + data->mem = mem; + + data->np = np; + + if (data->init && (data->flags & CM_SINGLE_INSTANCE || + (cm_base && cm2_base))) + data->init(data); + } + + return 0; +} + +/** + * omap_cm_init - low level init for the CM drivers + * + * Initializes the low level clock infrastructure for CM drivers. + * Returns 0 in success, negative error value in failure. + */ +int __init omap_cm_init(void) +{ + struct device_node *np; + const struct of_device_id *match; + const struct omap_prcm_init_data *data; + int ret; + + for_each_matching_node_and_match(np, omap_cm_dt_match_table, &match) { + data = match->data; + + if (data->flags & CM_NO_CLOCKS) + continue; + + ret = omap2_clk_provider_init(np, data->index, NULL, data->mem); + if (ret) + return ret; + } + + return 0; +} diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c index 95a8cff66aff..2c0e07ed6b99 100644 --- a/arch/arm/mach-omap2/cminst44xx.c +++ b/arch/arm/mach-omap2/cminst44xx.c @@ -63,7 +63,7 @@ static void __iomem *_cm_bases[OMAP4_MAX_PRCM_PARTITIONS]; * Populates the base addresses of the _cm_bases * array used for read/write of cm module registers. */ -void omap_cm_base_init(void) +static void omap_cm_base_init(void) { _cm_bases[OMAP4430_PRM_PARTITION] = prm_base; _cm_bases[OMAP4430_CM1_PARTITION] = cm_base; @@ -514,8 +514,10 @@ static struct cm_ll_data omap4xxx_cm_ll_data = { .module_disable = &omap4_cminst_module_disable, }; -int __init omap4_cm_init(void) +int __init omap4_cm_init(const struct omap_prcm_init_data *data) { + omap_cm_base_init(); + return cm_register(&omap4xxx_cm_ll_data); } diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index da041b4ab29c..af95a624fe71 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c @@ -14,6 +14,9 @@ #include #include +#include +#include +#include #include "soc.h" #include "iomap.h" @@ -25,13 +28,15 @@ #include "sdrc.h" #include "pm.h" #include "control.h" +#include "clock.h" /* Used by omap3_ctrl_save_padconf() */ #define START_PADCONF_SAVE 0x2 #define PADCONF_SAVE_DONE 0x1 static void __iomem *omap2_ctrl_base; -static void __iomem *omap4_ctrl_pad_base; +static s16 omap2_ctrl_offset; +static struct regmap *omap2_ctrl_syscon; #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) struct omap3_scratchpad { @@ -133,66 +138,79 @@ struct omap3_control_regs { static struct omap3_control_regs control_context; #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ -#define OMAP_CTRL_REGADDR(reg) (omap2_ctrl_base + (reg)) -#define OMAP4_CTRL_PAD_REGADDR(reg) (omap4_ctrl_pad_base + (reg)) - -void __init omap2_set_globals_control(void __iomem *ctrl, - void __iomem *ctrl_pad) +void __init omap2_set_globals_control(void __iomem *ctrl) { omap2_ctrl_base = ctrl; - omap4_ctrl_pad_base = ctrl_pad; -} - -void __iomem *omap_ctrl_base_get(void) -{ - return omap2_ctrl_base; } u8 omap_ctrl_readb(u16 offset) { - return readb_relaxed(OMAP_CTRL_REGADDR(offset)); + u32 val; + u8 byte_offset = offset & 0x3; + + val = omap_ctrl_readl(offset); + + return (val >> (byte_offset * 8)) & 0xff; } u16 omap_ctrl_readw(u16 offset) { - return readw_relaxed(OMAP_CTRL_REGADDR(offset)); + u32 val; + u16 byte_offset = offset & 0x2; + + val = omap_ctrl_readl(offset); + + return (val >> (byte_offset * 8)) & 0xffff; } u32 omap_ctrl_readl(u16 offset) { - return readl_relaxed(OMAP_CTRL_REGADDR(offset)); + u32 val; + + offset &= 0xfffc; + if (!omap2_ctrl_syscon) + val = readl_relaxed(omap2_ctrl_base + offset); + else + regmap_read(omap2_ctrl_syscon, omap2_ctrl_offset + offset, + &val); + + return val; } void omap_ctrl_writeb(u8 val, u16 offset) { - writeb_relaxed(val, OMAP_CTRL_REGADDR(offset)); + u32 tmp; + u8 byte_offset = offset & 0x3; + + tmp = omap_ctrl_readl(offset); + + tmp &= 0xffffffff ^ (0xff << (byte_offset * 8)); + tmp |= val << (byte_offset * 8); + + omap_ctrl_writel(tmp, offset); } void omap_ctrl_writew(u16 val, u16 offset) { - writew_relaxed(val, OMAP_CTRL_REGADDR(offset)); + u32 tmp; + u8 byte_offset = offset & 0x2; + + tmp = omap_ctrl_readl(offset); + + tmp &= 0xffffffff ^ (0xffff << (byte_offset * 8)); + tmp |= val << (byte_offset * 8); + + omap_ctrl_writel(tmp, offset); } void omap_ctrl_writel(u32 val, u16 offset) { - writel_relaxed(val, OMAP_CTRL_REGADDR(offset)); -} - -/* - * On OMAP4 control pad are not addressable from control - * core base. So the common omap_ctrl_read/write APIs breaks - * Hence export separate APIs to manage the omap4 pad control - * registers. This APIs will work only for OMAP4 - */ - -u32 omap4_ctrl_pad_readl(u16 offset) -{ - return readl_relaxed(OMAP4_CTRL_PAD_REGADDR(offset)); -} - -void omap4_ctrl_pad_writel(u32 val, u16 offset) -{ - writel_relaxed(val, OMAP4_CTRL_PAD_REGADDR(offset)); + offset &= 0xfffc; + if (!omap2_ctrl_syscon) + writel_relaxed(val, omap2_ctrl_base + offset); + else + regmap_write(omap2_ctrl_syscon, omap2_ctrl_offset + offset, + val); } #ifdef CONFIG_ARCH_OMAP3 @@ -611,3 +629,120 @@ void __init omap3_ctrl_init(void) omap3_ctrl_setup_d2d_padconf(); } #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ + +struct control_init_data { + int index; + s16 offset; +}; + +static struct control_init_data ctrl_data = { + .index = TI_CLKM_CTRL, +}; + +static const struct control_init_data omap2_ctrl_data = { + .index = TI_CLKM_CTRL, + .offset = -OMAP2_CONTROL_GENERAL, +}; + +static const struct of_device_id omap_scrm_dt_match_table[] = { + { .compatible = "ti,am3-scm", .data = &ctrl_data }, + { .compatible = "ti,am4-scm", .data = &ctrl_data }, + { .compatible = "ti,omap2-scm", .data = &omap2_ctrl_data }, + { .compatible = "ti,omap3-scm", .data = &omap2_ctrl_data }, + { .compatible = "ti,dm816-scrm", .data = &ctrl_data }, + { .compatible = "ti,omap4-scm-core", .data = &ctrl_data }, + { .compatible = "ti,omap5-scm-core", .data = &ctrl_data }, + { .compatible = "ti,dra7-scm-core", .data = &ctrl_data }, + { } +}; + +/** + * omap2_control_base_init - initialize iomappings for the control driver + * + * Detects and initializes the iomappings for the control driver, based + * on the DT data. Returns 0 in success, negative error value + * otherwise. + */ +int __init omap2_control_base_init(void) +{ + struct device_node *np; + const struct of_device_id *match; + struct control_init_data *data; + + for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) { + data = (struct control_init_data *)match->data; + + omap2_ctrl_base = of_iomap(np, 0); + if (!omap2_ctrl_base) + return -ENOMEM; + + omap2_ctrl_offset = data->offset; + } + + return 0; +} + +/** + * omap_control_init - low level init for the control driver + * + * Initializes the low level clock infrastructure for control driver. + * Returns 0 in success, negative error value in failure. + */ +int __init omap_control_init(void) +{ + struct device_node *np, *scm_conf; + const struct of_device_id *match; + const struct omap_prcm_init_data *data; + int ret; + struct regmap *syscon; + + for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) { + data = match->data; + + /* + * Check if we have scm_conf node, if yes, use this to + * access clock registers. + */ + scm_conf = of_get_child_by_name(np, "scm_conf"); + + if (scm_conf) { + syscon = syscon_node_to_regmap(scm_conf); + + if (IS_ERR(syscon)) + return PTR_ERR(syscon); + + omap2_ctrl_syscon = syscon; + + if (of_get_child_by_name(scm_conf, "clocks")) { + ret = omap2_clk_provider_init(scm_conf, + data->index, + syscon, NULL); + if (ret) + return ret; + } + + iounmap(omap2_ctrl_base); + omap2_ctrl_base = NULL; + } else { + /* No scm_conf found, direct access */ + ret = omap2_clk_provider_init(np, data->index, NULL, + omap2_ctrl_base); + if (ret) + return ret; + } + } + + return 0; +} + +/** + * omap3_control_legacy_iomap_init - legacy iomap init for clock providers + * + * Legacy iomap init for clock provider. Needed only by legacy boot mode, + * where the base addresses are not parsed from DT, but still required + * by the clock driver to be setup properly. + */ +void __init omap3_control_legacy_iomap_init(void) +{ + omap2_clk_legacy_provider_init(TI_CLKM_SCRM, omap2_ctrl_base); +} diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h index b8a487181210..80d2b7d8e36e 100644 --- a/arch/arm/mach-omap2/control.h +++ b/arch/arm/mach-omap2/control.h @@ -440,15 +440,12 @@ #ifndef __ASSEMBLY__ #ifdef CONFIG_ARCH_OMAP2PLUS -extern void __iomem *omap_ctrl_base_get(void); extern u8 omap_ctrl_readb(u16 offset); extern u16 omap_ctrl_readw(u16 offset); extern u32 omap_ctrl_readl(u16 offset); -extern u32 omap4_ctrl_pad_readl(u16 offset); extern void omap_ctrl_writeb(u8 val, u16 offset); extern void omap_ctrl_writew(u16 val, u16 offset); extern void omap_ctrl_writel(u32 val, u16 offset); -extern void omap4_ctrl_pad_writel(u32 val, u16 offset); extern void omap3_save_scratchpad_contents(void); extern void omap3_clear_scratchpad_contents(void); @@ -464,10 +461,11 @@ extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode); extern void omap3630_ctrl_disable_rta(void); extern int omap3_ctrl_save_padconf(void); void omap3_ctrl_init(void); -extern void omap2_set_globals_control(void __iomem *ctrl, - void __iomem *ctrl_pad); +int omap2_control_base_init(void); +int omap_control_init(void); +void omap2_set_globals_control(void __iomem *ctrl); +void __init omap3_control_legacy_iomap_init(void); #else -#define omap_ctrl_base_get() 0 #define omap_ctrl_readb(x) 0 #define omap_ctrl_readw(x) 0 #define omap_ctrl_readl(x) 0 diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c index 7a050f9c37ff..f492ae147c6a 100644 --- a/arch/arm/mach-omap2/display.c +++ b/arch/arm/mach-omap2/display.c @@ -26,6 +26,8 @@ #include #include #include +#include +#include #include