perf: add qcom l2 cache perf events driver
Adds perf events support for L2 cache PMU. The L2 cache PMU driver is named 'l2cache_0' and can be used with perf events to profile L2 events such as cache hits and misses on Qualcomm Technologies processors. Reviewed-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Neil Leeder <nleeder@codeaurora.org> [will: minimise nesting in l2_cache_associate_cpu_with_cluster] [will: use kstrtoul for unsigned long, remove redunant .owner setting] Signed-off-by: Will Deacon <will.deacon@arm.com>
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Qualcomm Technologies Level-2 Cache Performance Monitoring Unit (PMU)
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=====================================================================
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This driver supports the L2 cache clusters found in Qualcomm Technologies
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Centriq SoCs. There are multiple physical L2 cache clusters, each with their
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own PMU. Each cluster has one or more CPUs associated with it.
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There is one logical L2 PMU exposed, which aggregates the results from
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the physical PMUs.
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The driver provides a description of its available events and configuration
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options in sysfs, see /sys/devices/l2cache_0.
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The "format" directory describes the format of the events.
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Events can be envisioned as a 2-dimensional array. Each column represents
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a group of events. There are 8 groups. Only one entry from each
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group can be in use at a time. If multiple events from the same group
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are specified, the conflicting events cannot be counted at the same time.
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Events are specified as 0xCCG, where CC is 2 hex digits specifying
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the code (array row) and G specifies the group (column) 0-7.
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In addition there is a cycle counter event specified by the value 0xFE
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which is outside the above scheme.
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The driver provides a "cpumask" sysfs attribute which contains a mask
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consisting of one CPU per cluster which will be used to handle all the PMU
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events on that cluster.
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Examples for use with perf:
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perf stat -e l2cache_0/config=0x001/,l2cache_0/config=0x042/ -a sleep 1
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perf stat -e l2cache_0/config=0xfe/ -C 2 sleep 1
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The driver does not support sampling, therefore "perf record" will
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not work. Per-task perf sessions are not supported.
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@ -12,6 +12,15 @@ config ARM_PMU
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Say y if you want to use CPU performance monitors on ARM-based
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Say y if you want to use CPU performance monitors on ARM-based
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systems.
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systems.
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config QCOM_L2_PMU
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bool "Qualcomm Technologies L2-cache PMU"
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depends on ARCH_QCOM && ARM64 && PERF_EVENTS && ACPI
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help
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Provides support for the L2 cache performance monitor unit (PMU)
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in Qualcomm Technologies processors.
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Adds the L2 cache PMU into the perf events subsystem for
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monitoring L2 cache events.
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config XGENE_PMU
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config XGENE_PMU
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depends on PERF_EVENTS && ARCH_XGENE
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depends on PERF_EVENTS && ARCH_XGENE
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bool "APM X-Gene SoC PMU"
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bool "APM X-Gene SoC PMU"
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@ -1,2 +1,3 @@
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obj-$(CONFIG_ARM_PMU) += arm_pmu.o
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obj-$(CONFIG_ARM_PMU) += arm_pmu.o
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obj-$(CONFIG_QCOM_L2_PMU) += qcom_l2_pmu.o
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obj-$(CONFIG_XGENE_PMU) += xgene_pmu.o
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obj-$(CONFIG_XGENE_PMU) += xgene_pmu.o
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File diff suppressed because it is too large
Load Diff
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@ -138,6 +138,7 @@ enum cpuhp_state {
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CPUHP_AP_PERF_ARM_CCI_ONLINE,
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CPUHP_AP_PERF_ARM_CCI_ONLINE,
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CPUHP_AP_PERF_ARM_CCN_ONLINE,
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CPUHP_AP_PERF_ARM_CCN_ONLINE,
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CPUHP_AP_PERF_ARM_L2X0_ONLINE,
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CPUHP_AP_PERF_ARM_L2X0_ONLINE,
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CPUHP_AP_PERF_ARM_QCOM_L2_ONLINE,
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CPUHP_AP_WORKQUEUE_ONLINE,
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CPUHP_AP_WORKQUEUE_ONLINE,
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CPUHP_AP_RCUTREE_ONLINE,
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CPUHP_AP_RCUTREE_ONLINE,
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CPUHP_AP_ONLINE_DYN,
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CPUHP_AP_ONLINE_DYN,
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