Merge master.kernel.org:/pub/scm/linux/kernel/git/paulus/powerpc
* master.kernel.org:/pub/scm/linux/kernel/git/paulus/powerpc: (116 commits) [POWERPC] Add export of vgacon_remap_base [POWERPC] Remove bogus comment about page_is_ram [POWERPC] windfarm: don't die on suspend thread signal [POWERPC] Fix comment in kernel/irq.c [POWERPC] ppc: Fix booke watchdog initialization [POWERPC] PPC: Use ARRAY_SIZE macro when appropriate [POWERPC] Use ARRAY_SIZE macro when appropriate [POWERPC] Fix ppc64's writing to struct file_operations [POWERPC] ppc: use syslog macro for the printk log level [POWERPC] ppc: cs4218_tdm remove extra brace [POWERPC] Add mpc52xx/lite5200 PCI support [POWERPC] Only use H_BULK_REMOVE if the firmware supports it [POWERPC] Fixup error handling when emulating a floating point instruction [POWERPC] Enable interrupts if we are doing fp math emulation [POWERPC] Added kprobes support to ppc32 [POWERPC] Make pSeries use the H_BULK_REMOVE hypervisor call [POWERPC] Clear RI bit in MSR before restoring r13 when returning to userspace [POWERPC] Fix performance monitor exception [POWERPC] Compile fixes for arch/powerpc dcr code [POWERPC] Maple: use mmio nvram ...
This commit is contained in:
Linus Torvalds
commit
21eb4fa170
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|
@ -173,6 +173,11 @@ config PPC_86xx
|
|||
help
|
||||
The Freescale E600 SoCs have 74xx cores.
|
||||
|
||||
config PPC_8xx
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||||
bool "Freescale 8xx"
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||||
select FSL_SOC
|
||||
select 8xx
|
||||
|
||||
config 40x
|
||||
bool "AMCC 40x"
|
||||
select PPC_DCR_NATIVE
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||||
|
|
@ -181,8 +186,6 @@ config 44x
|
|||
bool "AMCC 44x"
|
||||
select PPC_DCR_NATIVE
|
||||
|
||||
config 8xx
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||||
bool "Freescale 8xx"
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||||
|
||||
config E200
|
||||
bool "Freescale e200"
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||||
|
|
@ -210,6 +213,10 @@ config POWER4
|
|||
config 6xx
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||||
bool
|
||||
|
||||
# this is temp to handle compat with arch=ppc
|
||||
config 8xx
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||||
bool
|
||||
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||||
# this is temp to handle compat with arch=ppc
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||||
config 83xx
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bool
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||||
|
|
@ -429,6 +436,21 @@ config PPC_MPC52xx
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|||
bool
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||||
default n
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config PPC_MPC5200
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||||
bool
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||||
select PPC_MPC52xx
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||||
default n
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||||
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||||
config PPC_MPC5200_BUGFIX
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||||
bool "MPC5200 (L25R) bugfix support"
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||||
depends on PPC_MPC5200
|
||||
default n
|
||||
help
|
||||
Enable workarounds for original MPC5200 errata. This is not required
|
||||
for MPC5200B based boards.
|
||||
|
||||
It is safe to say 'Y' here
|
||||
|
||||
config PPC_EFIKA
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||||
bool "bPlan Efika 5k2. MPC5200B based computer"
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||||
depends on PPC_MULTIPLATFORM && PPC32
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||||
|
|
@ -441,7 +463,7 @@ config PPC_EFIKA
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|||
config PPC_LITE5200
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bool "Freescale Lite5200 Eval Board"
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||||
depends on PPC_MULTIPLATFORM && PPC32
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||||
select PPC_MPC52xx
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||||
select PPC_MPC5200
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default n
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config PPC_PMAC
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|
|
@ -484,6 +506,7 @@ config PPC_MAPLE
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|||
select PPC_970_NAP
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select PPC_NATIVE
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select PPC_RTAS
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select MMIO_NVRAM
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||||
select ATA_NONSTANDARD if ATA
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||||
default n
|
||||
help
|
||||
|
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@ -541,6 +564,16 @@ config PPC_PS3
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|||
enabling this will not result in a bootable kernel on a
|
||||
PS3 system.
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||||
|
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config PPC_CELLEB
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bool "Toshiba's Cell Reference Set 'Celleb' Architecture"
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depends on PPC_MULTIPLATFORM && PPC64
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select PPC_CELL
|
||||
select PPC_OF_PLATFORM_PCI
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select HAS_TXX9_SERIAL
|
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select PPC_UDBG_BEAT
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select USB_OHCI_BIG_ENDIAN_MMIO
|
||||
select USB_EHCI_BIG_ENDIAN_MMIO
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||||
|
||||
config PPC_NATIVE
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||||
bool
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||||
depends on PPC_MULTIPLATFORM
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@ -554,6 +587,11 @@ config UDBG_RTAS_CONSOLE
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depends on PPC_RTAS
|
||||
default n
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||||
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config PPC_UDBG_BEAT
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bool "BEAT based debug console"
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depends on PPC_CELLEB
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default n
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config XICS
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||||
depends on PPC_PSERIES
|
||||
bool
|
||||
|
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@ -707,6 +745,7 @@ source arch/powerpc/platforms/86xx/Kconfig
|
|||
source arch/powerpc/platforms/8xx/Kconfig
|
||||
source arch/powerpc/platforms/cell/Kconfig
|
||||
source arch/powerpc/platforms/ps3/Kconfig
|
||||
source arch/powerpc/platforms/pasemi/Kconfig
|
||||
|
||||
menu "Kernel options"
|
||||
|
||||
|
|
@ -729,7 +768,7 @@ config FORCE_MAX_ZONEORDER
|
|||
|
||||
config MATH_EMULATION
|
||||
bool "Math emulation"
|
||||
depends on 4xx || 8xx || E200 || PPC_83xx || E500
|
||||
depends on 4xx || 8xx || E200 || PPC_MPC832x || E500
|
||||
---help---
|
||||
Some PowerPC chips designed for embedded applications do not have
|
||||
a floating-point unit and therefore do not implement the
|
||||
|
|
@ -1187,7 +1226,7 @@ source "arch/powerpc/oprofile/Kconfig"
|
|||
|
||||
config KPROBES
|
||||
bool "Kprobes (EXPERIMENTAL)"
|
||||
depends on PPC64 && KALLSYMS && EXPERIMENTAL && MODULES
|
||||
depends on !BOOKE && !4xx && KALLSYMS && EXPERIMENTAL && MODULES
|
||||
help
|
||||
Kprobes allows you to trap at almost any kernel address and
|
||||
execute a callback function. register_kprobe() establishes
|
||||
|
|
|
|||
|
|
@ -4,14 +4,14 @@ source "lib/Kconfig.debug"
|
|||
|
||||
config DEBUG_STACKOVERFLOW
|
||||
bool "Check for stack overflows"
|
||||
depends on DEBUG_KERNEL && PPC64
|
||||
depends on DEBUG_KERNEL
|
||||
help
|
||||
This option will cause messages to be printed if free stack space
|
||||
drops below a certain limit.
|
||||
|
||||
config DEBUG_STACK_USAGE
|
||||
bool "Stack utilization instrumentation"
|
||||
depends on DEBUG_KERNEL && PPC64
|
||||
depends on DEBUG_KERNEL
|
||||
help
|
||||
Enables the display of the minimum amount of free stack which each
|
||||
task has ever had available in the sysrq-T and sysrq-P debug output.
|
||||
|
|
@ -185,6 +185,20 @@ config PPC_EARLY_DEBUG_ISERIES
|
|||
Select this to enable early debugging for legacy iSeries. You need
|
||||
to hit "Ctrl-x Ctrl-x" to see the messages on the console.
|
||||
|
||||
config PPC_EARLY_DEBUG_PAS_REALMODE
|
||||
bool "PA Semi real mode"
|
||||
depends on PPC_PASEMI
|
||||
help
|
||||
Select this to enable early debugging for PA Semi.
|
||||
Output will be on UART0.
|
||||
|
||||
config PPC_EARLY_DEBUG_BEAT
|
||||
bool "Beat HV Console"
|
||||
depends on PPC_CELLEB
|
||||
select PPC_UDBG_BEAT
|
||||
help
|
||||
Select this to enable early debugging for Celleb with Beat.
|
||||
|
||||
endchoice
|
||||
|
||||
endmenu
|
||||
|
|
|
|||
|
|
@ -162,6 +162,7 @@ image-$(CONFIG_PPC_PSERIES) += zImage.pseries
|
|||
image-$(CONFIG_PPC_MAPLE) += zImage.pseries
|
||||
image-$(CONFIG_PPC_IBM_CELL_BLADE) += zImage.pseries
|
||||
image-$(CONFIG_PPC_PS3) += zImage.ps3
|
||||
image-$(CONFIG_PPC_CELLEB) += zImage.pseries
|
||||
image-$(CONFIG_PPC_CHRP) += zImage.chrp
|
||||
image-$(CONFIG_PPC_EFIKA) += zImage.chrp
|
||||
image-$(CONFIG_PPC_PMAC) += zImage.pmac
|
||||
|
|
|
|||
|
|
@ -53,13 +53,20 @@
|
|||
reg = <00000000 4000000 f4500000 00000020>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
name = "chosen";
|
||||
linux,platform = <0>;
|
||||
interrupt-controller = <10c00>;
|
||||
linux,phandle = <400>;
|
||||
};
|
||||
|
||||
soc8272@f0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
#interrupt-cells = <2>;
|
||||
device_type = "soc";
|
||||
ranges = < 0 0 2 00000000 f0000000 00053000>;
|
||||
reg = <f0000000 0>;
|
||||
ranges = <00000000 f0000000 00053000>;
|
||||
reg = <f0000000 10000>;
|
||||
|
||||
mdio@0 {
|
||||
device_type = "mdio";
|
||||
|
|
@ -71,7 +78,7 @@
|
|||
ethernet-phy@0 {
|
||||
linux,phandle = <2452000>;
|
||||
interrupt-parent = <10c00>;
|
||||
interrupts = <19 1>;
|
||||
interrupts = <17 4>;
|
||||
reg = <0>;
|
||||
bitbang = [ 12 12 13 02 02 01 ];
|
||||
device_type = "ethernet-phy";
|
||||
|
|
@ -79,7 +86,7 @@
|
|||
ethernet-phy@1 {
|
||||
linux,phandle = <2452001>;
|
||||
interrupt-parent = <10c00>;
|
||||
interrupts = <19 1>;
|
||||
interrupts = <17 4>;
|
||||
bitbang = [ 12 12 13 02 02 01 ];
|
||||
reg = <3>;
|
||||
device_type = "ethernet-phy";
|
||||
|
|
@ -90,7 +97,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
device_type = "network";
|
||||
device-id = <2>;
|
||||
device-id = <1>;
|
||||
compatible = "fs_enet";
|
||||
model = "FCC";
|
||||
reg = <11300 20 8400 100 11380 30>;
|
||||
|
|
@ -104,7 +111,7 @@
|
|||
|
||||
ethernet@25000 {
|
||||
device_type = "network";
|
||||
device-id = <3>;
|
||||
device-id = <2>;
|
||||
compatible = "fs_enet";
|
||||
model = "FCC";
|
||||
reg = <11320 20 8500 100 113b0 30>;
|
||||
|
|
@ -123,8 +130,8 @@
|
|||
#interrupt-cells = <2>;
|
||||
device_type = "cpm";
|
||||
model = "CPM2";
|
||||
ranges = <00000000 00000000 3ffff>;
|
||||
reg = <10d80 3280>;
|
||||
ranges = <00000000 00000000 20000>;
|
||||
reg = <0 20000>;
|
||||
command-proc = <119c0>;
|
||||
brg-frequency = <17D7840>;
|
||||
cpm_clk = <BEBC200>;
|
||||
|
|
@ -133,7 +140,7 @@
|
|||
device_type = "serial";
|
||||
compatible = "cpm_uart";
|
||||
model = "SCC";
|
||||
device-id = <2>;
|
||||
device-id = <1>;
|
||||
reg = <11a00 20 8000 100>;
|
||||
current-speed = <1c200>;
|
||||
interrupts = <28 2>;
|
||||
|
|
@ -147,7 +154,7 @@
|
|||
device_type = "serial";
|
||||
compatible = "cpm_uart";
|
||||
model = "SCC";
|
||||
device-id = <5>;
|
||||
device-id = <4>;
|
||||
reg = <11a60 20 8300 100>;
|
||||
current-speed = <1c200>;
|
||||
interrupts = <2b 2>;
|
||||
|
|
@ -181,24 +188,24 @@
|
|||
interrupt-map = <
|
||||
|
||||
/* IDSEL 0x16 */
|
||||
b000 0 0 1 f8200000 40 0
|
||||
b000 0 0 2 f8200000 41 0
|
||||
b000 0 0 3 f8200000 42 0
|
||||
b000 0 0 4 f8200000 43 0
|
||||
b000 0 0 1 f8200000 40 8
|
||||
b000 0 0 2 f8200000 41 8
|
||||
b000 0 0 3 f8200000 42 8
|
||||
b000 0 0 4 f8200000 43 8
|
||||
|
||||
/* IDSEL 0x17 */
|
||||
b800 0 0 1 f8200000 43 0
|
||||
b800 0 0 2 f8200000 40 0
|
||||
b800 0 0 3 f8200000 41 0
|
||||
b800 0 0 4 f8200000 42 0
|
||||
b800 0 0 1 f8200000 43 8
|
||||
b800 0 0 2 f8200000 40 8
|
||||
b800 0 0 3 f8200000 41 8
|
||||
b800 0 0 4 f8200000 42 8
|
||||
|
||||
/* IDSEL 0x18 */
|
||||
c000 0 0 1 f8200000 42 0
|
||||
c000 0 0 2 f8200000 43 0
|
||||
c000 0 0 3 f8200000 40 0
|
||||
c000 0 0 4 f8200000 41 0>;
|
||||
c000 0 0 1 f8200000 42 8
|
||||
c000 0 0 2 f8200000 43 8
|
||||
c000 0 0 3 f8200000 40 8
|
||||
c000 0 0 4 f8200000 41 8>;
|
||||
interrupt-parent = <10c00>;
|
||||
interrupts = <14 3>;
|
||||
interrupts = <14 8>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <02000000 0 80000000 80000000 0 40000000
|
||||
01000000 0 00000000 f6000000 0 02000000>;
|
||||
|
|
@ -210,7 +217,7 @@
|
|||
model = "SEC2";
|
||||
compatible = "talitos";
|
||||
reg = <30000 10000>;
|
||||
interrupts = <b 0>;
|
||||
interrupts = <b 2>;
|
||||
interrupt-parent = <10c00>;
|
||||
num-channels = <4>;
|
||||
channel-fifo-len = <18>;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,345 @@
|
|||
/*
|
||||
* MPC8323E EMDS Device Tree Source
|
||||
*
|
||||
* Copyright 2006 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/ {
|
||||
model = "MPC8323EMDS";
|
||||
compatible = "MPC83xx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
linux,phandle = <100>;
|
||||
|
||||
cpus {
|
||||
#cpus = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
linux,phandle = <200>;
|
||||
|
||||
PowerPC,8323@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <20>; // 32 bytes
|
||||
i-cache-line-size = <20>; // 32 bytes
|
||||
d-cache-size = <4000>; // L1, 16K
|
||||
i-cache-size = <4000>; // L1, 16K
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
32-bit;
|
||||
linux,phandle = <201>;
|
||||
linux,boot-cpu;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
linux,phandle = <300>;
|
||||
reg = <00000000 08000000>;
|
||||
};
|
||||
|
||||
bcsr@f8000000 {
|
||||
device_type = "board-control";
|
||||
reg = <f8000000 8000>;
|
||||
};
|
||||
|
||||
soc8323@e0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
#interrupt-cells = <2>;
|
||||
device_type = "soc";
|
||||
ranges = <0 e0000000 00100000>;
|
||||
reg = <e0000000 00000200>;
|
||||
bus-frequency = <7DE2900>;
|
||||
|
||||
wdt@200 {
|
||||
device_type = "watchdog";
|
||||
compatible = "mpc83xx_wdt";
|
||||
reg = <200 100>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
device_type = "i2c";
|
||||
compatible = "fsl-i2c";
|
||||
reg = <3000 100>;
|
||||
interrupts = <e 8>;
|
||||
interrupt-parent = <700>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
serial@4500 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <4500 100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <9 8>;
|
||||
interrupt-parent = <700>;
|
||||
};
|
||||
|
||||
serial@4600 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <4600 100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <a 8>;
|
||||
interrupt-parent = <700>;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
device_type = "crypto";
|
||||
model = "SEC2";
|
||||
compatible = "talitos";
|
||||
reg = <30000 7000>;
|
||||
interrupts = <b 8>;
|
||||
interrupt-parent = <700>;
|
||||
/* Rev. 2.2 */
|
||||
num-channels = <1>;
|
||||
channel-fifo-len = <18>;
|
||||
exec-units-mask = <0000004c>;
|
||||
descriptor-types-mask = <0122003f>;
|
||||
};
|
||||
|
||||
pci@8500 {
|
||||
linux,phandle = <8500>;
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x11 AD17 */
|
||||
8800 0 0 1 700 14 8
|
||||
8800 0 0 2 700 15 8
|
||||
8800 0 0 3 700 16 8
|
||||
8800 0 0 4 700 17 8
|
||||
|
||||
/* IDSEL 0x12 AD18 */
|
||||
9000 0 0 1 700 16 8
|
||||
9000 0 0 2 700 17 8
|
||||
9000 0 0 3 700 14 8
|
||||
9000 0 0 4 700 15 8
|
||||
|
||||
/* IDSEL 0x13 AD19 */
|
||||
9800 0 0 1 700 17 8
|
||||
9800 0 0 2 700 14 8
|
||||
9800 0 0 3 700 15 8
|
||||
9800 0 0 4 700 16 8
|
||||
|
||||
/* IDSEL 0x15 AD21*/
|
||||
a800 0 0 1 700 14 8
|
||||
a800 0 0 2 700 15 8
|
||||
a800 0 0 3 700 16 8
|
||||
a800 0 0 4 700 17 8
|
||||
|
||||
/* IDSEL 0x16 AD22*/
|
||||
b000 0 0 1 700 17 8
|
||||
b000 0 0 2 700 14 8
|
||||
b000 0 0 3 700 15 8
|
||||
b000 0 0 4 700 16 8
|
||||
|
||||
/* IDSEL 0x17 AD23*/
|
||||
b800 0 0 1 700 16 8
|
||||
b800 0 0 2 700 17 8
|
||||
b800 0 0 3 700 14 8
|
||||
b800 0 0 4 700 15 8
|
||||
|
||||
/* IDSEL 0x18 AD24*/
|
||||
c000 0 0 1 700 15 8
|
||||
c000 0 0 2 700 16 8
|
||||
c000 0 0 3 700 17 8
|
||||
c000 0 0 4 700 14 8>;
|
||||
interrupt-parent = <700>;
|
||||
interrupts = <42 8>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <02000000 0 a0000000 90000000 0 10000000
|
||||
42000000 0 80000000 80000000 0 10000000
|
||||
01000000 0 00000000 d0000000 0 00100000>;
|
||||
clock-frequency = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <8500 100>;
|
||||
compatible = "83xx";
|
||||
device_type = "pci";
|
||||
};
|
||||
|
||||
pic@700 {
|
||||
linux,phandle = <700>;
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <700 100>;
|
||||
built-in;
|
||||
device_type = "ipic";
|
||||
};
|
||||
|
||||
par_io@1400 {
|
||||
reg = <1400 100>;
|
||||
device_type = "par_io";
|
||||
num-ports = <7>;
|
||||
|
||||
ucc_pin@03 {
|
||||
linux,phandle = <140003>;
|
||||
pio-map = <
|
||||
/* port pin dir open_drain assignment has_irq */
|
||||
3 4 3 0 2 0 /* MDIO */
|
||||
3 5 1 0 2 0 /* MDC */
|
||||
0 d 2 0 1 0 /* RX_CLK (CLK9) */
|
||||
3 18 2 0 1 0 /* TX_CLK (CLK10) */
|
||||
1 1 1 0 1 0 /* TxD1 */
|
||||
1 0 1 0 1 0 /* TxD0 */
|
||||
1 1 1 0 1 0 /* TxD1 */
|
||||
1 2 1 0 1 0 /* TxD2 */
|
||||
1 3 1 0 1 0 /* TxD3 */
|
||||
1 4 2 0 1 0 /* RxD0 */
|
||||
1 5 2 0 1 0 /* RxD1 */
|
||||
1 6 2 0 1 0 /* RxD2 */
|
||||
1 7 2 0 1 0 /* RxD3 */
|
||||
1 8 2 0 1 0 /* RX_ER */
|
||||
1 9 1 0 1 0 /* TX_ER */
|
||||
1 a 2 0 1 0 /* RX_DV */
|
||||
1 b 2 0 1 0 /* COL */
|
||||
1 c 1 0 1 0 /* TX_EN */
|
||||
1 d 2 0 1 0>;/* CRS */
|
||||
};
|
||||
ucc_pin@04 {
|
||||
linux,phandle = <140004>;
|
||||
pio-map = <
|
||||
/* port pin dir open_drain assignment has_irq */
|
||||
3 1f 2 0 1 0 /* RX_CLK (CLK7) */
|
||||
3 6 2 0 1 0 /* TX_CLK (CLK8) */
|
||||
1 12 1 0 1 0 /* TxD0 */
|
||||
1 13 1 0 1 0 /* TxD1 */
|
||||
1 14 1 0 1 0 /* TxD2 */
|
||||
1 15 1 0 1 0 /* TxD3 */
|
||||
1 16 2 0 1 0 /* RxD0 */
|
||||
1 17 2 0 1 0 /* RxD1 */
|
||||
1 18 2 0 1 0 /* RxD2 */
|
||||
1 19 2 0 1 0 /* RxD3 */
|
||||
1 1a 2 0 1 0 /* RX_ER */
|
||||
1 1b 1 0 1 0 /* TX_ER */
|
||||
1 1c 2 0 1 0 /* RX_DV */
|
||||
1 1d 2 0 1 0 /* COL */
|
||||
1 1e 1 0 1 0 /* TX_EN */
|
||||
1 1f 2 0 1 0>;/* CRS */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
qe@e0100000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "qe";
|
||||
model = "QE";
|
||||
ranges = <0 e0100000 00100000>;
|
||||
reg = <e0100000 480>;
|
||||
brg-frequency = <0>;
|
||||
bus-frequency = <BCD3D80>;
|
||||
|
||||
muram@10000 {
|
||||
device_type = "muram";
|
||||
ranges = <0 00010000 00004000>;
|
||||
|
||||
data-only@0 {
|
||||
reg = <0 4000>;
|
||||
};
|
||||
};
|
||||
|
||||
spi@4c0 {
|
||||
device_type = "spi";
|
||||
compatible = "fsl_spi";
|
||||
reg = <4c0 40>;
|
||||
interrupts = <2>;
|
||||
interrupt-parent = <80>;
|
||||
mode = "cpu";
|
||||
};
|
||||
|
||||
spi@500 {
|
||||
device_type = "spi";
|
||||
compatible = "fsl_spi";
|
||||
reg = <500 40>;
|
||||
interrupts = <1>;
|
||||
interrupt-parent = <80>;
|
||||
mode = "cpu";
|
||||
};
|
||||
|
||||
usb@6c0 {
|
||||
device_type = "usb";
|
||||
compatible = "qe_udc";
|
||||
reg = <6c0 40 8B00 100>;
|
||||
interrupts = <b>;
|
||||
interrupt-parent = <80>;
|
||||
mode = "slave";
|
||||
};
|
||||
|
||||
ucc@2200 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
model = "UCC";
|
||||
device-id = <3>;
|
||||
reg = <2200 200>;
|
||||
interrupts = <22>;
|
||||
interrupt-parent = <80>;
|
||||
mac-address = [ 00 04 9f 00 23 23 ];
|
||||
rx-clock = <19>;
|
||||
tx-clock = <1a>;
|
||||
phy-handle = <212003>;
|
||||
pio-handle = <140003>;
|
||||
};
|
||||
|
||||
ucc@3200 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
model = "UCC";
|
||||
device-id = <4>;
|
||||
reg = <3000 200>;
|
||||
interrupts = <23>;
|
||||
interrupt-parent = <80>;
|
||||
mac-address = [ 00 11 22 33 44 55 ];
|
||||
rx-clock = <17>;
|
||||
tx-clock = <18>;
|
||||
phy-handle = <212004>;
|
||||
pio-handle = <140004>;
|
||||
};
|
||||
|
||||
mdio@2320 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2320 18>;
|
||||
device_type = "mdio";
|
||||
compatible = "ucc_geth_phy";
|
||||
|
||||
ethernet-phy@03 {
|
||||
linux,phandle = <212003>;
|
||||
interrupt-parent = <700>;
|
||||
interrupts = <11 2>;
|
||||
reg = <3>;
|
||||
device_type = "ethernet-phy";
|
||||
interface = <3>; //ENET_100_MII
|
||||
};
|
||||
ethernet-phy@04 {
|
||||
linux,phandle = <212004>;
|
||||
interrupt-parent = <700>;
|
||||
interrupts = <12 2>;
|
||||
reg = <4>;
|
||||
device_type = "ethernet-phy";
|
||||
interface = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
qeic@80 {
|
||||
linux,phandle = <80>;
|
||||
interrupt-controller;
|
||||
device_type = "qeic";
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <80 80>;
|
||||
built-in;
|
||||
big-endian;
|
||||
interrupts = <20 8 21 8>; //high:32 low:33
|
||||
interrupt-parent = <700>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -200,7 +200,7 @@
|
|||
a800 0 0 4 40000 31 1>;
|
||||
|
||||
interrupt-parent = <40000>;
|
||||
interrupts = <42 0>;
|
||||
interrupts = <8 0>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <02000000 0 80000000 80000000 0 20000000
|
||||
01000000 0 00000000 e2000000 0 01000000>;
|
||||
|
|
@ -250,7 +250,7 @@
|
|||
rx-clock = <1>;
|
||||
tx-clock = <1>;
|
||||
current-speed = <1c200>;
|
||||
interrupts = <64 1>;
|
||||
interrupts = <28 8>;
|
||||
interrupt-parent = <90c00>;
|
||||
};
|
||||
|
||||
|
|
@ -264,7 +264,7 @@
|
|||
rx-clock = <2>;
|
||||
tx-clock = <2>;
|
||||
current-speed = <1c200>;
|
||||
interrupts = <65 1>;
|
||||
interrupts = <29 8>;
|
||||
interrupt-parent = <90c00>;
|
||||
};
|
||||
|
||||
|
|
@ -278,7 +278,7 @@
|
|||
clock-setup = <ff00ffff 250000>;
|
||||
rx-clock = <15>;
|
||||
tx-clock = <16>;
|
||||
interrupts = <5d 1>;
|
||||
interrupts = <21 8>;
|
||||
interrupt-parent = <90c00>;
|
||||
phy-handle = <2452002>;
|
||||
};
|
||||
|
|
@ -293,7 +293,7 @@
|
|||
clock-setup = <ffff00ff 3700>;
|
||||
rx-clock = <17>;
|
||||
tx-clock = <18>;
|
||||
interrupts = <5e 1>;
|
||||
interrupts = <22 8>;
|
||||
interrupt-parent = <90c00>;
|
||||
phy-handle = <2452003>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,162 @@
|
|||
/*
|
||||
* MPC866 ADS Device Tree Source
|
||||
*
|
||||
* Copyright 2006 MontaVista Software, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
|
||||
/ {
|
||||
model = "MPC866ADS";
|
||||
compatible = "mpc8xx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
linux,phandle = <100>;
|
||||
|
||||
cpus {
|
||||
#cpus = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
linux,phandle = <200>;
|
||||
|
||||
PowerPC,866@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <20>; // 32 bytes
|
||||
i-cache-line-size = <20>; // 32 bytes
|
||||
d-cache-size = <2000>; // L1, 8K
|
||||
i-cache-size = <4000>; // L1, 16K
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
32-bit;
|
||||
interrupts = <f 2>; // decrementer interrupt
|
||||
interrupt-parent = <ff000000>;
|
||||
linux,phandle = <201>;
|
||||
linux,boot-cpu;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
linux,phandle = <300>;
|
||||
reg = <00000000 800000>;
|
||||
};
|
||||
|
||||
soc866@ff000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
#interrupt-cells = <2>;
|
||||
device_type = "soc";
|
||||
ranges = <0 ff000000 00100000>;
|
||||
reg = <ff000000 00000200>;
|
||||
bus-frequency = <0>;
|
||||
mdio@e80 {
|
||||
device_type = "mdio";
|
||||
compatible = "fs_enet";
|
||||
reg = <e80 8>;
|
||||
linux,phandle = <e80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
ethernet-phy@f {
|
||||
linux,phandle = <e800f>;
|
||||
reg = <f>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
};
|
||||
|
||||
fec@e00 {
|
||||
device_type = "network";
|
||||
compatible = "fs_enet";
|
||||
model = "FEC";
|
||||
device-id = <1>;
|
||||
reg = <e00 188>;
|
||||
mac-address = [ 00 00 0C 00 01 FD ];
|
||||
interrupts = <3 1>;
|
||||
interrupt-parent = <ff000000>;
|
||||
phy-handle = <e800f>;
|
||||
};
|
||||
|
||||
pic@ff000000 {
|
||||
linux,phandle = <ff000000>;
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0 24>;
|
||||
built-in;
|
||||
device_type = "mpc8xx-pic";
|
||||
compatible = "CPM";
|
||||
};
|
||||
|
||||
cpm@ff000000 {
|
||||
linux,phandle = <ff000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
#interrupt-cells = <2>;
|
||||
device_type = "cpm";
|
||||
model = "CPM";
|
||||
ranges = <0 0 4000>;
|
||||
reg = <860 f0>;
|
||||
command-proc = <9c0>;
|
||||
brg-frequency = <0>;
|
||||
interrupts = <0 2>; // cpm error interrupt
|
||||
interrupt-parent = <930>;
|
||||
|
||||
pic@930 {
|
||||
linux,phandle = <930>;
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <5 2 0 2>;
|
||||
interrupt-parent = <ff000000>;
|
||||
reg = <930 20>;
|
||||
built-in;
|
||||
device_type = "cpm-pic";
|
||||
compatible = "CPM";
|
||||
};
|
||||
|
||||
smc@a80 {
|
||||
device_type = "serial";
|
||||
compatible = "cpm_uart";
|
||||
model = "SMC";
|
||||
device-id = <1>;
|
||||
reg = <a80 10 3e80 40>;
|
||||
clock-setup = <00ffffff 0>;
|
||||
rx-clock = <1>;
|
||||
tx-clock = <1>;
|
||||
current-speed = <0>;
|
||||
interrupts = <4 3>;
|
||||
interrupt-parent = <930>;
|
||||
};
|
||||
|
||||
smc@a90 {
|
||||
device_type = "serial";
|
||||
compatible = "cpm_uart";
|
||||
model = "SMC";
|
||||
device-id = <2>;
|
||||
reg = <a90 20 3f80 40>;
|
||||
clock-setup = <ff00ffff 90000>;
|
||||
rx-clock = <2>;
|
||||
tx-clock = <2>;
|
||||
current-speed = <0>;
|
||||
interrupts = <3 3>;
|
||||
interrupt-parent = <930>;
|
||||
};
|
||||
|
||||
scc@a00 {
|
||||
device_type = "network";
|
||||
compatible = "fs_enet";
|
||||
model = "SCC";
|
||||
device-id = <1>;
|
||||
reg = <a00 18 3c00 80>;
|
||||
mac-address = [ 00 00 0C 00 03 FD ];
|
||||
interrupts = <1e 3>;
|
||||
interrupt-parent = <930>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,185 @@
|
|||
/*
|
||||
* MPC885 ADS Device Tree Source
|
||||
*
|
||||
* Copyright 2006 MontaVista Software, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
|
||||
/ {
|
||||
model = "MPC885ADS";
|
||||
compatible = "mpc8xx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
linux,phandle = <100>;
|
||||
|
||||
cpus {
|
||||
#cpus = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
linux,phandle = <200>;
|
||||
|
||||
PowerPC,885@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <20>; // 32 bytes
|
||||
i-cache-line-size = <20>; // 32 bytes
|
||||
d-cache-size = <2000>; // L1, 8K
|
||||
i-cache-size = <2000>; // L1, 8K
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
32-bit;
|
||||
interrupts = <f 2>; // decrementer interrupt
|
||||
interrupt-parent = <ff000000>;
|
||||
linux,phandle = <201>;
|
||||
linux,boot-cpu;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
linux,phandle = <300>;
|
||||
reg = <00000000 800000>;
|
||||
};
|
||||
|
||||
soc885@ff000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
#interrupt-cells = <2>;
|
||||
device_type = "soc";
|
||||
ranges = <0 ff000000 00100000>;
|
||||
reg = <ff000000 00000200>;
|
||||
bus-frequency = <0>;
|
||||
mdio@e80 {
|
||||
device_type = "mdio";
|
||||
compatible = "fs_enet";
|
||||
reg = <e80 8>;
|
||||
linux,phandle = <e80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
ethernet-phy@0 {
|
||||
linux,phandle = <e8000>;
|
||||
reg = <0>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
ethernet-phy@1 {
|
||||
linux,phandle = <e8001>;
|
||||
reg = <1>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
ethernet-phy@2 {
|
||||
linux,phandle = <e8002>;
|
||||
reg = <2>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
};
|
||||
|
||||
fec@e00 {
|
||||
device_type = "network";
|
||||
compatible = "fs_enet";
|
||||
model = "FEC";
|
||||
device-id = <1>;
|
||||
reg = <e00 188>;
|
||||
mac-address = [ 00 00 0C 00 01 FD ];
|
||||
interrupts = <3 1>;
|
||||
interrupt-parent = <ff000000>;
|
||||
phy-handle = <e8000>;
|
||||
};
|
||||
|
||||
fec@1e00 {
|
||||
device_type = "network";
|
||||
compatible = "fs_enet";
|
||||
model = "FEC";
|
||||
device-id = <2>;
|
||||
reg = <1e00 188>;
|
||||
mac-address = [ 00 00 0C 00 02 FD ];
|
||||
interrupts = <7 1>;
|
||||
interrupt-parent = <ff000000>;
|
||||
phy-handle = <e8001>;
|
||||
};
|
||||
|
||||
pic@ff000000 {
|
||||
linux,phandle = <ff000000>;
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0 24>;
|
||||
built-in;
|
||||
device_type = "mpc8xx-pic";
|
||||
compatible = "CPM";
|
||||
};
|
||||
|
||||
cpm@ff000000 {
|
||||
linux,phandle = <ff000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
#interrupt-cells = <2>;
|
||||
device_type = "cpm";
|
||||
model = "CPM";
|
||||
ranges = <0 0 4000>;
|
||||
reg = <860 f0>;
|
||||
command-proc = <9c0>;
|
||||
brg-frequency = <0>;
|
||||
interrupts = <0 2>; // cpm error interrupt
|
||||
interrupt-parent = <930>;
|
||||
|
||||
pic@930 {
|
||||
linux,phandle = <930>;
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <5 2 0 2>;
|
||||
interrupt-parent = <ff000000>;
|
||||
reg = <930 20>;
|
||||
built-in;
|
||||
device_type = "cpm-pic";
|
||||
compatible = "CPM";
|
||||
};
|
||||
|
||||
smc@a80 {
|
||||
device_type = "serial";
|
||||
compatible = "cpm_uart";
|
||||
model = "SMC";
|
||||
device-id = <1>;
|
||||
reg = <a80 10 3e80 40>;
|
||||
clock-setup = <00ffffff 0>;
|
||||
rx-clock = <1>;
|
||||
tx-clock = <1>;
|
||||
current-speed = <0>;
|
||||
interrupts = <4 3>;
|
||||
interrupt-parent = <930>;
|
||||
};
|
||||
|
||||
smc@a90 {
|
||||
device_type = "serial";
|
||||
compatible = "cpm_uart";
|
||||
model = "SMC";
|
||||
device-id = <2>;
|
||||
reg = <a90 20 3f80 40>;
|
||||
clock-setup = <ff00ffff 90000>;
|
||||
rx-clock = <2>;
|
||||
tx-clock = <2>;
|
||||
current-speed = <0>;
|
||||
interrupts = <3 3>;
|
||||
interrupt-parent = <930>;
|
||||
};
|
||||
|
||||
scc@a40 {
|
||||
device_type = "network";
|
||||
compatible = "fs_enet";
|
||||
model = "SCC";
|
||||
device-id = <3>;
|
||||
reg = <a40 18 3e00 80>;
|
||||
mac-address = [ 00 00 0C 00 03 FD ];
|
||||
interrupts = <1c 3>;
|
||||
interrupt-parent = <930>;
|
||||
phy-handle = <e8002>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,848 @@
|
|||
#
|
||||
# Automatically generated make config: don't edit
|
||||
# Linux kernel version: 2.6.17-rc5
|
||||
# Fri Jul 14 20:36:35 2006
|
||||
#
|
||||
# CONFIG_PPC64 is not set
|
||||
CONFIG_PPC32=y
|
||||
CONFIG_PPC_MERGE=y
|
||||
CONFIG_MMU=y
|
||||
CONFIG_GENERIC_HARDIRQS=y
|
||||
CONFIG_IRQ_PER_CPU=y
|
||||
CONFIG_RWSEM_XCHGADD_ALGORITHM=y
|
||||
CONFIG_GENERIC_HWEIGHT=y
|
||||
CONFIG_GENERIC_CALIBRATE_DELAY=y
|
||||
CONFIG_GENERIC_FIND_NEXT_BIT=y
|
||||
CONFIG_PPC=y
|
||||
CONFIG_EARLY_PRINTK=y
|
||||
CONFIG_GENERIC_NVRAM=y
|
||||
CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
|
||||
CONFIG_ARCH_MAY_HAVE_PC_FDC=y
|
||||
CONFIG_PPC_OF=y
|
||||
# CONFIG_PPC_UDBG_16550 is not set
|
||||
# CONFIG_GENERIC_TBSYNC is not set
|
||||
# CONFIG_DEFAULT_UIMAGE is not set
|
||||
|
||||
#
|
||||
# Processor support
|
||||
#
|
||||
# CONFIG_CLASSIC32 is not set
|
||||
# CONFIG_PPC_52xx is not set
|
||||
CONFIG_PPC_82xx=y
|
||||
# CONFIG_PPC_83xx is not set
|
||||
# CONFIG_PPC_85xx is not set
|
||||
# CONFIG_40x is not set
|
||||
# CONFIG_44x is not set
|
||||
# CONFIG_8xx is not set
|
||||
# CONFIG_E200 is not set
|
||||
CONFIG_6xx=y
|
||||
CONFIG_PPC_FPU=y
|
||||
CONFIG_PPC_STD_MMU=y
|
||||
CONFIG_PPC_STD_MMU_32=y
|
||||
# CONFIG_SMP is not set
|
||||
|
||||
#
|
||||
# Code maturity level options
|
||||
#
|
||||
# CONFIG_EXPERIMENTAL is not set
|
||||
CONFIG_BROKEN_ON_SMP=y
|
||||
CONFIG_INIT_ENV_ARG_LIMIT=32
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_LOCALVERSION="powerpc8272"
|
||||
CONFIG_LOCALVERSION_AUTO=y
|
||||
CONFIG_SWAP=y
|
||||
CONFIG_SYSVIPC=y
|
||||
# CONFIG_BSD_PROCESS_ACCT is not set
|
||||
CONFIG_SYSCTL=y
|
||||
# CONFIG_AUDIT is not set
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
# CONFIG_RELAY is not set
|
||||
CONFIG_INITRAMFS_SOURCE=""
|
||||
CONFIG_EMBEDDED=y
|
||||
CONFIG_KALLSYMS=y
|
||||
CONFIG_KALLSYMS_ALL=y
|
||||
CONFIG_KALLSYMS_EXTRA_PASS=y
|
||||
CONFIG_HOTPLUG=y
|
||||
CONFIG_PRINTK=y
|
||||
CONFIG_BUG=y
|
||||
CONFIG_ELF_CORE=y
|
||||
CONFIG_BASE_FULL=y
|
||||
CONFIG_FUTEX=y
|
||||
CONFIG_EPOLL=y
|
||||
CONFIG_SHMEM=y
|
||||
CONFIG_SLAB=y
|
||||
# CONFIG_TINY_SHMEM is not set
|
||||
CONFIG_BASE_SMALL=0
|
||||
# CONFIG_SLOB is not set
|
||||
|
||||
#
|
||||
# Loadable module support
|
||||
#
|
||||
# CONFIG_MODULES is not set
|
||||
|
||||
#
|
||||
# Block layer
|
||||
#
|
||||
# CONFIG_LBD is not set
|
||||
# CONFIG_BLK_DEV_IO_TRACE is not set
|
||||
# CONFIG_LSF is not set
|
||||
|
||||
#
|
||||
# IO Schedulers
|
||||
#
|
||||
CONFIG_IOSCHED_NOOP=y
|
||||
CONFIG_IOSCHED_AS=y
|
||||
CONFIG_IOSCHED_DEADLINE=y
|
||||
CONFIG_IOSCHED_CFQ=y
|
||||
CONFIG_DEFAULT_AS=y
|
||||
# CONFIG_DEFAULT_DEADLINE is not set
|
||||
# CONFIG_DEFAULT_CFQ is not set
|
||||
# CONFIG_DEFAULT_NOOP is not set
|
||||
CONFIG_DEFAULT_IOSCHED="anticipatory"
|
||||
CONFIG_PQ2ADS=y
|
||||
CONFIG_8260=y
|
||||
CONFIG_8272=y
|
||||
CONFIG_CPM2=y
|
||||
# CONFIG_WANT_EARLY_SERIAL is not set
|
||||
CONFIG_EMBEDDEDBOOT=y
|
||||
|
||||
#
|
||||
# Platform support
|
||||
#
|
||||
CONFIG_ADS8272=y
|
||||
|
||||
#
|
||||
# Kernel options
|
||||
#
|
||||
# CONFIG_HIGHMEM is not set
|
||||
# CONFIG_HZ_100 is not set
|
||||
CONFIG_HZ_250=y
|
||||
# CONFIG_HZ_1000 is not set
|
||||
CONFIG_HZ=250
|
||||
CONFIG_PREEMPT_NONE=y
|
||||
# CONFIG_PREEMPT_VOLUNTARY is not set
|
||||
# CONFIG_PREEMPT is not set
|
||||
CONFIG_BINFMT_ELF=y
|
||||
CONFIG_BINFMT_MISC=y
|
||||
# CONFIG_PC_KEYBOARD is not set
|
||||
CONFIG_ARCH_FLATMEM_ENABLE=y
|
||||
CONFIG_FLATMEM=y
|
||||
CONFIG_FLAT_NODE_MEM_MAP=y
|
||||
# CONFIG_SPARSEMEM_STATIC is not set
|
||||
CONFIG_SPLIT_PTLOCK_CPUS=4
|
||||
CONFIG_PROC_DEVICETREE=y
|
||||
# CONFIG_CMDLINE_BOOL is not set
|
||||
# CONFIG_PM is not set
|
||||
# CONFIG_SOFTWARE_SUSPEND is not set
|
||||
CONFIG_SECCOMP=y
|
||||
CONFIG_ISA_DMA_API=y
|
||||
|
||||
#
|
||||
# Bus options
|
||||
#
|
||||
# CONFIG_PPC_I8259 is not set
|
||||
CONFIG_FSL_SOC=y
|
||||
# CONFIG_PCI is not set
|
||||
# CONFIG_PCI_DOMAINS is not set
|
||||
|
||||
#
|
||||
# PCCARD (PCMCIA/CardBus) support
|
||||
#
|
||||
# CONFIG_PCCARD is not set
|
||||
|
||||
#
|
||||
# PCI Hotplug Support
|
||||
#
|
||||
|
||||
#
|
||||
# Advanced setup
|
||||
#
|
||||
# CONFIG_ADVANCED_OPTIONS is not set
|
||||
|
||||
#
|
||||
# Default settings for advanced configuration options are used
|
||||
#
|
||||
CONFIG_HIGHMEM_START=0xfe000000
|
||||
CONFIG_LOWMEM_SIZE=0x30000000
|
||||
CONFIG_KERNEL_START=0xc0000000
|
||||
CONFIG_TASK_SIZE=0x80000000
|
||||
CONFIG_BOOT_LOAD=0x00400000
|
||||
|
||||
#
|
||||
# Networking
|
||||
#
|
||||
CONFIG_NET=y
|
||||
|
||||
#
|
||||
# Networking options
|
||||
#
|
||||
# CONFIG_NETDEBUG is not set
|
||||
CONFIG_PACKET=y
|
||||
# CONFIG_PACKET_MMAP is not set
|
||||
CONFIG_UNIX=y
|
||||
# CONFIG_NET_KEY is not set
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_MULTICAST=y
|
||||
# CONFIG_IP_ADVANCED_ROUTER is not set
|
||||
CONFIG_IP_FIB_HASH=y
|
||||
CONFIG_IP_PNP=y
|
||||
CONFIG_IP_PNP_DHCP=y
|
||||
CONFIG_IP_PNP_BOOTP=y
|
||||
# CONFIG_IP_PNP_RARP is not set
|
||||
# CONFIG_NET_IPIP is not set
|
||||
# CONFIG_NET_IPGRE is not set
|
||||
# CONFIG_IP_MROUTE is not set
|
||||
CONFIG_SYN_COOKIES=y
|
||||
# CONFIG_INET_AH is not set
|
||||
# CONFIG_INET_ESP is not set
|
||||
# CONFIG_INET_IPCOMP is not set
|
||||
# CONFIG_INET_XFRM_TUNNEL is not set
|
||||
# CONFIG_INET_TUNNEL is not set
|
||||
CONFIG_INET_DIAG=y
|
||||
CONFIG_INET_TCP_DIAG=y
|
||||
# CONFIG_TCP_CONG_ADVANCED is not set
|
||||
CONFIG_TCP_CONG_BIC=y
|
||||
|
||||
#
|
||||
# IP: Virtual Server Configuration
|
||||
#
|
||||
# CONFIG_IP_VS is not set
|
||||
CONFIG_IPV6=y
|
||||
# CONFIG_IPV6_PRIVACY is not set
|
||||
# CONFIG_IPV6_ROUTER_PREF is not set
|
||||
# CONFIG_INET6_AH is not set
|
||||
# CONFIG_INET6_ESP is not set
|
||||
# CONFIG_INET6_IPCOMP is not set
|
||||
# CONFIG_INET6_XFRM_TUNNEL is not set
|
||||
# CONFIG_INET6_TUNNEL is not set
|
||||
# CONFIG_IPV6_TUNNEL is not set
|
||||
CONFIG_NETFILTER=y
|
||||
# CONFIG_NETFILTER_DEBUG is not set
|
||||
|
||||
#
|
||||
# Core Netfilter Configuration
|
||||
#
|
||||
# CONFIG_NETFILTER_NETLINK is not set
|
||||
# CONFIG_NETFILTER_XTABLES is not set
|
||||
|
||||
#
|
||||
# IP: Netfilter Configuration
|
||||
#
|
||||
# CONFIG_IP_NF_CONNTRACK is not set
|
||||
# CONFIG_IP_NF_QUEUE is not set
|
||||
# CONFIG_BRIDGE is not set
|
||||
# CONFIG_VLAN_8021Q is not set
|
||||
# CONFIG_DECNET is not set
|
||||
# CONFIG_LLC2 is not set
|
||||
# CONFIG_IPX is not set
|
||||
# CONFIG_ATALK is not set
|
||||
|
||||
#
|
||||
# QoS and/or fair queueing
|
||||
#
|
||||
# CONFIG_NET_SCHED is not set
|
||||
|
||||
#
|
||||
# Network testing
|
||||
#
|
||||
# CONFIG_NET_PKTGEN is not set
|
||||
# CONFIG_HAMRADIO is not set
|
||||
# CONFIG_IRDA is not set
|
||||
# CONFIG_BT is not set
|
||||
# CONFIG_IEEE80211 is not set
|
||||
|
||||
#
|
||||
# Device Drivers
|
||||
#
|
||||
|
||||
#
|
||||
# Generic Driver Options
|
||||
#
|
||||
CONFIG_STANDALONE=y
|
||||
CONFIG_PREVENT_FIRMWARE_BUILD=y
|
||||
# CONFIG_FW_LOADER is not set
|
||||
# CONFIG_DEBUG_DRIVER is not set
|
||||
|
||||
#
|
||||
# Connector - unified userspace <-> kernelspace linker
|
||||
#
|
||||
# CONFIG_CONNECTOR is not set
|
||||
|
||||
#
|
||||
# Memory Technology Devices (MTD)
|
||||
#
|
||||
# CONFIG_MTD is not set
|
||||
|
||||
#
|
||||
# Parallel port support
|
||||
#
|
||||
# CONFIG_PARPORT is not set
|
||||
|
||||
#
|
||||
# Plug and Play support
|
||||
#
|
||||
|
||||
#
|
||||
# Block devices
|
||||
#
|
||||
# CONFIG_BLK_DEV_FD is not set
|
||||
# CONFIG_BLK_DEV_COW_COMMON is not set
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
# CONFIG_BLK_DEV_CRYPTOLOOP is not set
|
||||
# CONFIG_BLK_DEV_NBD is not set
|
||||
# CONFIG_BLK_DEV_RAM is not set
|
||||
# CONFIG_BLK_DEV_INITRD is not set
|
||||
# CONFIG_CDROM_PKTCDVD is not set
|
||||
# CONFIG_ATA_OVER_ETH is not set
|
||||
|
||||
#
|
||||
# ATA/ATAPI/MFM/RLL support
|
||||
#
|
||||
CONFIG_IDE=y
|
||||
CONFIG_BLK_DEV_IDE=y
|
||||
|
||||
#
|
||||
# Please see Documentation/ide.txt for help/info on IDE drives
|
||||
#
|
||||
# CONFIG_BLK_DEV_IDE_SATA is not set
|
||||
CONFIG_BLK_DEV_IDEDISK=y
|
||||
# CONFIG_IDEDISK_MULTI_MODE is not set
|
||||
# CONFIG_BLK_DEV_IDECD is not set
|
||||
# CONFIG_BLK_DEV_IDEFLOPPY is not set
|
||||
# CONFIG_IDE_TASK_IOCTL is not set
|
||||
|
||||
#
|
||||
# IDE chipset support/bugfixes
|
||||
#
|
||||
# CONFIG_IDE_GENERIC is not set
|
||||
# CONFIG_IDE_ARM is not set
|
||||
# CONFIG_BLK_DEV_IDEDMA is not set
|
||||
# CONFIG_IDEDMA_AUTO is not set
|
||||
# CONFIG_BLK_DEV_HD is not set
|
||||
|
||||
#
|
||||
# SCSI device support
|
||||
#
|
||||
# CONFIG_RAID_ATTRS is not set
|
||||
# CONFIG_SCSI is not set
|
||||
|
||||
#
|
||||
# Multi-device support (RAID and LVM)
|
||||
#
|
||||
# CONFIG_MD is not set
|
||||
|
||||
#
|
||||
# Fusion MPT device support
|
||||
#
|
||||
# CONFIG_FUSION is not set
|
||||
|
||||
#
|
||||
# IEEE 1394 (FireWire) support
|
||||
#
|
||||
|
||||
#
|
||||
# I2O device support
|
||||
#
|
||||
|
||||
#
|
||||
# Macintosh device drivers
|
||||
#
|
||||
# CONFIG_WINDFARM is not set
|
||||
|
||||
#
|
||||
# Network device support
|
||||
#
|
||||
CONFIG_NETDEVICES=y
|
||||
# CONFIG_DUMMY is not set
|
||||
# CONFIG_BONDING is not set
|
||||
# CONFIG_EQUALIZER is not set
|
||||
CONFIG_TUN=y
|
||||
|
||||
#
|
||||
# PHY device support
|
||||
#
|
||||
CONFIG_PHYLIB=y
|
||||
|
||||
#
|
||||
# MII PHY device drivers
|
||||
#
|
||||
# CONFIG_MARVELL_PHY is not set
|
||||
CONFIG_DAVICOM_PHY=y
|
||||
# CONFIG_QSEMI_PHY is not set
|
||||
# CONFIG_LXT_PHY is not set
|
||||
# CONFIG_CICADA_PHY is not set
|
||||
# CONFIG_FIXED_PHY is not set
|
||||
|
||||
#
|
||||
# Ethernet (10 or 100Mbit)
|
||||
#
|
||||
CONFIG_NET_ETHERNET=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_FS_ENET=y
|
||||
# CONFIG_FS_ENET_HAS_SCC is not set
|
||||
CONFIG_FS_ENET_HAS_FCC=y
|
||||
|
||||
#
|
||||
# Ethernet (1000 Mbit)
|
||||
#
|
||||
|
||||
#
|
||||
# Ethernet (10000 Mbit)
|
||||
#
|
||||
|
||||
#
|
||||
# Token Ring devices
|
||||
#
|
||||
|
||||
#
|
||||
# Wireless LAN (non-hamradio)
|
||||
#
|
||||
# CONFIG_NET_RADIO is not set
|
||||
|
||||
#
|
||||
# Wan interfaces
|
||||
#
|
||||
# CONFIG_WAN is not set
|
||||
CONFIG_PPP=y
|
||||
# CONFIG_PPP_FILTER is not set
|
||||
CONFIG_PPP_ASYNC=y
|
||||
CONFIG_PPP_SYNC_TTY=y
|
||||
CONFIG_PPP_DEFLATE=y
|
||||
# CONFIG_PPP_BSDCOMP is not set
|
||||
# CONFIG_SLIP is not set
|
||||
# CONFIG_NETPOLL is not set
|
||||
# CONFIG_NET_POLL_CONTROLLER is not set
|
||||
|
||||
#
|
||||
# ISDN subsystem
|
||||
#
|
||||
# CONFIG_ISDN is not set
|
||||
|
||||
#
|
||||
# Telephony Support
|
||||
#
|
||||
# CONFIG_PHONE is not set
|
||||
|
||||
#
|
||||
# Input device support
|
||||
#
|
||||
CONFIG_INPUT=y
|
||||
|
||||
#
|
||||
# Userland interfaces
|
||||
#
|
||||
CONFIG_INPUT_MOUSEDEV=y
|
||||
CONFIG_INPUT_MOUSEDEV_PSAUX=y
|
||||
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
|
||||
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
|
||||
# CONFIG_INPUT_JOYDEV is not set
|
||||
# CONFIG_INPUT_TSDEV is not set
|
||||
CONFIG_INPUT_EVDEV=y
|
||||
# CONFIG_INPUT_EVBUG is not set
|
||||
|
||||
#
|
||||
# Input Device Drivers
|
||||
#
|
||||
CONFIG_INPUT_KEYBOARD=y
|
||||
CONFIG_KEYBOARD_ATKBD=y
|
||||
# CONFIG_KEYBOARD_SUNKBD is not set
|
||||
# CONFIG_KEYBOARD_LKKBD is not set
|
||||
# CONFIG_KEYBOARD_XTKBD is not set
|
||||
# CONFIG_KEYBOARD_NEWTON is not set
|
||||
CONFIG_INPUT_MOUSE=y
|
||||
CONFIG_MOUSE_PS2=y
|
||||
# CONFIG_MOUSE_SERIAL is not set
|
||||
# CONFIG_MOUSE_VSXXXAA is not set
|
||||
# CONFIG_INPUT_JOYSTICK is not set
|
||||
# CONFIG_INPUT_TOUCHSCREEN is not set
|
||||
# CONFIG_INPUT_MISC is not set
|
||||
|
||||
#
|
||||
# Hardware I/O ports
|
||||
#
|
||||
CONFIG_SERIO=y
|
||||
# CONFIG_SERIO_I8042 is not set
|
||||
CONFIG_SERIO_SERPORT=y
|
||||
CONFIG_SERIO_LIBPS2=y
|
||||
# CONFIG_SERIO_RAW is not set
|
||||
# CONFIG_GAMEPORT is not set
|
||||
|
||||
#
|
||||
# Character devices
|
||||
#
|
||||
# CONFIG_VT is not set
|
||||
# CONFIG_SERIAL_NONSTANDARD is not set
|
||||
|
||||
#
|
||||
# Serial drivers
|
||||
#
|
||||
# CONFIG_SERIAL_8250 is not set
|
||||
|
||||
#
|
||||
# Non-8250 serial port support
|
||||
#
|
||||
CONFIG_SERIAL_CORE=y
|
||||
CONFIG_SERIAL_CORE_CONSOLE=y
|
||||
CONFIG_SERIAL_CPM=y
|
||||
CONFIG_SERIAL_CPM_CONSOLE=y
|
||||
CONFIG_SERIAL_CPM_SCC1=y
|
||||
# CONFIG_SERIAL_CPM_SCC2 is not set
|
||||
# CONFIG_SERIAL_CPM_SCC3 is not set
|
||||
CONFIG_SERIAL_CPM_SCC4=y
|
||||
# CONFIG_SERIAL_CPM_SMC1 is not set
|
||||
# CONFIG_SERIAL_CPM_SMC2 is not set
|
||||
CONFIG_UNIX98_PTYS=y
|
||||
CONFIG_LEGACY_PTYS=y
|
||||
CONFIG_LEGACY_PTY_COUNT=256
|
||||
|
||||
#
|
||||
# IPMI
|
||||
#
|
||||
# CONFIG_IPMI_HANDLER is not set
|
||||
|
||||
#
|
||||
# Watchdog Cards
|
||||
#
|
||||
# CONFIG_WATCHDOG is not set
|
||||
# CONFIG_NVRAM is not set
|
||||
# CONFIG_GEN_RTC is not set
|
||||
# CONFIG_DTLK is not set
|
||||
# CONFIG_R3964 is not set
|
||||
|
||||
#
|
||||
# Ftape, the floppy tape device driver
|
||||
#
|
||||
# CONFIG_AGP is not set
|
||||
# CONFIG_RAW_DRIVER is not set
|
||||
|
||||
#
|
||||
# TPM devices
|
||||
#
|
||||
|
||||
#
|
||||
# I2C support
|
||||
#
|
||||
# CONFIG_I2C is not set
|
||||
|
||||
#
|
||||
# SPI support
|
||||
#
|
||||
# CONFIG_SPI is not set
|
||||
# CONFIG_SPI_MASTER is not set
|
||||
|
||||
#
|
||||
# Dallas's 1-wire bus
|
||||
#
|
||||
# CONFIG_W1 is not set
|
||||
|
||||
#
|
||||
# Hardware Monitoring support
|
||||
#
|
||||
# CONFIG_HWMON is not set
|
||||
# CONFIG_HWMON_VID is not set
|
||||
|
||||
#
|
||||
# Misc devices
|
||||
#
|
||||
|
||||
#
|
||||
# Multimedia devices
|
||||
#
|
||||
# CONFIG_VIDEO_DEV is not set
|
||||
CONFIG_VIDEO_V4L2=y
|
||||
|
||||
#
|
||||
# Digital Video Broadcasting Devices
|
||||
#
|
||||
# CONFIG_DVB is not set
|
||||
|
||||
#
|
||||
# Graphics support
|
||||
#
|
||||
# CONFIG_FB is not set
|
||||
|
||||
#
|
||||
# Sound
|
||||
#
|
||||
# CONFIG_SOUND is not set
|
||||
|
||||
#
|
||||
# USB support
|
||||
#
|
||||
# CONFIG_USB_ARCH_HAS_HCD is not set
|
||||
# CONFIG_USB_ARCH_HAS_OHCI is not set
|
||||
# CONFIG_USB_ARCH_HAS_EHCI is not set
|
||||
|
||||
#
|
||||
# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
|
||||
#
|
||||
|
||||
#
|
||||
# USB Gadget Support
|
||||
#
|
||||
CONFIG_USB_GADGET=y
|
||||
# CONFIG_USB_GADGET_DEBUG_FILES is not set
|
||||
# CONFIG_USB_GADGET_NET2280 is not set
|
||||
# CONFIG_USB_GADGET_PXA2XX is not set
|
||||
# CONFIG_USB_GADGET_GOKU is not set
|
||||
# CONFIG_USB_GADGET_LH7A40X is not set
|
||||
# CONFIG_USB_GADGET_OMAP is not set
|
||||
# CONFIG_USB_GADGET_AT91 is not set
|
||||
# CONFIG_USB_GADGET_DUMMY_HCD is not set
|
||||
# CONFIG_USB_GADGET_DUALSPEED is not set
|
||||
|
||||
#
|
||||
# MMC/SD Card support
|
||||
#
|
||||
# CONFIG_MMC is not set
|
||||
|
||||
#
|
||||
# LED devices
|
||||
#
|
||||
# CONFIG_NEW_LEDS is not set
|
||||
|
||||
#
|
||||
# LED drivers
|
||||
#
|
||||
|
||||
#
|
||||
# LED Triggers
|
||||
#
|
||||
|
||||
#
|
||||
# InfiniBand support
|
||||
#
|
||||
|
||||
#
|
||||
# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
|
||||
#
|
||||
|
||||
#
|
||||
# Real Time Clock
|
||||
#
|
||||
|
||||
#
|
||||
# File systems
|
||||
#
|
||||
CONFIG_EXT2_FS=y
|
||||
# CONFIG_EXT2_FS_XATTR is not set
|
||||
# CONFIG_EXT2_FS_XIP is not set
|
||||
CONFIG_EXT3_FS=y
|
||||
CONFIG_EXT3_FS_XATTR=y
|
||||
# CONFIG_EXT3_FS_POSIX_ACL is not set
|
||||
# CONFIG_EXT3_FS_SECURITY is not set
|
||||
CONFIG_JBD=y
|
||||
# CONFIG_JBD_DEBUG is not set
|
||||
CONFIG_FS_MBCACHE=y
|
||||
# CONFIG_REISERFS_FS is not set
|
||||
# CONFIG_JFS_FS is not set
|
||||
CONFIG_FS_POSIX_ACL=y
|
||||
CONFIG_XFS_FS=y
|
||||
# CONFIG_XFS_QUOTA is not set
|
||||
# CONFIG_XFS_SECURITY is not set
|
||||
# CONFIG_XFS_POSIX_ACL is not set
|
||||
# CONFIG_MINIX_FS is not set
|
||||
# CONFIG_ROMFS_FS is not set
|
||||
CONFIG_INOTIFY=y
|
||||
# CONFIG_QUOTA is not set
|
||||
CONFIG_DNOTIFY=y
|
||||
# CONFIG_AUTOFS_FS is not set
|
||||
CONFIG_AUTOFS4_FS=y
|
||||
# CONFIG_FUSE_FS is not set
|
||||
|
||||
#
|
||||
# CD-ROM/DVD Filesystems
|
||||
#
|
||||
# CONFIG_ISO9660_FS is not set
|
||||
# CONFIG_UDF_FS is not set
|
||||
|
||||
#
|
||||
# DOS/FAT/NT Filesystems
|
||||
#
|
||||
# CONFIG_MSDOS_FS is not set
|
||||
# CONFIG_VFAT_FS is not set
|
||||
# CONFIG_NTFS_FS is not set
|
||||
|
||||
#
|
||||
# Pseudo filesystems
|
||||
#
|
||||
CONFIG_PROC_FS=y
|
||||
CONFIG_PROC_KCORE=y
|
||||
CONFIG_SYSFS=y
|
||||
CONFIG_TMPFS=y
|
||||
# CONFIG_HUGETLB_PAGE is not set
|
||||
CONFIG_RAMFS=y
|
||||
|
||||
#
|
||||
# Miscellaneous filesystems
|
||||
#
|
||||
# CONFIG_HFSPLUS_FS is not set
|
||||
CONFIG_CRAMFS=y
|
||||
# CONFIG_VXFS_FS is not set
|
||||
# CONFIG_HPFS_FS is not set
|
||||
# CONFIG_QNX4FS_FS is not set
|
||||
# CONFIG_SYSV_FS is not set
|
||||
# CONFIG_UFS_FS is not set
|
||||
|
||||
#
|
||||
# Network File Systems
|
||||
#
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V3=y
|
||||
CONFIG_NFS_V3_ACL=y
|
||||
# CONFIG_NFSD is not set
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_LOCKD=y
|
||||
CONFIG_LOCKD_V4=y
|
||||
CONFIG_NFS_ACL_SUPPORT=y
|
||||
CONFIG_NFS_COMMON=y
|
||||
CONFIG_SUNRPC=y
|
||||
CONFIG_SMB_FS=y
|
||||
# CONFIG_SMB_NLS_DEFAULT is not set
|
||||
# CONFIG_CIFS is not set
|
||||
# CONFIG_NCP_FS is not set
|
||||
# CONFIG_CODA_FS is not set
|
||||
|
||||
#
|
||||
# Partition Types
|
||||
#
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
# CONFIG_ACORN_PARTITION is not set
|
||||
# CONFIG_OSF_PARTITION is not set
|
||||
# CONFIG_AMIGA_PARTITION is not set
|
||||
# CONFIG_ATARI_PARTITION is not set
|
||||
# CONFIG_MAC_PARTITION is not set
|
||||
CONFIG_MSDOS_PARTITION=y
|
||||
# CONFIG_BSD_DISKLABEL is not set
|
||||
# CONFIG_MINIX_SUBPARTITION is not set
|
||||
# CONFIG_SOLARIS_X86_PARTITION is not set
|
||||
# CONFIG_UNIXWARE_DISKLABEL is not set
|
||||
# CONFIG_LDM_PARTITION is not set
|
||||
# CONFIG_SGI_PARTITION is not set
|
||||
# CONFIG_ULTRIX_PARTITION is not set
|
||||
# CONFIG_SUN_PARTITION is not set
|
||||
# CONFIG_KARMA_PARTITION is not set
|
||||
# CONFIG_EFI_PARTITION is not set
|
||||
|
||||
#
|
||||
# Native Language Support
|
||||
#
|
||||
CONFIG_NLS=y
|
||||
CONFIG_NLS_DEFAULT="iso8859-1"
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
# CONFIG_NLS_CODEPAGE_737 is not set
|
||||
# CONFIG_NLS_CODEPAGE_775 is not set
|
||||
# CONFIG_NLS_CODEPAGE_850 is not set
|
||||
# CONFIG_NLS_CODEPAGE_852 is not set
|
||||
# CONFIG_NLS_CODEPAGE_855 is not set
|
||||
# CONFIG_NLS_CODEPAGE_857 is not set
|
||||
# CONFIG_NLS_CODEPAGE_860 is not set
|
||||
# CONFIG_NLS_CODEPAGE_861 is not set
|
||||
# CONFIG_NLS_CODEPAGE_862 is not set
|
||||
# CONFIG_NLS_CODEPAGE_863 is not set
|
||||
# CONFIG_NLS_CODEPAGE_864 is not set
|
||||
# CONFIG_NLS_CODEPAGE_865 is not set
|
||||
# CONFIG_NLS_CODEPAGE_866 is not set
|
||||
# CONFIG_NLS_CODEPAGE_869 is not set
|
||||
# CONFIG_NLS_CODEPAGE_936 is not set
|
||||
# CONFIG_NLS_CODEPAGE_950 is not set
|
||||
# CONFIG_NLS_CODEPAGE_932 is not set
|
||||
# CONFIG_NLS_CODEPAGE_949 is not set
|
||||
# CONFIG_NLS_CODEPAGE_874 is not set
|
||||
# CONFIG_NLS_ISO8859_8 is not set
|
||||
# CONFIG_NLS_CODEPAGE_1250 is not set
|
||||
# CONFIG_NLS_CODEPAGE_1251 is not set
|
||||
CONFIG_NLS_ASCII=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
# CONFIG_NLS_ISO8859_2 is not set
|
||||
# CONFIG_NLS_ISO8859_3 is not set
|
||||
# CONFIG_NLS_ISO8859_4 is not set
|
||||
# CONFIG_NLS_ISO8859_5 is not set
|
||||
# CONFIG_NLS_ISO8859_6 is not set
|
||||
# CONFIG_NLS_ISO8859_7 is not set
|
||||
# CONFIG_NLS_ISO8859_9 is not set
|
||||
# CONFIG_NLS_ISO8859_13 is not set
|
||||
# CONFIG_NLS_ISO8859_14 is not set
|
||||
# CONFIG_NLS_ISO8859_15 is not set
|
||||
# CONFIG_NLS_KOI8_R is not set
|
||||
# CONFIG_NLS_KOI8_U is not set
|
||||
CONFIG_NLS_UTF8=y
|
||||
|
||||
#
|
||||
# Library routines
|
||||
#
|
||||
CONFIG_CRC_CCITT=y
|
||||
# CONFIG_CRC16 is not set
|
||||
CONFIG_CRC32=y
|
||||
# CONFIG_LIBCRC32C is not set
|
||||
CONFIG_ZLIB_INFLATE=y
|
||||
CONFIG_ZLIB_DEFLATE=y
|
||||
|
||||
#
|
||||
# Kernel hacking
|
||||
#
|
||||
# CONFIG_PRINTK_TIME is not set
|
||||
# CONFIG_MAGIC_SYSRQ is not set
|
||||
CONFIG_DEBUG_KERNEL=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
CONFIG_DETECT_SOFTLOCKUP=y
|
||||
# CONFIG_SCHEDSTATS is not set
|
||||
# CONFIG_DEBUG_SLAB is not set
|
||||
# CONFIG_DEBUG_MUTEXES is not set
|
||||
# CONFIG_DEBUG_SPINLOCK is not set
|
||||
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
|
||||
# CONFIG_DEBUG_KOBJECT is not set
|
||||
CONFIG_DEBUG_INFO=y
|
||||
# CONFIG_DEBUG_FS is not set
|
||||
# CONFIG_DEBUG_VM is not set
|
||||
# CONFIG_UNWIND_INFO is not set
|
||||
CONFIG_FORCED_INLINING=y
|
||||
# CONFIG_RCU_TORTURE_TEST is not set
|
||||
# CONFIG_DEBUGGER is not set
|
||||
# CONFIG_KGDB_CONSOLE is not set
|
||||
CONFIG_BDI_SWITCH=y
|
||||
# CONFIG_BOOTX_TEXT is not set
|
||||
# CONFIG_PPC_EARLY_DEBUG is not set
|
||||
|
||||
#
|
||||
# Security options
|
||||
#
|
||||
# CONFIG_KEYS is not set
|
||||
# CONFIG_SECURITY is not set
|
||||
|
||||
#
|
||||
# Cryptographic options
|
||||
#
|
||||
CONFIG_CRYPTO=y
|
||||
# CONFIG_CRYPTO_HMAC is not set
|
||||
# CONFIG_CRYPTO_NULL is not set
|
||||
# CONFIG_CRYPTO_MD4 is not set
|
||||
CONFIG_CRYPTO_MD5=y
|
||||
# CONFIG_CRYPTO_SHA1 is not set
|
||||
# CONFIG_CRYPTO_SHA256 is not set
|
||||
# CONFIG_CRYPTO_SHA512 is not set
|
||||
# CONFIG_CRYPTO_WP512 is not set
|
||||
# CONFIG_CRYPTO_TGR192 is not set
|
||||
CONFIG_CRYPTO_DES=y
|
||||
# CONFIG_CRYPTO_BLOWFISH is not set
|
||||
# CONFIG_CRYPTO_TWOFISH is not set
|
||||
# CONFIG_CRYPTO_SERPENT is not set
|
||||
# CONFIG_CRYPTO_AES is not set
|
||||
# CONFIG_CRYPTO_CAST5 is not set
|
||||
# CONFIG_CRYPTO_CAST6 is not set
|
||||
# CONFIG_CRYPTO_TEA is not set
|
||||
# CONFIG_CRYPTO_ARC4 is not set
|
||||
# CONFIG_CRYPTO_KHAZAD is not set
|
||||
# CONFIG_CRYPTO_ANUBIS is not set
|
||||
# CONFIG_CRYPTO_DEFLATE is not set
|
||||
# CONFIG_CRYPTO_MICHAEL_MIC is not set
|
||||
# CONFIG_CRYPTO_CRC32C is not set
|
||||
# CONFIG_CRYPTO_TEST is not set
|
||||
|
||||
#
|
||||
# Hardware crypto devices
|
||||
#
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,7 +1,7 @@
|
|||
#
|
||||
# Automatically generated make config: don't edit
|
||||
# Linux kernel version: 2.6.20-rc5
|
||||
# Mon Jan 22 22:23:43 2007
|
||||
# Fri Jan 26 00:19:02 2007
|
||||
#
|
||||
# CONFIG_PPC64 is not set
|
||||
CONFIG_PPC32=y
|
||||
|
|
@ -149,7 +149,6 @@ CONFIG_PREEMPT_NONE=y
|
|||
# CONFIG_PREEMPT is not set
|
||||
CONFIG_BINFMT_ELF=y
|
||||
# CONFIG_BINFMT_MISC is not set
|
||||
CONFIG_MATH_EMULATION=y
|
||||
CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
|
||||
CONFIG_ARCH_FLATMEM_ENABLE=y
|
||||
CONFIG_ARCH_POPULATES_NODE_MAP=y
|
||||
|
|
@ -324,6 +323,7 @@ CONFIG_MTD=y
|
|||
# User Modules And Translation Layers
|
||||
#
|
||||
CONFIG_MTD_CHAR=y
|
||||
# CONFIG_MTD_BLKDEVS is not set
|
||||
# CONFIG_MTD_BLOCK is not set
|
||||
# CONFIG_MTD_BLOCK_RO is not set
|
||||
# CONFIG_FTL is not set
|
||||
|
|
@ -366,6 +366,7 @@ CONFIG_MTD_PHYSMAP=y
|
|||
CONFIG_MTD_PHYSMAP_START=0xfe000000
|
||||
CONFIG_MTD_PHYSMAP_LEN=0x1000000
|
||||
CONFIG_MTD_PHYSMAP_BANKWIDTH=2
|
||||
# CONFIG_MTD_PHYSMAP_OF is not set
|
||||
# CONFIG_MTD_PLATRAM is not set
|
||||
|
||||
#
|
||||
|
|
@ -390,6 +391,7 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=2
|
|||
# NAND Flash Device Drivers
|
||||
#
|
||||
# CONFIG_MTD_NAND is not set
|
||||
# CONFIG_MTD_NAND_CAFE is not set
|
||||
|
||||
#
|
||||
# OneNAND Flash Device Drivers
|
||||
|
|
@ -1011,7 +1013,6 @@ CONFIG_USB=y
|
|||
CONFIG_USB_DEVICEFS=y
|
||||
# CONFIG_USB_BANDWIDTH is not set
|
||||
# CONFIG_USB_DYNAMIC_MINORS is not set
|
||||
# CONFIG_USB_MULTITHREAD_PROBE is not set
|
||||
# CONFIG_USB_OTG is not set
|
||||
|
||||
#
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
#
|
||||
# Automatically generated make config: don't edit
|
||||
# Linux kernel version: 2.6.20-rc5
|
||||
# Mon Jan 22 22:24:10 2007
|
||||
# Fri Jan 26 00:19:27 2007
|
||||
#
|
||||
# CONFIG_PPC64 is not set
|
||||
CONFIG_PPC32=y
|
||||
|
|
@ -149,7 +149,6 @@ CONFIG_PREEMPT_NONE=y
|
|||
# CONFIG_PREEMPT is not set
|
||||
CONFIG_BINFMT_ELF=y
|
||||
# CONFIG_BINFMT_MISC is not set
|
||||
CONFIG_MATH_EMULATION=y
|
||||
CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
|
||||
CONFIG_ARCH_FLATMEM_ENABLE=y
|
||||
CONFIG_ARCH_POPULATES_NODE_MAP=y
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
#
|
||||
# Automatically generated make config: don't edit
|
||||
# Linux kernel version: 2.6.20-rc5
|
||||
# Mon Jan 22 22:24:40 2007
|
||||
# Fri Jan 26 00:19:45 2007
|
||||
#
|
||||
# CONFIG_PPC64 is not set
|
||||
CONFIG_PPC32=y
|
||||
|
|
@ -150,7 +150,6 @@ CONFIG_PREEMPT_NONE=y
|
|||
# CONFIG_PREEMPT is not set
|
||||
CONFIG_BINFMT_ELF=y
|
||||
# CONFIG_BINFMT_MISC is not set
|
||||
CONFIG_MATH_EMULATION=y
|
||||
CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
|
||||
CONFIG_ARCH_FLATMEM_ENABLE=y
|
||||
CONFIG_ARCH_POPULATES_NODE_MAP=y
|
||||
|
|
|
|||
|
|
@ -0,0 +1,829 @@
|
|||
#
|
||||
# Automatically generated make config: don't edit
|
||||
# Linux kernel version: 2.6.19-rc6
|
||||
# Fri Nov 24 21:13:55 2006
|
||||
#
|
||||
# CONFIG_PPC64 is not set
|
||||
CONFIG_PPC32=y
|
||||
CONFIG_PPC_MERGE=y
|
||||
CONFIG_MMU=y
|
||||
CONFIG_GENERIC_HARDIRQS=y
|
||||
CONFIG_IRQ_PER_CPU=y
|
||||
CONFIG_RWSEM_XCHGADD_ALGORITHM=y
|
||||
CONFIG_GENERIC_HWEIGHT=y
|
||||
CONFIG_GENERIC_CALIBRATE_DELAY=y
|
||||
CONFIG_GENERIC_FIND_NEXT_BIT=y
|
||||
CONFIG_PPC=y
|
||||
CONFIG_EARLY_PRINTK=y
|
||||
CONFIG_GENERIC_NVRAM=y
|
||||
CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
|
||||
CONFIG_ARCH_MAY_HAVE_PC_FDC=y
|
||||
CONFIG_PPC_OF=y
|
||||
# CONFIG_PPC_UDBG_16550 is not set
|
||||
# CONFIG_GENERIC_TBSYNC is not set
|
||||
CONFIG_AUDIT_ARCH=y
|
||||
# CONFIG_DEFAULT_UIMAGE is not set
|
||||
|
||||
#
|
||||
# Processor support
|
||||
#
|
||||
# CONFIG_CLASSIC32 is not set
|
||||
# CONFIG_PPC_52xx is not set
|
||||
# CONFIG_PPC_82xx is not set
|
||||
# CONFIG_PPC_83xx is not set
|
||||
# CONFIG_PPC_85xx is not set
|
||||
# CONFIG_PPC_86xx is not set
|
||||
CONFIG_PPC_8xx=y
|
||||
# CONFIG_40x is not set
|
||||
# CONFIG_44x is not set
|
||||
# CONFIG_E200 is not set
|
||||
CONFIG_8xx=y
|
||||
# CONFIG_PPC_DCR_NATIVE is not set
|
||||
# CONFIG_PPC_DCR_MMIO is not set
|
||||
CONFIG_NOT_COHERENT_CACHE=y
|
||||
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
|
||||
|
||||
#
|
||||
# Code maturity level options
|
||||
#
|
||||
CONFIG_EXPERIMENTAL=y
|
||||
CONFIG_BROKEN_ON_SMP=y
|
||||
CONFIG_INIT_ENV_ARG_LIMIT=32
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_LOCALVERSION_AUTO=y
|
||||
# CONFIG_SWAP is not set
|
||||
CONFIG_SYSVIPC=y
|
||||
# CONFIG_IPC_NS is not set
|
||||
# CONFIG_POSIX_MQUEUE is not set
|
||||
# CONFIG_BSD_PROCESS_ACCT is not set
|
||||
# CONFIG_TASKSTATS is not set
|
||||
# CONFIG_UTS_NS is not set
|
||||
# CONFIG_AUDIT is not set
|
||||
# CONFIG_IKCONFIG is not set
|
||||
# CONFIG_RELAY is not set
|
||||
CONFIG_INITRAMFS_SOURCE=""
|
||||
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
|
||||
CONFIG_SYSCTL=y
|
||||
CONFIG_EMBEDDED=y
|
||||
# CONFIG_SYSCTL_SYSCALL is not set
|
||||
CONFIG_KALLSYMS=y
|
||||
# CONFIG_KALLSYMS_EXTRA_PASS is not set
|
||||
# CONFIG_HOTPLUG is not set
|
||||
CONFIG_PRINTK=y
|
||||
# CONFIG_BUG is not set
|
||||
CONFIG_ELF_CORE=y
|
||||
# CONFIG_BASE_FULL is not set
|
||||
CONFIG_FUTEX=y
|
||||
# CONFIG_EPOLL is not set
|
||||
CONFIG_SHMEM=y
|
||||
CONFIG_SLAB=y
|
||||
# CONFIG_VM_EVENT_COUNTERS is not set
|
||||
CONFIG_RT_MUTEXES=y
|
||||
# CONFIG_TINY_SHMEM is not set
|
||||
CONFIG_BASE_SMALL=1
|
||||
# CONFIG_SLOB is not set
|
||||
|
||||
#
|
||||
# Loadable module support
|
||||
#
|
||||
# CONFIG_MODULES is not set
|
||||
|
||||
#
|
||||
# Block layer
|
||||
#
|
||||
CONFIG_BLOCK=y
|
||||
# CONFIG_LBD is not set
|
||||
# CONFIG_BLK_DEV_IO_TRACE is not set
|
||||
# CONFIG_LSF is not set
|
||||
|
||||
#
|
||||
# IO Schedulers
|
||||
#
|
||||
CONFIG_IOSCHED_NOOP=y
|
||||
CONFIG_IOSCHED_AS=y
|
||||
CONFIG_IOSCHED_DEADLINE=y
|
||||
CONFIG_IOSCHED_CFQ=y
|
||||
CONFIG_DEFAULT_AS=y
|
||||
# CONFIG_DEFAULT_DEADLINE is not set
|
||||
# CONFIG_DEFAULT_CFQ is not set
|
||||
# CONFIG_DEFAULT_NOOP is not set
|
||||
CONFIG_DEFAULT_IOSCHED="anticipatory"
|
||||
# CONFIG_WANT_EARLY_SERIAL is not set
|
||||
CONFIG_EMBEDDEDBOOT=y
|
||||
# CONFIG_MPIC is not set
|
||||
|
||||
#
|
||||
# Platform support
|
||||
#
|
||||
CONFIG_CPM1=y
|
||||
# CONFIG_MPC8XXFADS is not set
|
||||
CONFIG_MPC86XADS=y
|
||||
# CONFIG_MPC885ADS is not set
|
||||
|
||||
#
|
||||
# MPC8xx CPM Options
|
||||
#
|
||||
|
||||
#
|
||||
# Generic MPC8xx Options
|
||||
#
|
||||
CONFIG_8xx_COPYBACK=y
|
||||
CONFIG_8xx_CPU6=y
|
||||
CONFIG_NO_UCODE_PATCH=y
|
||||
# CONFIG_USB_SOF_UCODE_PATCH is not set
|
||||
# CONFIG_I2C_SPI_UCODE_PATCH is not set
|
||||
# CONFIG_I2C_SPI_SMC1_UCODE_PATCH is not set
|
||||
|
||||
#
|
||||
# Kernel options
|
||||
#
|
||||
# CONFIG_HIGHMEM is not set
|
||||
# CONFIG_HZ_100 is not set
|
||||
# CONFIG_HZ_250 is not set
|
||||
CONFIG_HZ_1000=y
|
||||
CONFIG_HZ=1000
|
||||
CONFIG_PREEMPT_NONE=y
|
||||
# CONFIG_PREEMPT_VOLUNTARY is not set
|
||||
# CONFIG_PREEMPT is not set
|
||||
CONFIG_BINFMT_ELF=y
|
||||
# CONFIG_BINFMT_MISC is not set
|
||||
CONFIG_MATH_EMULATION=y
|
||||
CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
|
||||
CONFIG_ARCH_FLATMEM_ENABLE=y
|
||||
CONFIG_ARCH_POPULATES_NODE_MAP=y
|
||||
CONFIG_SELECT_MEMORY_MODEL=y
|
||||
CONFIG_FLATMEM_MANUAL=y
|
||||
# CONFIG_DISCONTIGMEM_MANUAL is not set
|
||||
# CONFIG_SPARSEMEM_MANUAL is not set
|
||||
CONFIG_FLATMEM=y
|
||||
CONFIG_FLAT_NODE_MEM_MAP=y
|
||||
# CONFIG_SPARSEMEM_STATIC is not set
|
||||
CONFIG_SPLIT_PTLOCK_CPUS=4
|
||||
# CONFIG_RESOURCES_64BIT is not set
|
||||
# CONFIG_PROC_DEVICETREE is not set
|
||||
# CONFIG_CMDLINE_BOOL is not set
|
||||
# CONFIG_PM is not set
|
||||
# CONFIG_SECCOMP is not set
|
||||
CONFIG_ISA_DMA_API=y
|
||||
|
||||
#
|
||||
# Bus options
|
||||
#
|
||||
# CONFIG_MPIC_WEIRD is not set
|
||||
# CONFIG_PPC_I8259 is not set
|
||||
CONFIG_FSL_SOC=y
|
||||
# CONFIG_PCI is not set
|
||||
# CONFIG_PCI_DOMAINS is not set
|
||||
# CONFIG_PCI_QSPAN is not set
|
||||
|
||||
#
|
||||
# PCCARD (PCMCIA/CardBus) support
|
||||
#
|
||||
|
||||
#
|
||||
# PCI Hotplug Support
|
||||
#
|
||||
|
||||
#
|
||||
# Advanced setup
|
||||
#
|
||||
# CONFIG_ADVANCED_OPTIONS is not set
|
||||
|
||||
#
|
||||
# Default settings for advanced configuration options are used
|
||||
#
|
||||
CONFIG_HIGHMEM_START=0xfe000000
|
||||
CONFIG_LOWMEM_SIZE=0x30000000
|
||||
CONFIG_KERNEL_START=0xc0000000
|
||||
CONFIG_TASK_SIZE=0x80000000
|
||||
CONFIG_CONSISTENT_START=0xff100000
|
||||
CONFIG_CONSISTENT_SIZE=0x00200000
|
||||
CONFIG_BOOT_LOAD=0x00400000
|
||||
|
||||
#
|
||||
# Networking
|
||||
#
|
||||
CONFIG_NET=y
|
||||
|
||||
#
|
||||
# Networking options
|
||||
#
|
||||
# CONFIG_NETDEBUG is not set
|
||||
CONFIG_PACKET=y
|
||||
# CONFIG_PACKET_MMAP is not set
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_XFRM=y
|
||||
# CONFIG_XFRM_USER is not set
|
||||
# CONFIG_XFRM_SUB_POLICY is not set
|
||||
# CONFIG_NET_KEY is not set
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_MULTICAST=y
|
||||
# CONFIG_IP_ADVANCED_ROUTER is not set
|
||||
CONFIG_IP_FIB_HASH=y
|
||||
CONFIG_IP_PNP=y
|
||||
# CONFIG_IP_PNP_DHCP is not set
|
||||
# CONFIG_IP_PNP_BOOTP is not set
|
||||
# CONFIG_IP_PNP_RARP is not set
|
||||
# CONFIG_NET_IPIP is not set
|
||||
# CONFIG_NET_IPGRE is not set
|
||||
# CONFIG_IP_MROUTE is not set
|
||||
# CONFIG_ARPD is not set
|
||||
CONFIG_SYN_COOKIES=y
|
||||
# CONFIG_INET_AH is not set
|
||||
# CONFIG_INET_ESP is not set
|
||||
# CONFIG_INET_IPCOMP is not set
|
||||
# CONFIG_INET_XFRM_TUNNEL is not set
|
||||
# CONFIG_INET_TUNNEL is not set
|
||||
CONFIG_INET_XFRM_MODE_TRANSPORT=y
|
||||
CONFIG_INET_XFRM_MODE_TUNNEL=y
|
||||
CONFIG_INET_XFRM_MODE_BEET=y
|
||||
CONFIG_INET_DIAG=y
|
||||
CONFIG_INET_TCP_DIAG=y
|
||||
# CONFIG_TCP_CONG_ADVANCED is not set
|
||||
CONFIG_TCP_CONG_CUBIC=y
|
||||
CONFIG_DEFAULT_TCP_CONG="cubic"
|
||||
# CONFIG_IPV6 is not set
|
||||
# CONFIG_INET6_XFRM_TUNNEL is not set
|
||||
# CONFIG_INET6_TUNNEL is not set
|
||||
# CONFIG_NETWORK_SECMARK is not set
|
||||
# CONFIG_NETFILTER is not set
|
||||
|
||||
#
|
||||
# DCCP Configuration (EXPERIMENTAL)
|
||||
#
|
||||
# CONFIG_IP_DCCP is not set
|
||||
|
||||
#
|
||||
# SCTP Configuration (EXPERIMENTAL)
|
||||
#
|
||||
# CONFIG_IP_SCTP is not set
|
||||
|
||||
#
|
||||
# TIPC Configuration (EXPERIMENTAL)
|
||||
#
|
||||
# CONFIG_TIPC is not set
|
||||
# CONFIG_ATM is not set
|
||||
# CONFIG_BRIDGE is not set
|
||||
# CONFIG_VLAN_8021Q is not set
|
||||
# CONFIG_DECNET is not set
|
||||
# CONFIG_LLC2 is not set
|
||||
# CONFIG_IPX is not set
|
||||
# CONFIG_ATALK is not set
|
||||
# CONFIG_X25 is not set
|
||||
# CONFIG_LAPB is not set
|
||||
# CONFIG_ECONET is not set
|
||||
# CONFIG_WAN_ROUTER is not set
|
||||
|
||||
#
|
||||
# QoS and/or fair queueing
|
||||
#
|
||||
# CONFIG_NET_SCHED is not set
|
||||
|
||||
#
|
||||
# Network testing
|
||||
#
|
||||
# CONFIG_NET_PKTGEN is not set
|
||||
# CONFIG_HAMRADIO is not set
|
||||
# CONFIG_IRDA is not set
|
||||
# CONFIG_BT is not set
|
||||
# CONFIG_IEEE80211 is not set
|
||||
|
||||
#
|
||||
# Device Drivers
|
||||
#
|
||||
|
||||
#
|
||||
# Generic Driver Options
|
||||
#
|
||||
CONFIG_STANDALONE=y
|
||||
CONFIG_PREVENT_FIRMWARE_BUILD=y
|
||||
# CONFIG_SYS_HYPERVISOR is not set
|
||||
|
||||
#
|
||||
# Connector - unified userspace <-> kernelspace linker
|
||||
#
|
||||
# CONFIG_CONNECTOR is not set
|
||||
|
||||
#
|
||||
# Memory Technology Devices (MTD)
|
||||
#
|
||||
# CONFIG_MTD is not set
|
||||
|
||||
#
|
||||
# Parallel port support
|
||||
#
|
||||
# CONFIG_PARPORT is not set
|
||||
|
||||
#
|
||||
# Plug and Play support
|
||||
#
|
||||
|
||||
#
|
||||
# Block devices
|
||||
#
|
||||
# CONFIG_BLK_DEV_FD is not set
|
||||
# CONFIG_BLK_DEV_COW_COMMON is not set
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
# CONFIG_BLK_DEV_CRYPTOLOOP is not set
|
||||
# CONFIG_BLK_DEV_NBD is not set
|
||||
# CONFIG_BLK_DEV_RAM is not set
|
||||
# CONFIG_BLK_DEV_INITRD is not set
|
||||
# CONFIG_CDROM_PKTCDVD is not set
|
||||
# CONFIG_ATA_OVER_ETH is not set
|
||||
|
||||
#
|
||||
# Misc devices
|
||||
#
|
||||
# CONFIG_TIFM_CORE is not set
|
||||
|
||||
#
|
||||
# ATA/ATAPI/MFM/RLL support
|
||||
#
|
||||
# CONFIG_IDE is not set
|
||||
|
||||
#
|
||||
# SCSI device support
|
||||
#
|
||||
# CONFIG_RAID_ATTRS is not set
|
||||
# CONFIG_SCSI is not set
|
||||
# CONFIG_SCSI_NETLINK is not set
|
||||
|
||||
#
|
||||
# Serial ATA (prod) and Parallel ATA (experimental) drivers
|
||||
#
|
||||
# CONFIG_ATA is not set
|
||||
|
||||
#
|
||||
# Multi-device support (RAID and LVM)
|
||||
#
|
||||
# CONFIG_MD is not set
|
||||
|
||||
#
|
||||
# Fusion MPT device support
|
||||
#
|
||||
# CONFIG_FUSION is not set
|
||||
|
||||
#
|
||||
# IEEE 1394 (FireWire) support
|
||||
#
|
||||
|
||||
#
|
||||
# I2O device support
|
||||
#
|
||||
|
||||
#
|
||||
# Macintosh device drivers
|
||||
#
|
||||
# CONFIG_WINDFARM is not set
|
||||
|
||||
#
|
||||
# Network device support
|
||||
#
|
||||
CONFIG_NETDEVICES=y
|
||||
# CONFIG_DUMMY is not set
|
||||
# CONFIG_BONDING is not set
|
||||
# CONFIG_EQUALIZER is not set
|
||||
# CONFIG_TUN is not set
|
||||
|
||||
#
|
||||
# PHY device support
|
||||
#
|
||||
CONFIG_PHYLIB=y
|
||||
|
||||
#
|
||||
# MII PHY device drivers
|
||||
#
|
||||
# CONFIG_MARVELL_PHY is not set
|
||||
# CONFIG_DAVICOM_PHY is not set
|
||||
# CONFIG_QSEMI_PHY is not set
|
||||
# CONFIG_LXT_PHY is not set
|
||||
# CONFIG_CICADA_PHY is not set
|
||||
# CONFIG_VITESSE_PHY is not set
|
||||
# CONFIG_SMSC_PHY is not set
|
||||
CONFIG_FIXED_PHY=y
|
||||
CONFIG_FIXED_MII_10_FDX=y
|
||||
CONFIG_FIXED_MII_100_FDX=y
|
||||
|
||||
#
|
||||
# Ethernet (10 or 100Mbit)
|
||||
#
|
||||
CONFIG_NET_ETHERNET=y
|
||||
CONFIG_MII=y
|
||||
# CONFIG_FEC_8XX is not set
|
||||
CONFIG_FS_ENET=y
|
||||
CONFIG_FS_ENET_HAS_SCC=y
|
||||
CONFIG_FS_ENET_HAS_FEC=y
|
||||
|
||||
#
|
||||
# Ethernet (1000 Mbit)
|
||||
#
|
||||
|
||||
#
|
||||
# Ethernet (10000 Mbit)
|
||||
#
|
||||
|
||||
#
|
||||
# Token Ring devices
|
||||
#
|
||||
|
||||
#
|
||||
# Wireless LAN (non-hamradio)
|
||||
#
|
||||
# CONFIG_NET_RADIO is not set
|
||||
|
||||
#
|
||||
# Wan interfaces
|
||||
#
|
||||
# CONFIG_WAN is not set
|
||||
# CONFIG_PPP is not set
|
||||
# CONFIG_SLIP is not set
|
||||
# CONFIG_SHAPER is not set
|
||||
# CONFIG_NETCONSOLE is not set
|
||||
# CONFIG_NETPOLL is not set
|
||||
# CONFIG_NET_POLL_CONTROLLER is not set
|
||||
|
||||
#
|
||||
# ISDN subsystem
|
||||
#
|
||||
# CONFIG_ISDN is not set
|
||||
|
||||
#
|
||||
# Telephony Support
|
||||
#
|
||||
# CONFIG_PHONE is not set
|
||||
|
||||
#
|
||||
# Input device support
|
||||
#
|
||||
CONFIG_INPUT=y
|
||||
# CONFIG_INPUT_FF_MEMLESS is not set
|
||||
|
||||
#
|
||||
# Userland interfaces
|
||||
#
|
||||
CONFIG_INPUT_MOUSEDEV=y
|
||||
CONFIG_INPUT_MOUSEDEV_PSAUX=y
|
||||
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
|
||||
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
|
||||
# CONFIG_INPUT_JOYDEV is not set
|
||||
# CONFIG_INPUT_TSDEV is not set
|
||||
# CONFIG_INPUT_EVDEV is not set
|
||||
# CONFIG_INPUT_EVBUG is not set
|
||||
|
||||
#
|
||||
# Input Device Drivers
|
||||
#
|
||||
CONFIG_INPUT_KEYBOARD=y
|
||||
CONFIG_KEYBOARD_ATKBD=y
|
||||
# CONFIG_KEYBOARD_SUNKBD is not set
|
||||
# CONFIG_KEYBOARD_LKKBD is not set
|
||||
# CONFIG_KEYBOARD_XTKBD is not set
|
||||
# CONFIG_KEYBOARD_NEWTON is not set
|
||||
# CONFIG_KEYBOARD_STOWAWAY is not set
|
||||
CONFIG_INPUT_MOUSE=y
|
||||
CONFIG_MOUSE_PS2=y
|
||||
# CONFIG_MOUSE_SERIAL is not set
|
||||
# CONFIG_MOUSE_VSXXXAA is not set
|
||||
# CONFIG_INPUT_JOYSTICK is not set
|
||||
# CONFIG_INPUT_TOUCHSCREEN is not set
|
||||
# CONFIG_INPUT_MISC is not set
|
||||
|
||||
#
|
||||
# Hardware I/O ports
|
||||
#
|
||||
CONFIG_SERIO=y
|
||||
CONFIG_SERIO_I8042=y
|
||||
CONFIG_SERIO_SERPORT=y
|
||||
CONFIG_SERIO_LIBPS2=y
|
||||
# CONFIG_SERIO_RAW is not set
|
||||
# CONFIG_GAMEPORT is not set
|
||||
|
||||
#
|
||||
# Character devices
|
||||
#
|
||||
# CONFIG_VT is not set
|
||||
# CONFIG_SERIAL_NONSTANDARD is not set
|
||||
|
||||
#
|
||||
# Serial drivers
|
||||
#
|
||||
# CONFIG_SERIAL_8250 is not set
|
||||
|
||||
#
|
||||
# Non-8250 serial port support
|
||||
#
|
||||
CONFIG_SERIAL_CORE=y
|
||||
CONFIG_SERIAL_CORE_CONSOLE=y
|
||||
CONFIG_SERIAL_CPM=y
|
||||
CONFIG_SERIAL_CPM_CONSOLE=y
|
||||
# CONFIG_SERIAL_CPM_SCC1 is not set
|
||||
# CONFIG_SERIAL_CPM_SCC2 is not set
|
||||
# CONFIG_SERIAL_CPM_SCC3 is not set
|
||||
# CONFIG_SERIAL_CPM_SCC4 is not set
|
||||
CONFIG_SERIAL_CPM_SMC1=y
|
||||
CONFIG_SERIAL_CPM_SMC2=y
|
||||
CONFIG_UNIX98_PTYS=y
|
||||
# CONFIG_LEGACY_PTYS is not set
|
||||
|
||||
#
|
||||
# IPMI
|
||||
#
|
||||
# CONFIG_IPMI_HANDLER is not set
|
||||
|
||||
#
|
||||
# Watchdog Cards
|
||||
#
|
||||
# CONFIG_WATCHDOG is not set
|
||||
CONFIG_HW_RANDOM=y
|
||||
# CONFIG_NVRAM is not set
|
||||
CONFIG_GEN_RTC=y
|
||||
# CONFIG_GEN_RTC_X is not set
|
||||
# CONFIG_DTLK is not set
|
||||
# CONFIG_R3964 is not set
|
||||
|
||||
#
|
||||
# Ftape, the floppy tape device driver
|
||||
#
|
||||
# CONFIG_RAW_DRIVER is not set
|
||||
|
||||
#
|
||||
# TPM devices
|
||||
#
|
||||
# CONFIG_TCG_TPM is not set
|
||||
|
||||
#
|
||||
# I2C support
|
||||
#
|
||||
# CONFIG_I2C is not set
|
||||
|
||||
#
|
||||
# SPI support
|
||||
#
|
||||
# CONFIG_SPI is not set
|
||||
# CONFIG_SPI_MASTER is not set
|
||||
|
||||
#
|
||||
# Dallas's 1-wire bus
|
||||
#
|
||||
# CONFIG_W1 is not set
|
||||
|
||||
#
|
||||
# Hardware Monitoring support
|
||||
#
|
||||
CONFIG_HWMON=y
|
||||
# CONFIG_HWMON_VID is not set
|
||||
# CONFIG_SENSORS_ABITUGURU is not set
|
||||
# CONFIG_SENSORS_F71805F is not set
|
||||
# CONFIG_SENSORS_VT1211 is not set
|
||||
# CONFIG_HWMON_DEBUG_CHIP is not set
|
||||
|
||||
#
|
||||
# Multimedia devices
|
||||
#
|
||||
# CONFIG_VIDEO_DEV is not set
|
||||
|
||||
#
|
||||
# Digital Video Broadcasting Devices
|
||||
#
|
||||
# CONFIG_DVB is not set
|
||||
|
||||
#
|
||||
# Graphics support
|
||||
#
|
||||
CONFIG_FIRMWARE_EDID=y
|
||||
# CONFIG_FB is not set
|
||||
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
|
||||
|
||||
#
|
||||
# Sound
|
||||
#
|
||||
# CONFIG_SOUND is not set
|
||||
|
||||
#
|
||||
# USB support
|
||||
#
|
||||
# CONFIG_USB_ARCH_HAS_HCD is not set
|
||||
# CONFIG_USB_ARCH_HAS_OHCI is not set
|
||||
# CONFIG_USB_ARCH_HAS_EHCI is not set
|
||||
|
||||
#
|
||||
# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
|
||||
#
|
||||
|
||||
#
|
||||
# USB Gadget Support
|
||||
#
|
||||
# CONFIG_USB_GADGET is not set
|
||||
|
||||
#
|
||||
# MMC/SD Card support
|
||||
#
|
||||
# CONFIG_MMC is not set
|
||||
|
||||
#
|
||||
# LED devices
|
||||
#
|
||||
# CONFIG_NEW_LEDS is not set
|
||||
|
||||
#
|
||||
# LED drivers
|
||||
#
|
||||
|
||||
#
|
||||
# LED Triggers
|
||||
#
|
||||
|
||||
#
|
||||
# InfiniBand support
|
||||
#
|
||||
|
||||
#
|
||||
# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
|
||||
#
|
||||
|
||||
#
|
||||
# Real Time Clock
|
||||
#
|
||||
# CONFIG_RTC_CLASS is not set
|
||||
|
||||
#
|
||||
# DMA Engine support
|
||||
#
|
||||
# CONFIG_DMA_ENGINE is not set
|
||||
|
||||
#
|
||||
# DMA Clients
|
||||
#
|
||||
|
||||
#
|
||||
# DMA Devices
|
||||
#
|
||||
|
||||
#
|
||||
# File systems
|
||||
#
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT2_FS_XATTR=y
|
||||
# CONFIG_EXT2_FS_POSIX_ACL is not set
|
||||
# CONFIG_EXT2_FS_SECURITY is not set
|
||||
# CONFIG_EXT2_FS_XIP is not set
|
||||
CONFIG_EXT3_FS=y
|
||||
CONFIG_EXT3_FS_XATTR=y
|
||||
# CONFIG_EXT3_FS_POSIX_ACL is not set
|
||||
# CONFIG_EXT3_FS_SECURITY is not set
|
||||
# CONFIG_EXT4DEV_FS is not set
|
||||
CONFIG_JBD=y
|
||||
# CONFIG_JBD_DEBUG is not set
|
||||
CONFIG_FS_MBCACHE=y
|
||||
# CONFIG_REISERFS_FS is not set
|
||||
# CONFIG_JFS_FS is not set
|
||||
# CONFIG_FS_POSIX_ACL is not set
|
||||
# CONFIG_XFS_FS is not set
|
||||
# CONFIG_GFS2_FS is not set
|
||||
# CONFIG_OCFS2_FS is not set
|
||||
# CONFIG_MINIX_FS is not set
|
||||
# CONFIG_ROMFS_FS is not set
|
||||
CONFIG_INOTIFY=y
|
||||
CONFIG_INOTIFY_USER=y
|
||||
# CONFIG_QUOTA is not set
|
||||
CONFIG_DNOTIFY=y
|
||||
# CONFIG_AUTOFS_FS is not set
|
||||
# CONFIG_AUTOFS4_FS is not set
|
||||
# CONFIG_FUSE_FS is not set
|
||||
|
||||
#
|
||||
# CD-ROM/DVD Filesystems
|
||||
#
|
||||
# CONFIG_ISO9660_FS is not set
|
||||
# CONFIG_UDF_FS is not set
|
||||
|
||||
#
|
||||
# DOS/FAT/NT Filesystems
|
||||
#
|
||||
# CONFIG_MSDOS_FS is not set
|
||||
# CONFIG_VFAT_FS is not set
|
||||
# CONFIG_NTFS_FS is not set
|
||||
|
||||
#
|
||||
# Pseudo filesystems
|
||||
#
|
||||
CONFIG_PROC_FS=y
|
||||
# CONFIG_PROC_KCORE is not set
|
||||
CONFIG_PROC_SYSCTL=y
|
||||
CONFIG_SYSFS=y
|
||||
CONFIG_TMPFS=y
|
||||
# CONFIG_TMPFS_POSIX_ACL is not set
|
||||
# CONFIG_HUGETLB_PAGE is not set
|
||||
CONFIG_RAMFS=y
|
||||
# CONFIG_CONFIGFS_FS is not set
|
||||
|
||||
#
|
||||
# Miscellaneous filesystems
|
||||
#
|
||||
# CONFIG_ADFS_FS is not set
|
||||
# CONFIG_AFFS_FS is not set
|
||||
# CONFIG_HFS_FS is not set
|
||||
# CONFIG_HFSPLUS_FS is not set
|
||||
# CONFIG_BEFS_FS is not set
|
||||
# CONFIG_BFS_FS is not set
|
||||
# CONFIG_EFS_FS is not set
|
||||
CONFIG_CRAMFS=y
|
||||
# CONFIG_VXFS_FS is not set
|
||||
# CONFIG_HPFS_FS is not set
|
||||
# CONFIG_QNX4FS_FS is not set
|
||||
# CONFIG_SYSV_FS is not set
|
||||
# CONFIG_UFS_FS is not set
|
||||
|
||||
#
|
||||
# Network File Systems
|
||||
#
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V3=y
|
||||
# CONFIG_NFS_V3_ACL is not set
|
||||
# CONFIG_NFS_V4 is not set
|
||||
# CONFIG_NFS_DIRECTIO is not set
|
||||
# CONFIG_NFSD is not set
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_LOCKD=y
|
||||
CONFIG_LOCKD_V4=y
|
||||
CONFIG_NFS_COMMON=y
|
||||
CONFIG_SUNRPC=y
|
||||
# CONFIG_RPCSEC_GSS_KRB5 is not set
|
||||
# CONFIG_RPCSEC_GSS_SPKM3 is not set
|
||||
# CONFIG_SMB_FS is not set
|
||||
# CONFIG_CIFS is not set
|
||||
# CONFIG_NCP_FS is not set
|
||||
# CONFIG_CODA_FS is not set
|
||||
# CONFIG_AFS_FS is not set
|
||||
# CONFIG_9P_FS is not set
|
||||
|
||||
#
|
||||
# Partition Types
|
||||
#
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
# CONFIG_ACORN_PARTITION is not set
|
||||
# CONFIG_OSF_PARTITION is not set
|
||||
# CONFIG_AMIGA_PARTITION is not set
|
||||
# CONFIG_ATARI_PARTITION is not set
|
||||
# CONFIG_MAC_PARTITION is not set
|
||||
CONFIG_MSDOS_PARTITION=y
|
||||
# CONFIG_BSD_DISKLABEL is not set
|
||||
# CONFIG_MINIX_SUBPARTITION is not set
|
||||
# CONFIG_SOLARIS_X86_PARTITION is not set
|
||||
# CONFIG_UNIXWARE_DISKLABEL is not set
|
||||
# CONFIG_LDM_PARTITION is not set
|
||||
# CONFIG_SGI_PARTITION is not set
|
||||
# CONFIG_ULTRIX_PARTITION is not set
|
||||
# CONFIG_SUN_PARTITION is not set
|
||||
# CONFIG_KARMA_PARTITION is not set
|
||||
# CONFIG_EFI_PARTITION is not set
|
||||
|
||||
#
|
||||
# Native Language Support
|
||||
#
|
||||
# CONFIG_NLS is not set
|
||||
|
||||
#
|
||||
# Library routines
|
||||
#
|
||||
CONFIG_CRC_CCITT=y
|
||||
# CONFIG_CRC16 is not set
|
||||
CONFIG_CRC32=y
|
||||
# CONFIG_LIBCRC32C is not set
|
||||
CONFIG_ZLIB_INFLATE=y
|
||||
CONFIG_PLIST=y
|
||||
|
||||
#
|
||||
# Instrumentation Support
|
||||
#
|
||||
# CONFIG_PROFILING is not set
|
||||
|
||||
#
|
||||
# Kernel hacking
|
||||
#
|
||||
# CONFIG_PRINTK_TIME is not set
|
||||
CONFIG_ENABLE_MUST_CHECK=y
|
||||
# CONFIG_MAGIC_SYSRQ is not set
|
||||
# CONFIG_UNUSED_SYMBOLS is not set
|
||||
# CONFIG_DEBUG_KERNEL is not set
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
# CONFIG_DEBUG_FS is not set
|
||||
# CONFIG_UNWIND_INFO is not set
|
||||
# CONFIG_HEADERS_CHECK is not set
|
||||
# CONFIG_BOOTX_TEXT is not set
|
||||
# CONFIG_PPC_EARLY_DEBUG is not set
|
||||
|
||||
#
|
||||
# Security options
|
||||
#
|
||||
# CONFIG_KEYS is not set
|
||||
# CONFIG_SECURITY is not set
|
||||
|
||||
#
|
||||
# Cryptographic options
|
||||
#
|
||||
# CONFIG_CRYPTO is not set
|
||||
|
|
@ -0,0 +1,827 @@
|
|||
#
|
||||
# Automatically generated make config: don't edit
|
||||
# Linux kernel version: 2.6.19-rc4
|
||||
# Fri Nov 10 21:30:40 2006
|
||||
#
|
||||
# CONFIG_PPC64 is not set
|
||||
CONFIG_PPC32=y
|
||||
CONFIG_PPC_MERGE=y
|
||||
CONFIG_MMU=y
|
||||
CONFIG_GENERIC_HARDIRQS=y
|
||||
CONFIG_IRQ_PER_CPU=y
|
||||
CONFIG_RWSEM_XCHGADD_ALGORITHM=y
|
||||
CONFIG_GENERIC_HWEIGHT=y
|
||||
CONFIG_GENERIC_CALIBRATE_DELAY=y
|
||||
CONFIG_GENERIC_FIND_NEXT_BIT=y
|
||||
CONFIG_PPC=y
|
||||
CONFIG_EARLY_PRINTK=y
|
||||
CONFIG_GENERIC_NVRAM=y
|
||||
CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
|
||||
CONFIG_ARCH_MAY_HAVE_PC_FDC=y
|
||||
CONFIG_PPC_OF=y
|
||||
# CONFIG_PPC_UDBG_16550 is not set
|
||||
# CONFIG_GENERIC_TBSYNC is not set
|
||||
CONFIG_AUDIT_ARCH=y
|
||||
# CONFIG_DEFAULT_UIMAGE is not set
|
||||
|
||||
#
|
||||
# Processor support
|
||||
#
|
||||
# CONFIG_CLASSIC32 is not set
|
||||
# CONFIG_PPC_52xx is not set
|
||||
# CONFIG_PPC_82xx is not set
|
||||
# CONFIG_PPC_83xx is not set
|
||||
# CONFIG_PPC_85xx is not set
|
||||
# CONFIG_PPC_86xx is not set
|
||||
CONFIG_PPC_8xx=y
|
||||
# CONFIG_40x is not set
|
||||
# CONFIG_44x is not set
|
||||
# CONFIG_E200 is not set
|
||||
CONFIG_8xx=y
|
||||
CONFIG_NOT_COHERENT_CACHE=y
|
||||
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
|
||||
|
||||
#
|
||||
# Code maturity level options
|
||||
#
|
||||
CONFIG_EXPERIMENTAL=y
|
||||
CONFIG_BROKEN_ON_SMP=y
|
||||
CONFIG_INIT_ENV_ARG_LIMIT=32
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_LOCALVERSION_AUTO=y
|
||||
# CONFIG_SWAP is not set
|
||||
CONFIG_SYSVIPC=y
|
||||
# CONFIG_IPC_NS is not set
|
||||
# CONFIG_POSIX_MQUEUE is not set
|
||||
# CONFIG_BSD_PROCESS_ACCT is not set
|
||||
# CONFIG_TASKSTATS is not set
|
||||
# CONFIG_UTS_NS is not set
|
||||
# CONFIG_AUDIT is not set
|
||||
# CONFIG_IKCONFIG is not set
|
||||
# CONFIG_RELAY is not set
|
||||
CONFIG_INITRAMFS_SOURCE=""
|
||||
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
|
||||
CONFIG_SYSCTL=y
|
||||
CONFIG_EMBEDDED=y
|
||||
# CONFIG_SYSCTL_SYSCALL is not set
|
||||
CONFIG_KALLSYMS=y
|
||||
# CONFIG_KALLSYMS_EXTRA_PASS is not set
|
||||
# CONFIG_HOTPLUG is not set
|
||||
CONFIG_PRINTK=y
|
||||
# CONFIG_BUG is not set
|
||||
CONFIG_ELF_CORE=y
|
||||
# CONFIG_BASE_FULL is not set
|
||||
CONFIG_FUTEX=y
|
||||
# CONFIG_EPOLL is not set
|
||||
CONFIG_SHMEM=y
|
||||
CONFIG_SLAB=y
|
||||
# CONFIG_VM_EVENT_COUNTERS is not set
|
||||
CONFIG_RT_MUTEXES=y
|
||||
# CONFIG_TINY_SHMEM is not set
|
||||
CONFIG_BASE_SMALL=1
|
||||
# CONFIG_SLOB is not set
|
||||
|
||||
#
|
||||
# Loadable module support
|
||||
#
|
||||
# CONFIG_MODULES is not set
|
||||
|
||||
#
|
||||
# Block layer
|
||||
#
|
||||
CONFIG_BLOCK=y
|
||||
# CONFIG_LBD is not set
|
||||
# CONFIG_BLK_DEV_IO_TRACE is not set
|
||||
# CONFIG_LSF is not set
|
||||
|
||||
#
|
||||
# IO Schedulers
|
||||
#
|
||||
CONFIG_IOSCHED_NOOP=y
|
||||
CONFIG_IOSCHED_AS=y
|
||||
CONFIG_IOSCHED_DEADLINE=y
|
||||
CONFIG_IOSCHED_CFQ=y
|
||||
CONFIG_DEFAULT_AS=y
|
||||
# CONFIG_DEFAULT_DEADLINE is not set
|
||||
# CONFIG_DEFAULT_CFQ is not set
|
||||
# CONFIG_DEFAULT_NOOP is not set
|
||||
CONFIG_DEFAULT_IOSCHED="anticipatory"
|
||||
# CONFIG_WANT_EARLY_SERIAL is not set
|
||||
CONFIG_EMBEDDEDBOOT=y
|
||||
# CONFIG_MPIC is not set
|
||||
|
||||
#
|
||||
# Platform support
|
||||
#
|
||||
CONFIG_CPM1=y
|
||||
# CONFIG_MPC8XXFADS is not set
|
||||
# CONFIG_MPC86XADS is not set
|
||||
CONFIG_MPC885ADS=y
|
||||
|
||||
#
|
||||
# MPC8xx CPM Options
|
||||
#
|
||||
|
||||
#
|
||||
# Generic MPC8xx Options
|
||||
#
|
||||
CONFIG_8xx_COPYBACK=y
|
||||
# CONFIG_8xx_CPU6 is not set
|
||||
CONFIG_NO_UCODE_PATCH=y
|
||||
# CONFIG_USB_SOF_UCODE_PATCH is not set
|
||||
# CONFIG_I2C_SPI_UCODE_PATCH is not set
|
||||
# CONFIG_I2C_SPI_SMC1_UCODE_PATCH is not set
|
||||
|
||||
#
|
||||
# Kernel options
|
||||
#
|
||||
# CONFIG_HIGHMEM is not set
|
||||
# CONFIG_HZ_100 is not set
|
||||
# CONFIG_HZ_250 is not set
|
||||
CONFIG_HZ_1000=y
|
||||
CONFIG_HZ=1000
|
||||
CONFIG_PREEMPT_NONE=y
|
||||
# CONFIG_PREEMPT_VOLUNTARY is not set
|
||||
# CONFIG_PREEMPT is not set
|
||||
CONFIG_BINFMT_ELF=y
|
||||
# CONFIG_BINFMT_MISC is not set
|
||||
CONFIG_MATH_EMULATION=y
|
||||
CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
|
||||
CONFIG_ARCH_FLATMEM_ENABLE=y
|
||||
CONFIG_ARCH_POPULATES_NODE_MAP=y
|
||||
CONFIG_SELECT_MEMORY_MODEL=y
|
||||
CONFIG_FLATMEM_MANUAL=y
|
||||
# CONFIG_DISCONTIGMEM_MANUAL is not set
|
||||
# CONFIG_SPARSEMEM_MANUAL is not set
|
||||
CONFIG_FLATMEM=y
|
||||
CONFIG_FLAT_NODE_MEM_MAP=y
|
||||
# CONFIG_SPARSEMEM_STATIC is not set
|
||||
CONFIG_SPLIT_PTLOCK_CPUS=4
|
||||
# CONFIG_RESOURCES_64BIT is not set
|
||||
# CONFIG_PROC_DEVICETREE is not set
|
||||
# CONFIG_CMDLINE_BOOL is not set
|
||||
# CONFIG_PM is not set
|
||||
# CONFIG_SECCOMP is not set
|
||||
CONFIG_ISA_DMA_API=y
|
||||
|
||||
#
|
||||
# Bus options
|
||||
#
|
||||
# CONFIG_MPIC_WEIRD is not set
|
||||
# CONFIG_PPC_I8259 is not set
|
||||
CONFIG_FSL_SOC=y
|
||||
# CONFIG_PCI is not set
|
||||
# CONFIG_PCI_DOMAINS is not set
|
||||
# CONFIG_PCI_QSPAN is not set
|
||||
|
||||
#
|
||||
# PCCARD (PCMCIA/CardBus) support
|
||||
#
|
||||
|
||||
#
|
||||
# PCI Hotplug Support
|
||||
#
|
||||
|
||||
#
|
||||
# Advanced setup
|
||||
#
|
||||
# CONFIG_ADVANCED_OPTIONS is not set
|
||||
|
||||
#
|
||||
# Default settings for advanced configuration options are used
|
||||
#
|
||||
CONFIG_HIGHMEM_START=0xfe000000
|
||||
CONFIG_LOWMEM_SIZE=0x30000000
|
||||
CONFIG_KERNEL_START=0xc0000000
|
||||
CONFIG_TASK_SIZE=0x80000000
|
||||
CONFIG_CONSISTENT_START=0xff100000
|
||||
CONFIG_CONSISTENT_SIZE=0x00200000
|
||||
CONFIG_BOOT_LOAD=0x00400000
|
||||
|
||||
#
|
||||
# Networking
|
||||
#
|
||||
CONFIG_NET=y
|
||||
|
||||
#
|
||||
# Networking options
|
||||
#
|
||||
# CONFIG_NETDEBUG is not set
|
||||
CONFIG_PACKET=y
|
||||
# CONFIG_PACKET_MMAP is not set
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_XFRM=y
|
||||
# CONFIG_XFRM_USER is not set
|
||||
# CONFIG_XFRM_SUB_POLICY is not set
|
||||
# CONFIG_NET_KEY is not set
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_MULTICAST=y
|
||||
# CONFIG_IP_ADVANCED_ROUTER is not set
|
||||
CONFIG_IP_FIB_HASH=y
|
||||
CONFIG_IP_PNP=y
|
||||
# CONFIG_IP_PNP_DHCP is not set
|
||||
# CONFIG_IP_PNP_BOOTP is not set
|
||||
# CONFIG_IP_PNP_RARP is not set
|
||||
# CONFIG_NET_IPIP is not set
|
||||
# CONFIG_NET_IPGRE is not set
|
||||
# CONFIG_IP_MROUTE is not set
|
||||
# CONFIG_ARPD is not set
|
||||
CONFIG_SYN_COOKIES=y
|
||||
# CONFIG_INET_AH is not set
|
||||
# CONFIG_INET_ESP is not set
|
||||
# CONFIG_INET_IPCOMP is not set
|
||||
# CONFIG_INET_XFRM_TUNNEL is not set
|
||||
# CONFIG_INET_TUNNEL is not set
|
||||
CONFIG_INET_XFRM_MODE_TRANSPORT=y
|
||||
CONFIG_INET_XFRM_MODE_TUNNEL=y
|
||||
CONFIG_INET_XFRM_MODE_BEET=y
|
||||
CONFIG_INET_DIAG=y
|
||||
CONFIG_INET_TCP_DIAG=y
|
||||
# CONFIG_TCP_CONG_ADVANCED is not set
|
||||
CONFIG_TCP_CONG_CUBIC=y
|
||||
CONFIG_DEFAULT_TCP_CONG="cubic"
|
||||
# CONFIG_IPV6 is not set
|
||||
# CONFIG_INET6_XFRM_TUNNEL is not set
|
||||
# CONFIG_INET6_TUNNEL is not set
|
||||
# CONFIG_NETWORK_SECMARK is not set
|
||||
# CONFIG_NETFILTER is not set
|
||||
|
||||
#
|
||||
# DCCP Configuration (EXPERIMENTAL)
|
||||
#
|
||||
# CONFIG_IP_DCCP is not set
|
||||
|
||||
#
|
||||
# SCTP Configuration (EXPERIMENTAL)
|
||||
#
|
||||
# CONFIG_IP_SCTP is not set
|
||||
|
||||
#
|
||||
# TIPC Configuration (EXPERIMENTAL)
|
||||
#
|
||||
# CONFIG_TIPC is not set
|
||||
# CONFIG_ATM is not set
|
||||
# CONFIG_BRIDGE is not set
|
||||
# CONFIG_VLAN_8021Q is not set
|
||||
# CONFIG_DECNET is not set
|
||||
# CONFIG_LLC2 is not set
|
||||
# CONFIG_IPX is not set
|
||||
# CONFIG_ATALK is not set
|
||||
# CONFIG_X25 is not set
|
||||
# CONFIG_LAPB is not set
|
||||
# CONFIG_ECONET is not set
|
||||
# CONFIG_WAN_ROUTER is not set
|
||||
|
||||
#
|
||||
# QoS and/or fair queueing
|
||||
#
|
||||
# CONFIG_NET_SCHED is not set
|
||||
|
||||
#
|
||||
# Network testing
|
||||
#
|
||||
# CONFIG_NET_PKTGEN is not set
|
||||
# CONFIG_HAMRADIO is not set
|
||||
# CONFIG_IRDA is not set
|
||||
# CONFIG_BT is not set
|
||||
# CONFIG_IEEE80211 is not set
|
||||
|
||||
#
|
||||
# Device Drivers
|
||||
#
|
||||
|
||||
#
|
||||
# Generic Driver Options
|
||||
#
|
||||
CONFIG_STANDALONE=y
|
||||
CONFIG_PREVENT_FIRMWARE_BUILD=y
|
||||
# CONFIG_SYS_HYPERVISOR is not set
|
||||
|
||||
#
|
||||
# Connector - unified userspace <-> kernelspace linker
|
||||
#
|
||||
# CONFIG_CONNECTOR is not set
|
||||
|
||||
#
|
||||
# Memory Technology Devices (MTD)
|
||||
#
|
||||
# CONFIG_MTD is not set
|
||||
|
||||
#
|
||||
# Parallel port support
|
||||
#
|
||||
# CONFIG_PARPORT is not set
|
||||
|
||||
#
|
||||
# Plug and Play support
|
||||
#
|
||||
|
||||
#
|
||||
# Block devices
|
||||
#
|
||||
# CONFIG_BLK_DEV_FD is not set
|
||||
# CONFIG_BLK_DEV_COW_COMMON is not set
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
# CONFIG_BLK_DEV_CRYPTOLOOP is not set
|
||||
# CONFIG_BLK_DEV_NBD is not set
|
||||
# CONFIG_BLK_DEV_RAM is not set
|
||||
# CONFIG_BLK_DEV_INITRD is not set
|
||||
# CONFIG_CDROM_PKTCDVD is not set
|
||||
# CONFIG_ATA_OVER_ETH is not set
|
||||
|
||||
#
|
||||
# Misc devices
|
||||
#
|
||||
# CONFIG_TIFM_CORE is not set
|
||||
|
||||
#
|
||||
# ATA/ATAPI/MFM/RLL support
|
||||
#
|
||||
# CONFIG_IDE is not set
|
||||
|
||||
#
|
||||
# SCSI device support
|
||||
#
|
||||
# CONFIG_RAID_ATTRS is not set
|
||||
# CONFIG_SCSI is not set
|
||||
# CONFIG_SCSI_NETLINK is not set
|
||||
|
||||
#
|
||||
# Serial ATA (prod) and Parallel ATA (experimental) drivers
|
||||
#
|
||||
# CONFIG_ATA is not set
|
||||
|
||||
#
|
||||
# Multi-device support (RAID and LVM)
|
||||
#
|
||||
# CONFIG_MD is not set
|
||||
|
||||
#
|
||||
# Fusion MPT device support
|
||||
#
|
||||
# CONFIG_FUSION is not set
|
||||
|
||||
#
|
||||
# IEEE 1394 (FireWire) support
|
||||
#
|
||||
|
||||
#
|
||||
# I2O device support
|
||||
#
|
||||
|
||||
#
|
||||
# Macintosh device drivers
|
||||
#
|
||||
# CONFIG_WINDFARM is not set
|
||||
|
||||
#
|
||||
# Network device support
|
||||
#
|
||||
CONFIG_NETDEVICES=y
|
||||
# CONFIG_DUMMY is not set
|
||||
# CONFIG_BONDING is not set
|
||||
# CONFIG_EQUALIZER is not set
|
||||
# CONFIG_TUN is not set
|
||||
|
||||
#
|
||||
# PHY device support
|
||||
#
|
||||
CONFIG_PHYLIB=y
|
||||
|
||||
#
|
||||
# MII PHY device drivers
|
||||
#
|
||||
# CONFIG_MARVELL_PHY is not set
|
||||
CONFIG_DAVICOM_PHY=y
|
||||
# CONFIG_QSEMI_PHY is not set
|
||||
# CONFIG_LXT_PHY is not set
|
||||
# CONFIG_CICADA_PHY is not set
|
||||
# CONFIG_VITESSE_PHY is not set
|
||||
# CONFIG_SMSC_PHY is not set
|
||||
CONFIG_FIXED_PHY=y
|
||||
CONFIG_FIXED_MII_10_FDX=y
|
||||
# CONFIG_FIXED_MII_100_FDX is not set
|
||||
|
||||
#
|
||||
# Ethernet (10 or 100Mbit)
|
||||
#
|
||||
CONFIG_NET_ETHERNET=y
|
||||
CONFIG_MII=y
|
||||
# CONFIG_FEC_8XX is not set
|
||||
CONFIG_FS_ENET=y
|
||||
CONFIG_FS_ENET_HAS_SCC=y
|
||||
CONFIG_FS_ENET_HAS_FEC=y
|
||||
|
||||
#
|
||||
# Ethernet (1000 Mbit)
|
||||
#
|
||||
|
||||
#
|
||||
# Ethernet (10000 Mbit)
|
||||
#
|
||||
|
||||
#
|
||||
# Token Ring devices
|
||||
#
|
||||
|
||||
#
|
||||
# Wireless LAN (non-hamradio)
|
||||
#
|
||||
# CONFIG_NET_RADIO is not set
|
||||
|
||||
#
|
||||
# Wan interfaces
|
||||
#
|
||||
# CONFIG_WAN is not set
|
||||
# CONFIG_PPP is not set
|
||||
# CONFIG_SLIP is not set
|
||||
# CONFIG_SHAPER is not set
|
||||
# CONFIG_NETCONSOLE is not set
|
||||
# CONFIG_NETPOLL is not set
|
||||
# CONFIG_NET_POLL_CONTROLLER is not set
|
||||
|
||||
#
|
||||
# ISDN subsystem
|
||||
#
|
||||
# CONFIG_ISDN is not set
|
||||
|
||||
#
|
||||
# Telephony Support
|
||||
#
|
||||
# CONFIG_PHONE is not set
|
||||
|
||||
#
|
||||
# Input device support
|
||||
#
|
||||
CONFIG_INPUT=y
|
||||
# CONFIG_INPUT_FF_MEMLESS is not set
|
||||
|
||||
#
|
||||
# Userland interfaces
|
||||
#
|
||||
CONFIG_INPUT_MOUSEDEV=y
|
||||
CONFIG_INPUT_MOUSEDEV_PSAUX=y
|
||||
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
|
||||
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
|
||||
# CONFIG_INPUT_JOYDEV is not set
|
||||
# CONFIG_INPUT_TSDEV is not set
|
||||
# CONFIG_INPUT_EVDEV is not set
|
||||
# CONFIG_INPUT_EVBUG is not set
|
||||
|
||||
#
|
||||
# Input Device Drivers
|
||||
#
|
||||
CONFIG_INPUT_KEYBOARD=y
|
||||
CONFIG_KEYBOARD_ATKBD=y
|
||||
# CONFIG_KEYBOARD_SUNKBD is not set
|
||||
# CONFIG_KEYBOARD_LKKBD is not set
|
||||
# CONFIG_KEYBOARD_XTKBD is not set
|
||||
# CONFIG_KEYBOARD_NEWTON is not set
|
||||
# CONFIG_KEYBOARD_STOWAWAY is not set
|
||||
CONFIG_INPUT_MOUSE=y
|
||||
CONFIG_MOUSE_PS2=y
|
||||
# CONFIG_MOUSE_SERIAL is not set
|
||||
# CONFIG_MOUSE_VSXXXAA is not set
|
||||
# CONFIG_INPUT_JOYSTICK is not set
|
||||
# CONFIG_INPUT_TOUCHSCREEN is not set
|
||||
# CONFIG_INPUT_MISC is not set
|
||||
|
||||
#
|
||||
# Hardware I/O ports
|
||||
#
|
||||
CONFIG_SERIO=y
|
||||
CONFIG_SERIO_I8042=y
|
||||
CONFIG_SERIO_SERPORT=y
|
||||
CONFIG_SERIO_LIBPS2=y
|
||||
# CONFIG_SERIO_RAW is not set
|
||||
# CONFIG_GAMEPORT is not set
|
||||
|
||||
#
|
||||
# Character devices
|
||||
#
|
||||
# CONFIG_VT is not set
|
||||
# CONFIG_SERIAL_NONSTANDARD is not set
|
||||
|
||||
#
|
||||
# Serial drivers
|
||||
#
|
||||
# CONFIG_SERIAL_8250 is not set
|
||||
|
||||
#
|
||||
# Non-8250 serial port support
|
||||
#
|
||||
CONFIG_SERIAL_CORE=y
|
||||
CONFIG_SERIAL_CORE_CONSOLE=y
|
||||
CONFIG_SERIAL_CPM=y
|
||||
CONFIG_SERIAL_CPM_CONSOLE=y
|
||||
# CONFIG_SERIAL_CPM_SCC1 is not set
|
||||
# CONFIG_SERIAL_CPM_SCC2 is not set
|
||||
# CONFIG_SERIAL_CPM_SCC3 is not set
|
||||
# CONFIG_SERIAL_CPM_SCC4 is not set
|
||||
CONFIG_SERIAL_CPM_SMC1=y
|
||||
CONFIG_SERIAL_CPM_SMC2=y
|
||||
CONFIG_UNIX98_PTYS=y
|
||||
# CONFIG_LEGACY_PTYS is not set
|
||||
|
||||
#
|
||||
# IPMI
|
||||
#
|
||||
# CONFIG_IPMI_HANDLER is not set
|
||||
|
||||
#
|
||||
# Watchdog Cards
|
||||
#
|
||||
# CONFIG_WATCHDOG is not set
|
||||
CONFIG_HW_RANDOM=y
|
||||
# CONFIG_NVRAM is not set
|
||||
CONFIG_GEN_RTC=y
|
||||
# CONFIG_GEN_RTC_X is not set
|
||||
# CONFIG_DTLK is not set
|
||||
# CONFIG_R3964 is not set
|
||||
|
||||
#
|
||||
# Ftape, the floppy tape device driver
|
||||
#
|
||||
# CONFIG_RAW_DRIVER is not set
|
||||
|
||||
#
|
||||
# TPM devices
|
||||
#
|
||||
# CONFIG_TCG_TPM is not set
|
||||
|
||||
#
|
||||
# I2C support
|
||||
#
|
||||
# CONFIG_I2C is not set
|
||||
|
||||
#
|
||||
# SPI support
|
||||
#
|
||||
# CONFIG_SPI is not set
|
||||
# CONFIG_SPI_MASTER is not set
|
||||
|
||||
#
|
||||
# Dallas's 1-wire bus
|
||||
#
|
||||
# CONFIG_W1 is not set
|
||||
|
||||
#
|
||||
# Hardware Monitoring support
|
||||
#
|
||||
CONFIG_HWMON=y
|
||||
# CONFIG_HWMON_VID is not set
|
||||
# CONFIG_SENSORS_ABITUGURU is not set
|
||||
# CONFIG_SENSORS_F71805F is not set
|
||||
# CONFIG_SENSORS_VT1211 is not set
|
||||
# CONFIG_HWMON_DEBUG_CHIP is not set
|
||||
|
||||
#
|
||||
# Multimedia devices
|
||||
#
|
||||
# CONFIG_VIDEO_DEV is not set
|
||||
|
||||
#
|
||||
# Digital Video Broadcasting Devices
|
||||
#
|
||||
# CONFIG_DVB is not set
|
||||
|
||||
#
|
||||
# Graphics support
|
||||
#
|
||||
CONFIG_FIRMWARE_EDID=y
|
||||
# CONFIG_FB is not set
|
||||
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
|
||||
|
||||
#
|
||||
# Sound
|
||||
#
|
||||
# CONFIG_SOUND is not set
|
||||
|
||||
#
|
||||
# USB support
|
||||
#
|
||||
# CONFIG_USB_ARCH_HAS_HCD is not set
|
||||
# CONFIG_USB_ARCH_HAS_OHCI is not set
|
||||
# CONFIG_USB_ARCH_HAS_EHCI is not set
|
||||
|
||||
#
|
||||
# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
|
||||
#
|
||||
|
||||
#
|
||||
# USB Gadget Support
|
||||
#
|
||||
# CONFIG_USB_GADGET is not set
|
||||
|
||||
#
|
||||
# MMC/SD Card support
|
||||
#
|
||||
# CONFIG_MMC is not set
|
||||
|
||||
#
|
||||
# LED devices
|
||||
#
|
||||
# CONFIG_NEW_LEDS is not set
|
||||
|
||||
#
|
||||
# LED drivers
|
||||
#
|
||||
|
||||
#
|
||||
# LED Triggers
|
||||
#
|
||||
|
||||
#
|
||||
# InfiniBand support
|
||||
#
|
||||
|
||||
#
|
||||
# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
|
||||
#
|
||||
|
||||
#
|
||||
# Real Time Clock
|
||||
#
|
||||
# CONFIG_RTC_CLASS is not set
|
||||
|
||||
#
|
||||
# DMA Engine support
|
||||
#
|
||||
# CONFIG_DMA_ENGINE is not set
|
||||
|
||||
#
|
||||
# DMA Clients
|
||||
#
|
||||
|
||||
#
|
||||
# DMA Devices
|
||||
#
|
||||
|
||||
#
|
||||
# File systems
|
||||
#
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT2_FS_XATTR=y
|
||||
# CONFIG_EXT2_FS_POSIX_ACL is not set
|
||||
# CONFIG_EXT2_FS_SECURITY is not set
|
||||
# CONFIG_EXT2_FS_XIP is not set
|
||||
CONFIG_EXT3_FS=y
|
||||
CONFIG_EXT3_FS_XATTR=y
|
||||
# CONFIG_EXT3_FS_POSIX_ACL is not set
|
||||
# CONFIG_EXT3_FS_SECURITY is not set
|
||||
# CONFIG_EXT4DEV_FS is not set
|
||||
CONFIG_JBD=y
|
||||
# CONFIG_JBD_DEBUG is not set
|
||||
CONFIG_FS_MBCACHE=y
|
||||
# CONFIG_REISERFS_FS is not set
|
||||
# CONFIG_JFS_FS is not set
|
||||
# CONFIG_FS_POSIX_ACL is not set
|
||||
# CONFIG_XFS_FS is not set
|
||||
# CONFIG_GFS2_FS is not set
|
||||
# CONFIG_OCFS2_FS is not set
|
||||
# CONFIG_MINIX_FS is not set
|
||||
# CONFIG_ROMFS_FS is not set
|
||||
CONFIG_INOTIFY=y
|
||||
CONFIG_INOTIFY_USER=y
|
||||
# CONFIG_QUOTA is not set
|
||||
CONFIG_DNOTIFY=y
|
||||
# CONFIG_AUTOFS_FS is not set
|
||||
# CONFIG_AUTOFS4_FS is not set
|
||||
# CONFIG_FUSE_FS is not set
|
||||
|
||||
#
|
||||
# CD-ROM/DVD Filesystems
|
||||
#
|
||||
# CONFIG_ISO9660_FS is not set
|
||||
# CONFIG_UDF_FS is not set
|
||||
|
||||
#
|
||||
# DOS/FAT/NT Filesystems
|
||||
#
|
||||
# CONFIG_MSDOS_FS is not set
|
||||
# CONFIG_VFAT_FS is not set
|
||||
# CONFIG_NTFS_FS is not set
|
||||
|
||||
#
|
||||
# Pseudo filesystems
|
||||
#
|
||||
CONFIG_PROC_FS=y
|
||||
# CONFIG_PROC_KCORE is not set
|
||||
CONFIG_PROC_SYSCTL=y
|
||||
CONFIG_SYSFS=y
|
||||
CONFIG_TMPFS=y
|
||||
# CONFIG_TMPFS_POSIX_ACL is not set
|
||||
# CONFIG_HUGETLB_PAGE is not set
|
||||
CONFIG_RAMFS=y
|
||||
# CONFIG_CONFIGFS_FS is not set
|
||||
|
||||
#
|
||||
# Miscellaneous filesystems
|
||||
#
|
||||
# CONFIG_ADFS_FS is not set
|
||||
# CONFIG_AFFS_FS is not set
|
||||
# CONFIG_HFS_FS is not set
|
||||
# CONFIG_HFSPLUS_FS is not set
|
||||
# CONFIG_BEFS_FS is not set
|
||||
# CONFIG_BFS_FS is not set
|
||||
# CONFIG_EFS_FS is not set
|
||||
CONFIG_CRAMFS=y
|
||||
# CONFIG_VXFS_FS is not set
|
||||
# CONFIG_HPFS_FS is not set
|
||||
# CONFIG_QNX4FS_FS is not set
|
||||
# CONFIG_SYSV_FS is not set
|
||||
# CONFIG_UFS_FS is not set
|
||||
|
||||
#
|
||||
# Network File Systems
|
||||
#
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V3=y
|
||||
# CONFIG_NFS_V3_ACL is not set
|
||||
# CONFIG_NFS_V4 is not set
|
||||
# CONFIG_NFS_DIRECTIO is not set
|
||||
# CONFIG_NFSD is not set
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_LOCKD=y
|
||||
CONFIG_LOCKD_V4=y
|
||||
CONFIG_NFS_COMMON=y
|
||||
CONFIG_SUNRPC=y
|
||||
# CONFIG_RPCSEC_GSS_KRB5 is not set
|
||||
# CONFIG_RPCSEC_GSS_SPKM3 is not set
|
||||
# CONFIG_SMB_FS is not set
|
||||
# CONFIG_CIFS is not set
|
||||
# CONFIG_NCP_FS is not set
|
||||
# CONFIG_CODA_FS is not set
|
||||
# CONFIG_AFS_FS is not set
|
||||
# CONFIG_9P_FS is not set
|
||||
|
||||
#
|
||||
# Partition Types
|
||||
#
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
# CONFIG_ACORN_PARTITION is not set
|
||||
# CONFIG_OSF_PARTITION is not set
|
||||
# CONFIG_AMIGA_PARTITION is not set
|
||||
# CONFIG_ATARI_PARTITION is not set
|
||||
# CONFIG_MAC_PARTITION is not set
|
||||
CONFIG_MSDOS_PARTITION=y
|
||||
# CONFIG_BSD_DISKLABEL is not set
|
||||
# CONFIG_MINIX_SUBPARTITION is not set
|
||||
# CONFIG_SOLARIS_X86_PARTITION is not set
|
||||
# CONFIG_UNIXWARE_DISKLABEL is not set
|
||||
# CONFIG_LDM_PARTITION is not set
|
||||
# CONFIG_SGI_PARTITION is not set
|
||||
# CONFIG_ULTRIX_PARTITION is not set
|
||||
# CONFIG_SUN_PARTITION is not set
|
||||
# CONFIG_KARMA_PARTITION is not set
|
||||
# CONFIG_EFI_PARTITION is not set
|
||||
|
||||
#
|
||||
# Native Language Support
|
||||
#
|
||||
# CONFIG_NLS is not set
|
||||
|
||||
#
|
||||
# Library routines
|
||||
#
|
||||
CONFIG_CRC_CCITT=y
|
||||
# CONFIG_CRC16 is not set
|
||||
CONFIG_CRC32=y
|
||||
# CONFIG_LIBCRC32C is not set
|
||||
CONFIG_ZLIB_INFLATE=y
|
||||
CONFIG_PLIST=y
|
||||
|
||||
#
|
||||
# Instrumentation Support
|
||||
#
|
||||
# CONFIG_PROFILING is not set
|
||||
|
||||
#
|
||||
# Kernel hacking
|
||||
#
|
||||
# CONFIG_PRINTK_TIME is not set
|
||||
CONFIG_ENABLE_MUST_CHECK=y
|
||||
# CONFIG_MAGIC_SYSRQ is not set
|
||||
# CONFIG_UNUSED_SYMBOLS is not set
|
||||
# CONFIG_DEBUG_KERNEL is not set
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
# CONFIG_DEBUG_FS is not set
|
||||
# CONFIG_UNWIND_INFO is not set
|
||||
# CONFIG_HEADERS_CHECK is not set
|
||||
# CONFIG_BOOTX_TEXT is not set
|
||||
# CONFIG_PPC_EARLY_DEBUG is not set
|
||||
|
||||
#
|
||||
# Security options
|
||||
#
|
||||
# CONFIG_KEYS is not set
|
||||
# CONFIG_SECURITY is not set
|
||||
|
||||
#
|
||||
# Cryptographic options
|
||||
#
|
||||
# CONFIG_CRYPTO is not set
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,7 +1,7 @@
|
|||
#
|
||||
# Automatically generated make config: don't edit
|
||||
# Linux kernel version: 2.6.20-rc5
|
||||
# Mon Jan 22 22:29:11 2007
|
||||
# Linux kernel version: 2.6.20-rc6
|
||||
# Thu Jan 25 13:35:34 2007
|
||||
#
|
||||
CONFIG_PPC64=y
|
||||
CONFIG_64BIT=y
|
||||
|
|
@ -70,10 +70,10 @@ CONFIG_SYSVIPC=y
|
|||
CONFIG_SYSFS_DEPRECATED=y
|
||||
# CONFIG_RELAY is not set
|
||||
CONFIG_INITRAMFS_SOURCE=""
|
||||
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
|
||||
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
|
||||
CONFIG_SYSCTL=y
|
||||
CONFIG_EMBEDDED=y
|
||||
# CONFIG_SYSCTL_SYSCALL is not set
|
||||
# CONFIG_EMBEDDED is not set
|
||||
CONFIG_SYSCTL_SYSCALL=y
|
||||
CONFIG_KALLSYMS=y
|
||||
CONFIG_KALLSYMS_ALL=y
|
||||
CONFIG_KALLSYMS_EXTRA_PASS=y
|
||||
|
|
@ -160,7 +160,7 @@ CONFIG_SPU_BASE=y
|
|||
# PS3 Platform Options
|
||||
#
|
||||
CONFIG_PS3_HTAB_SIZE=20
|
||||
CONFIG_PS3_DYNAMIC_DMA=y
|
||||
# CONFIG_PS3_DYNAMIC_DMA is not set
|
||||
CONFIG_PS3_USE_LPAR_ADDR=y
|
||||
CONFIG_PS3_VUART=y
|
||||
|
||||
|
|
@ -207,7 +207,7 @@ CONFIG_PPC_64K_PAGES=y
|
|||
# CONFIG_SCHED_SMT is not set
|
||||
CONFIG_PROC_DEVICETREE=y
|
||||
CONFIG_CMDLINE_BOOL=y
|
||||
CONFIG_CMDLINE="root=/dev/nfs rw ip=dhcp"
|
||||
CONFIG_CMDLINE="root=/dev/sda1 ip=dhcp"
|
||||
# CONFIG_PM is not set
|
||||
# CONFIG_SECCOMP is not set
|
||||
CONFIG_ISA_DMA_API=y
|
||||
|
|
@ -240,7 +240,8 @@ CONFIG_NET=y
|
|||
# Networking options
|
||||
#
|
||||
# CONFIG_NETDEBUG is not set
|
||||
# CONFIG_PACKET is not set
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_PACKET_MMAP=y
|
||||
CONFIG_UNIX=y
|
||||
# CONFIG_NET_KEY is not set
|
||||
CONFIG_INET=y
|
||||
|
|
@ -353,6 +354,7 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
|
|||
# CONFIG_BLK_DEV_COW_COMMON is not set
|
||||
# CONFIG_BLK_DEV_LOOP is not set
|
||||
# CONFIG_BLK_DEV_NBD is not set
|
||||
# CONFIG_BLK_DEV_UB is not set
|
||||
# CONFIG_BLK_DEV_RAM is not set
|
||||
# CONFIG_BLK_DEV_INITRD is not set
|
||||
# CONFIG_CDROM_PKTCDVD is not set
|
||||
|
|
@ -380,10 +382,11 @@ CONFIG_SCSI_PROC_FS=y
|
|||
#
|
||||
# SCSI support type (disk, tape, CD-ROM)
|
||||
#
|
||||
# CONFIG_BLK_DEV_SD is not set
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
# CONFIG_CHR_DEV_ST is not set
|
||||
# CONFIG_CHR_DEV_OSST is not set
|
||||
# CONFIG_BLK_DEV_SR is not set
|
||||
CONFIG_BLK_DEV_SR=y
|
||||
# CONFIG_BLK_DEV_SR_VENDOR is not set
|
||||
# CONFIG_CHR_DEV_SG is not set
|
||||
# CONFIG_CHR_DEV_SCH is not set
|
||||
|
||||
|
|
@ -456,6 +459,7 @@ CONFIG_NETDEVICES=y
|
|||
# Ethernet (10 or 100Mbit)
|
||||
#
|
||||
# CONFIG_NET_ETHERNET is not set
|
||||
CONFIG_MII=y
|
||||
|
||||
#
|
||||
# Ethernet (1000 Mbit)
|
||||
|
|
@ -504,10 +508,13 @@ CONFIG_INPUT=y
|
|||
#
|
||||
# Userland interfaces
|
||||
#
|
||||
# CONFIG_INPUT_MOUSEDEV is not set
|
||||
CONFIG_INPUT_MOUSEDEV=y
|
||||
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
|
||||
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
|
||||
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
|
||||
# CONFIG_INPUT_JOYDEV is not set
|
||||
# CONFIG_INPUT_TSDEV is not set
|
||||
CONFIG_INPUT_EVDEV=y
|
||||
# CONFIG_INPUT_EVDEV is not set
|
||||
# CONFIG_INPUT_EVBUG is not set
|
||||
|
||||
#
|
||||
|
|
@ -598,6 +605,7 @@ CONFIG_GEN_RTC=y
|
|||
# Digital Video Broadcasting Devices
|
||||
#
|
||||
# CONFIG_DVB is not set
|
||||
# CONFIG_USB_DABUSB is not set
|
||||
|
||||
#
|
||||
# Graphics support
|
||||
|
|
@ -626,14 +634,141 @@ CONFIG_HID=y
|
|||
#
|
||||
# USB support
|
||||
#
|
||||
# CONFIG_USB_ARCH_HAS_HCD is not set
|
||||
# CONFIG_USB_ARCH_HAS_OHCI is not set
|
||||
# CONFIG_USB_ARCH_HAS_EHCI is not set
|
||||
CONFIG_USB_ARCH_HAS_HCD=y
|
||||
CONFIG_USB_ARCH_HAS_OHCI=y
|
||||
CONFIG_USB_ARCH_HAS_EHCI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_DEBUG=y
|
||||
|
||||
#
|
||||
# Miscellaneous USB options
|
||||
#
|
||||
# CONFIG_USB_DEVICEFS is not set
|
||||
# CONFIG_USB_BANDWIDTH is not set
|
||||
# CONFIG_USB_DYNAMIC_MINORS is not set
|
||||
# CONFIG_USB_OTG is not set
|
||||
|
||||
#
|
||||
# USB Host Controller Drivers
|
||||
#
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
# CONFIG_USB_EHCI_SPLIT_ISO is not set
|
||||
# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
|
||||
# CONFIG_USB_EHCI_TT_NEWSCHED is not set
|
||||
CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y
|
||||
# CONFIG_USB_ISP116X_HCD is not set
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
# CONFIG_USB_OHCI_HCD_PPC_OF is not set
|
||||
# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
|
||||
CONFIG_USB_OHCI_BIG_ENDIAN_MMIO=y
|
||||
CONFIG_USB_OHCI_LITTLE_ENDIAN=y
|
||||
# CONFIG_USB_SL811_HCD is not set
|
||||
|
||||
#
|
||||
# USB Device Class drivers
|
||||
#
|
||||
# CONFIG_USB_ACM is not set
|
||||
# CONFIG_USB_PRINTER is not set
|
||||
|
||||
#
|
||||
# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
|
||||
#
|
||||
|
||||
#
|
||||
# may also be needed; see USB_STORAGE Help for more information
|
||||
#
|
||||
CONFIG_USB_STORAGE=y
|
||||
# CONFIG_USB_STORAGE_DEBUG is not set
|
||||
# CONFIG_USB_STORAGE_DATAFAB is not set
|
||||
# CONFIG_USB_STORAGE_FREECOM is not set
|
||||
# CONFIG_USB_STORAGE_DPCM is not set
|
||||
# CONFIG_USB_STORAGE_USBAT is not set
|
||||
# CONFIG_USB_STORAGE_SDDR09 is not set
|
||||
# CONFIG_USB_STORAGE_SDDR55 is not set
|
||||
# CONFIG_USB_STORAGE_JUMPSHOT is not set
|
||||
# CONFIG_USB_STORAGE_ALAUDA is not set
|
||||
# CONFIG_USB_STORAGE_KARMA is not set
|
||||
# CONFIG_USB_LIBUSUAL is not set
|
||||
|
||||
#
|
||||
# USB Input Devices
|
||||
#
|
||||
CONFIG_USB_HID=y
|
||||
# CONFIG_USB_HIDINPUT_POWERBOOK is not set
|
||||
# CONFIG_HID_FF is not set
|
||||
# CONFIG_USB_HIDDEV is not set
|
||||
# CONFIG_USB_AIPTEK is not set
|
||||
# CONFIG_USB_WACOM is not set
|
||||
# CONFIG_USB_ACECAD is not set
|
||||
# CONFIG_USB_KBTAB is not set
|
||||
# CONFIG_USB_POWERMATE is not set
|
||||
# CONFIG_USB_TOUCHSCREEN is not set
|
||||
# CONFIG_USB_YEALINK is not set
|
||||
# CONFIG_USB_XPAD is not set
|
||||
# CONFIG_USB_ATI_REMOTE is not set
|
||||
# CONFIG_USB_ATI_REMOTE2 is not set
|
||||
# CONFIG_USB_KEYSPAN_REMOTE is not set
|
||||
# CONFIG_USB_APPLETOUCH is not set
|
||||
|
||||
#
|
||||
# USB Imaging devices
|
||||
#
|
||||
# CONFIG_USB_MDC800 is not set
|
||||
# CONFIG_USB_MICROTEK is not set
|
||||
|
||||
#
|
||||
# USB Network Adapters
|
||||
#
|
||||
# CONFIG_USB_CATC is not set
|
||||
# CONFIG_USB_KAWETH is not set
|
||||
# CONFIG_USB_PEGASUS is not set
|
||||
# CONFIG_USB_RTL8150 is not set
|
||||
CONFIG_USB_USBNET_MII=y
|
||||
CONFIG_USB_USBNET=y
|
||||
CONFIG_USB_NET_CDCETHER=y
|
||||
# CONFIG_USB_NET_GL620A is not set
|
||||
# CONFIG_USB_NET_NET1080 is not set
|
||||
# CONFIG_USB_NET_PLUSB is not set
|
||||
CONFIG_USB_NET_MCS7830=y
|
||||
# CONFIG_USB_NET_RNDIS_HOST is not set
|
||||
# CONFIG_USB_NET_CDC_SUBSET is not set
|
||||
# CONFIG_USB_NET_ZAURUS is not set
|
||||
CONFIG_USB_MON=y
|
||||
|
||||
#
|
||||
# USB port drivers
|
||||
#
|
||||
|
||||
#
|
||||
# USB Serial Converter support
|
||||
#
|
||||
# CONFIG_USB_SERIAL is not set
|
||||
|
||||
#
|
||||
# USB Miscellaneous drivers
|
||||
#
|
||||
# CONFIG_USB_EMI62 is not set
|
||||
# CONFIG_USB_EMI26 is not set
|
||||
# CONFIG_USB_ADUTUX is not set
|
||||
# CONFIG_USB_AUERSWALD is not set
|
||||
# CONFIG_USB_RIO500 is not set
|
||||
# CONFIG_USB_LEGOTOWER is not set
|
||||
# CONFIG_USB_LCD is not set
|
||||
# CONFIG_USB_LED is not set
|
||||
# CONFIG_USB_CYPRESS_CY7C63 is not set
|
||||
# CONFIG_USB_CYTHERM is not set
|
||||
# CONFIG_USB_PHIDGET is not set
|
||||
# CONFIG_USB_IDMOUSE is not set
|
||||
# CONFIG_USB_FTDI_ELAN is not set
|
||||
# CONFIG_USB_APPLEDISPLAY is not set
|
||||
# CONFIG_USB_SISUSBVGA is not set
|
||||
# CONFIG_USB_LD is not set
|
||||
# CONFIG_USB_TRANCEVIBRATOR is not set
|
||||
|
||||
#
|
||||
# USB DSL modem support
|
||||
#
|
||||
|
||||
#
|
||||
# USB Gadget Support
|
||||
#
|
||||
|
|
@ -691,8 +826,14 @@ CONFIG_HID=y
|
|||
# File systems
|
||||
#
|
||||
# CONFIG_EXT2_FS is not set
|
||||
# CONFIG_EXT3_FS is not set
|
||||
CONFIG_EXT3_FS=y
|
||||
CONFIG_EXT3_FS_XATTR=y
|
||||
# CONFIG_EXT3_FS_POSIX_ACL is not set
|
||||
# CONFIG_EXT3_FS_SECURITY is not set
|
||||
# CONFIG_EXT4DEV_FS is not set
|
||||
CONFIG_JBD=y
|
||||
# CONFIG_JBD_DEBUG is not set
|
||||
CONFIG_FS_MBCACHE=y
|
||||
# CONFIG_REISERFS_FS is not set
|
||||
# CONFIG_JFS_FS is not set
|
||||
# CONFIG_FS_POSIX_ACL is not set
|
||||
|
|
@ -712,14 +853,20 @@ CONFIG_DNOTIFY=y
|
|||
#
|
||||
# CD-ROM/DVD Filesystems
|
||||
#
|
||||
# CONFIG_ISO9660_FS is not set
|
||||
# CONFIG_UDF_FS is not set
|
||||
CONFIG_ISO9660_FS=y
|
||||
CONFIG_JOLIET=y
|
||||
# CONFIG_ZISOFS is not set
|
||||
CONFIG_UDF_FS=y
|
||||
CONFIG_UDF_NLS=y
|
||||
|
||||
#
|
||||
# DOS/FAT/NT Filesystems
|
||||
#
|
||||
CONFIG_FAT_FS=y
|
||||
# CONFIG_MSDOS_FS is not set
|
||||
# CONFIG_VFAT_FS is not set
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_FAT_DEFAULT_CODEPAGE=437
|
||||
CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
|
||||
# CONFIG_NTFS_FS is not set
|
||||
|
||||
#
|
||||
|
|
@ -785,7 +932,46 @@ CONFIG_MSDOS_PARTITION=y
|
|||
#
|
||||
# Native Language Support
|
||||
#
|
||||
# CONFIG_NLS is not set
|
||||
CONFIG_NLS=y
|
||||
CONFIG_NLS_DEFAULT="iso8859-1"
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
# CONFIG_NLS_CODEPAGE_737 is not set
|
||||
# CONFIG_NLS_CODEPAGE_775 is not set
|
||||
# CONFIG_NLS_CODEPAGE_850 is not set
|
||||
# CONFIG_NLS_CODEPAGE_852 is not set
|
||||
# CONFIG_NLS_CODEPAGE_855 is not set
|
||||
# CONFIG_NLS_CODEPAGE_857 is not set
|
||||
# CONFIG_NLS_CODEPAGE_860 is not set
|
||||
# CONFIG_NLS_CODEPAGE_861 is not set
|
||||
# CONFIG_NLS_CODEPAGE_862 is not set
|
||||
# CONFIG_NLS_CODEPAGE_863 is not set
|
||||
# CONFIG_NLS_CODEPAGE_864 is not set
|
||||
# CONFIG_NLS_CODEPAGE_865 is not set
|
||||
# CONFIG_NLS_CODEPAGE_866 is not set
|
||||
# CONFIG_NLS_CODEPAGE_869 is not set
|
||||
# CONFIG_NLS_CODEPAGE_936 is not set
|
||||
# CONFIG_NLS_CODEPAGE_950 is not set
|
||||
# CONFIG_NLS_CODEPAGE_932 is not set
|
||||
# CONFIG_NLS_CODEPAGE_949 is not set
|
||||
# CONFIG_NLS_CODEPAGE_874 is not set
|
||||
# CONFIG_NLS_ISO8859_8 is not set
|
||||
# CONFIG_NLS_CODEPAGE_1250 is not set
|
||||
# CONFIG_NLS_CODEPAGE_1251 is not set
|
||||
# CONFIG_NLS_ASCII is not set
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
# CONFIG_NLS_ISO8859_2 is not set
|
||||
# CONFIG_NLS_ISO8859_3 is not set
|
||||
# CONFIG_NLS_ISO8859_4 is not set
|
||||
# CONFIG_NLS_ISO8859_5 is not set
|
||||
# CONFIG_NLS_ISO8859_6 is not set
|
||||
# CONFIG_NLS_ISO8859_7 is not set
|
||||
# CONFIG_NLS_ISO8859_9 is not set
|
||||
# CONFIG_NLS_ISO8859_13 is not set
|
||||
# CONFIG_NLS_ISO8859_14 is not set
|
||||
# CONFIG_NLS_ISO8859_15 is not set
|
||||
# CONFIG_NLS_KOI8_R is not set
|
||||
# CONFIG_NLS_KOI8_U is not set
|
||||
# CONFIG_NLS_UTF8 is not set
|
||||
|
||||
#
|
||||
# Distributed Lock Manager
|
||||
|
|
@ -795,9 +981,10 @@ CONFIG_MSDOS_PARTITION=y
|
|||
#
|
||||
# Library routines
|
||||
#
|
||||
CONFIG_BITREVERSE=y
|
||||
# CONFIG_CRC_CCITT is not set
|
||||
# CONFIG_CRC16 is not set
|
||||
# CONFIG_CRC32 is not set
|
||||
CONFIG_CRC32=y
|
||||
# CONFIG_LIBCRC32C is not set
|
||||
CONFIG_PLIST=y
|
||||
CONFIG_IOMAP_COPY=y
|
||||
|
|
@ -821,22 +1008,23 @@ CONFIG_DEBUG_KERNEL=y
|
|||
CONFIG_LOG_BUF_SHIFT=17
|
||||
CONFIG_DETECT_SOFTLOCKUP=y
|
||||
# CONFIG_SCHEDSTATS is not set
|
||||
# CONFIG_DEBUG_SLAB is not set
|
||||
CONFIG_DEBUG_SLAB=y
|
||||
# CONFIG_DEBUG_SLAB_LEAK is not set
|
||||
# CONFIG_DEBUG_RT_MUTEXES is not set
|
||||
# CONFIG_RT_MUTEX_TESTER is not set
|
||||
CONFIG_DEBUG_SPINLOCK=y
|
||||
# CONFIG_DEBUG_MUTEXES is not set
|
||||
# CONFIG_DEBUG_RWSEMS is not set
|
||||
CONFIG_DEBUG_MUTEXES=y
|
||||
CONFIG_DEBUG_RWSEMS=y
|
||||
CONFIG_DEBUG_SPINLOCK_SLEEP=y
|
||||
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
|
||||
# CONFIG_DEBUG_KOBJECT is not set
|
||||
# CONFIG_DEBUG_BUGVERBOSE is not set
|
||||
CONFIG_DEBUG_BUGVERBOSE=y
|
||||
CONFIG_DEBUG_INFO=y
|
||||
# CONFIG_DEBUG_VM is not set
|
||||
CONFIG_DEBUG_LIST=y
|
||||
CONFIG_FORCED_INLINING=y
|
||||
# CONFIG_RCU_TORTURE_TEST is not set
|
||||
# CONFIG_DEBUG_STACKOVERFLOW is not set
|
||||
CONFIG_DEBUG_STACKOVERFLOW=y
|
||||
# CONFIG_DEBUG_STACK_USAGE is not set
|
||||
# CONFIG_DEBUGGER is not set
|
||||
CONFIG_IRQSTACKS=y
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@ obj-y += vdso32/
|
|||
obj-$(CONFIG_PPC64) += setup_64.o binfmt_elf32.o sys_ppc32.o \
|
||||
signal_64.o ptrace32.o \
|
||||
paca.o cpu_setup_ppc970.o \
|
||||
cpu_setup_pa6t.o \
|
||||
firmware.o sysfs.o nvram_64.o
|
||||
obj-$(CONFIG_PPC64) += vdso64/
|
||||
obj-$(CONFIG_ALTIVEC) += vecemu.o vector.o
|
||||
|
|
|
|||
|
|
@ -0,0 +1,44 @@
|
|||
/*
|
||||
* Copyright (C) 2006-2007 PA Semi, Inc
|
||||
*
|
||||
* Maintained by: Olof Johansson <olof@lixom.net>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
#include <asm/processor.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/cputable.h>
|
||||
#include <asm/ppc_asm.h>
|
||||
#include <asm/asm-offsets.h>
|
||||
#include <asm/cache.h>
|
||||
|
||||
/* Right now, restore and setup are the same thing */
|
||||
_GLOBAL(__restore_cpu_pa6t)
|
||||
_GLOBAL(__setup_cpu_pa6t)
|
||||
/* Do nothing if not running in HV mode */
|
||||
mfmsr r0
|
||||
rldicl. r0,r0,4,63
|
||||
beqlr
|
||||
|
||||
mfspr r0,SPRN_HID5
|
||||
ori r0,r0,0x30
|
||||
mtspr SPRN_HID5,r0
|
||||
|
||||
mfspr r0,SPRN_LPCR
|
||||
ori r0,r0,0x7000
|
||||
mtspr SPRN_LPCR,r0
|
||||
|
||||
blr
|
||||
|
|
@ -43,6 +43,8 @@ extern void __setup_cpu_745x(unsigned long offset, struct cpu_spec* spec);
|
|||
#ifdef CONFIG_PPC64
|
||||
extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec);
|
||||
extern void __setup_cpu_ppc970MP(unsigned long offset, struct cpu_spec* spec);
|
||||
extern void __setup_cpu_pa6t(unsigned long offset, struct cpu_spec* spec);
|
||||
extern void __restore_cpu_pa6t(unsigned long offset, struct cpu_spec* spec);
|
||||
extern void __restore_cpu_ppc970(void);
|
||||
#endif /* CONFIG_PPC64 */
|
||||
|
||||
|
|
@ -86,6 +88,7 @@ static struct cpu_spec cpu_specs[] = {
|
|||
.icache_bsize = 128,
|
||||
.dcache_bsize = 128,
|
||||
.num_pmcs = 8,
|
||||
.pmc_type = PPC_PMC_IBM,
|
||||
.oprofile_cpu_type = "ppc64/power3",
|
||||
.oprofile_type = PPC_OPROFILE_RS64,
|
||||
.platform = "power3",
|
||||
|
|
@ -99,6 +102,7 @@ static struct cpu_spec cpu_specs[] = {
|
|||
.icache_bsize = 128,
|
||||
.dcache_bsize = 128,
|
||||
.num_pmcs = 8,
|
||||
.pmc_type = PPC_PMC_IBM,
|
||||
.oprofile_cpu_type = "ppc64/power3",
|
||||
.oprofile_type = PPC_OPROFILE_RS64,
|
||||
.platform = "power3",
|
||||
|
|
@ -112,6 +116,7 @@ static struct cpu_spec cpu_specs[] = {
|
|||
.icache_bsize = 128,
|
||||
.dcache_bsize = 128,
|
||||
.num_pmcs = 8,
|
||||
.pmc_type = PPC_PMC_IBM,
|
||||
.oprofile_cpu_type = "ppc64/rs64",
|
||||
.oprofile_type = PPC_OPROFILE_RS64,
|
||||
.platform = "rs64",
|
||||
|
|
@ -125,6 +130,7 @@ static struct cpu_spec cpu_specs[] = {
|
|||
.icache_bsize = 128,
|
||||
.dcache_bsize = 128,
|
||||
.num_pmcs = 8,
|
||||
.pmc_type = PPC_PMC_IBM,
|
||||
.oprofile_cpu_type = "ppc64/rs64",
|
||||
.oprofile_type = PPC_OPROFILE_RS64,
|
||||
.platform = "rs64",
|
||||
|
|
@ -138,6 +144,7 @@ static struct cpu_spec cpu_specs[] = {
|
|||
.icache_bsize = 128,
|
||||
.dcache_bsize = 128,
|
||||
.num_pmcs = 8,
|
||||
.pmc_type = PPC_PMC_IBM,
|
||||
.oprofile_cpu_type = "ppc64/rs64",
|
||||
.oprofile_type = PPC_OPROFILE_RS64,
|
||||
.platform = "rs64",
|
||||
|
|
@ -151,6 +158,7 @@ static struct cpu_spec cpu_specs[] = {
|
|||
.icache_bsize = 128,
|
||||
.dcache_bsize = 128,
|
||||
.num_pmcs = 8,
|
||||
.pmc_type = PPC_PMC_IBM,
|
||||
.oprofile_cpu_type = "ppc64/rs64",
|
||||
.oprofile_type = PPC_OPROFILE_RS64,
|
||||
.platform = "rs64",
|
||||
|
|
@ -164,6 +172,7 @@ static struct cpu_spec cpu_specs[] = {
|
|||
.icache_bsize = 128,
|
||||
.dcache_bsize = 128,
|
||||
.num_pmcs = 8,
|
||||
.pmc_type = PPC_PMC_IBM,
|
||||
.oprofile_cpu_type = "ppc64/power4",
|
||||
.oprofile_type = PPC_OPROFILE_POWER4,
|
||||
.platform = "power4",
|
||||
|
|
@ -177,6 +186,7 @@ static struct cpu_spec cpu_specs[] = {
|
|||
.icache_bsize = 128,
|
||||
.dcache_bsize = 128,
|
||||
.num_pmcs = 8,
|
||||
.pmc_type = PPC_PMC_IBM,
|
||||
.oprofile_cpu_type = "ppc64/power4",
|
||||
.oprofile_type = PPC_OPROFILE_POWER4,
|
||||
.platform = "power4",
|
||||
|
|
@ -191,6 +201,7 @@ static struct cpu_spec cpu_specs[] = {
|
|||
.icache_bsize = 128,
|
||||
.dcache_bsize = 128,
|
||||
.num_pmcs = 8,
|
||||
.pmc_type = PPC_PMC_IBM,
|
||||
.cpu_setup = __setup_cpu_ppc970,
|
||||
.cpu_restore = __restore_cpu_ppc970,
|
||||
.oprofile_cpu_type = "ppc64/970",
|
||||
|
|
@ -207,6 +218,7 @@ static struct cpu_spec cpu_specs[] = {
|
|||
.icache_bsize = 128,
|
||||
.dcache_bsize = 128,
|
||||
.num_pmcs = 8,
|
||||
.pmc_type = PPC_PMC_IBM,
|
||||
.cpu_setup = __setup_cpu_ppc970,
|
||||
.cpu_restore = __restore_cpu_ppc970,
|
||||
.oprofile_cpu_type = "ppc64/970",
|
||||
|
|
@ -239,6 +251,7 @@ static struct cpu_spec cpu_specs[] = {
|
|||
.icache_bsize = 128,
|
||||
.dcache_bsize = 128,
|
||||
.num_pmcs = 8,
|
||||
.pmc_type = PPC_PMC_IBM,
|
||||
.cpu_setup = __setup_cpu_ppc970,
|
||||
.oprofile_cpu_type = "ppc64/970",
|
||||
.oprofile_type = PPC_OPROFILE_POWER4,
|
||||
|
|
@ -253,6 +266,7 @@ static struct cpu_spec cpu_specs[] = {
|
|||
.icache_bsize = 128,
|
||||
.dcache_bsize = 128,
|
||||
.num_pmcs = 6,
|
||||
.pmc_type = PPC_PMC_IBM,
|
||||
.oprofile_cpu_type = "ppc64/power5",
|
||||
.oprofile_type = PPC_OPROFILE_POWER4,
|
||||
/* SIHV / SIPR bits are implemented on POWER4+ (GQ)
|
||||
|
|
@ -271,6 +285,7 @@ static struct cpu_spec cpu_specs[] = {
|
|||
.icache_bsize = 128,
|
||||
.dcache_bsize = 128,
|
||||
.num_pmcs = 6,
|
||||
.pmc_type = PPC_PMC_IBM,
|
||||
.oprofile_cpu_type = "ppc64/power5+",
|
||||
.oprofile_type = PPC_OPROFILE_POWER4,
|
||||
.oprofile_mmcra_sihv = MMCRA_SIHV,
|
||||
|
|
@ -321,6 +336,7 @@ static struct cpu_spec cpu_specs[] = {
|
|||
.icache_bsize = 128,
|
||||
.dcache_bsize = 128,
|
||||
.num_pmcs = 6,
|
||||
.pmc_type = PPC_PMC_IBM,
|
||||
.oprofile_cpu_type = "ppc64/power6",
|
||||
.oprofile_type = PPC_OPROFILE_POWER4,
|
||||
.oprofile_mmcra_sihv = POWER6_MMCRA_SIHV,
|
||||
|
|
@ -340,6 +356,7 @@ static struct cpu_spec cpu_specs[] = {
|
|||
.icache_bsize = 128,
|
||||
.dcache_bsize = 128,
|
||||
.num_pmcs = 4,
|
||||
.pmc_type = PPC_PMC_IBM,
|
||||
.oprofile_cpu_type = "ppc64/cell-be",
|
||||
.oprofile_type = PPC_OPROFILE_CELL,
|
||||
.platform = "ppc-cell-be",
|
||||
|
|
@ -353,6 +370,9 @@ static struct cpu_spec cpu_specs[] = {
|
|||
.icache_bsize = 64,
|
||||
.dcache_bsize = 64,
|
||||
.num_pmcs = 6,
|
||||
.pmc_type = PPC_PMC_PA6T,
|
||||
.cpu_setup = __setup_cpu_pa6t,
|
||||
.cpu_restore = __restore_cpu_pa6t,
|
||||
.platform = "pa6t",
|
||||
},
|
||||
{ /* default match */
|
||||
|
|
@ -364,6 +384,7 @@ static struct cpu_spec cpu_specs[] = {
|
|||
.icache_bsize = 128,
|
||||
.dcache_bsize = 128,
|
||||
.num_pmcs = 6,
|
||||
.pmc_type = PPC_PMC_IBM,
|
||||
.platform = "power4",
|
||||
}
|
||||
#endif /* CONFIG_PPC64 */
|
||||
|
|
|
|||
|
|
@ -172,13 +172,18 @@ syscall_error_cont:
|
|||
stdcx. r0,0,r1 /* to clear the reservation */
|
||||
andi. r6,r8,MSR_PR
|
||||
ld r4,_LINK(r1)
|
||||
/*
|
||||
* Clear RI before restoring r13. If we are returning to
|
||||
* userspace and we take an exception after restoring r13,
|
||||
* we end up corrupting the userspace r13 value.
|
||||
*/
|
||||
li r12,MSR_RI
|
||||
andc r11,r10,r12
|
||||
mtmsrd r11,1 /* clear MSR.RI */
|
||||
beq- 1f
|
||||
ACCOUNT_CPU_USER_EXIT(r11, r12)
|
||||
ld r13,GPR13(r1) /* only restore r13 if returning to usermode */
|
||||
1: ld r2,GPR2(r1)
|
||||
li r12,MSR_RI
|
||||
andc r11,r10,r12
|
||||
mtmsrd r11,1 /* clear MSR.RI */
|
||||
ld r1,GPR1(r1)
|
||||
mtlr r4
|
||||
mtcr r5
|
||||
|
|
@ -488,42 +493,44 @@ END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
|
|||
#endif
|
||||
stb r5,PACASOFTIRQEN(r13)
|
||||
|
||||
ld r3,_MSR(r1)
|
||||
andi. r0,r3,MSR_RI
|
||||
beq- unrecov_restore
|
||||
|
||||
/* extract EE bit and use it to restore paca->hard_enabled */
|
||||
ld r3,_MSR(r1)
|
||||
rldicl r4,r3,49,63 /* r0 = (r3 >> 15) & 1 */
|
||||
stb r4,PACAHARDIRQEN(r13)
|
||||
|
||||
andi. r0,r3,MSR_PR
|
||||
ld r4,_CTR(r1)
|
||||
ld r0,_LINK(r1)
|
||||
mtctr r4
|
||||
mtlr r0
|
||||
ld r4,_XER(r1)
|
||||
mtspr SPRN_XER,r4
|
||||
|
||||
REST_8GPRS(5, r1)
|
||||
|
||||
andi. r0,r3,MSR_RI
|
||||
beq- unrecov_restore
|
||||
|
||||
stdcx. r0,0,r1 /* to clear the reservation */
|
||||
|
||||
/*
|
||||
* Clear RI before restoring r13. If we are returning to
|
||||
* userspace and we take an exception after restoring r13,
|
||||
* we end up corrupting the userspace r13 value.
|
||||
*/
|
||||
mfmsr r4
|
||||
andc r4,r4,r0 /* r0 contains MSR_RI here */
|
||||
mtmsrd r4,1
|
||||
|
||||
/*
|
||||
* r13 is our per cpu area, only restore it if we are returning to
|
||||
* userspace
|
||||
*/
|
||||
andi. r0,r3,MSR_PR
|
||||
beq 1f
|
||||
ACCOUNT_CPU_USER_EXIT(r3, r4)
|
||||
ACCOUNT_CPU_USER_EXIT(r2, r4)
|
||||
REST_GPR(13, r1)
|
||||
1:
|
||||
ld r3,_CTR(r1)
|
||||
ld r0,_LINK(r1)
|
||||
mtctr r3
|
||||
mtlr r0
|
||||
ld r3,_XER(r1)
|
||||
mtspr SPRN_XER,r3
|
||||
|
||||
REST_8GPRS(5, r1)
|
||||
|
||||
stdcx. r0,0,r1 /* to clear the reservation */
|
||||
|
||||
mfmsr r0
|
||||
li r2, MSR_RI
|
||||
andc r0,r0,r2
|
||||
mtmsrd r0,1
|
||||
|
||||
ld r0,_MSR(r1)
|
||||
mtspr SPRN_SRR1,r0
|
||||
mtspr SPRN_SRR1,r3
|
||||
|
||||
ld r2,_CCR(r1)
|
||||
mtcrf 0xFF,r2
|
||||
|
|
|
|||
|
|
@ -344,12 +344,7 @@ i##n: \
|
|||
/* System reset */
|
||||
/* core99 pmac starts the seconary here by changing the vector, and
|
||||
putting it back to what it was (unknown_exception) when done. */
|
||||
#if defined(CONFIG_GEMINI) && defined(CONFIG_SMP)
|
||||
. = 0x100
|
||||
b __secondary_start_gemini
|
||||
#else
|
||||
EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD)
|
||||
#endif
|
||||
|
||||
/* Machine check */
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -613,7 +613,7 @@ system_call_pSeries:
|
|||
/*** pSeries interrupt support ***/
|
||||
|
||||
/* moved from 0xf00 */
|
||||
MASKABLE_EXCEPTION_PSERIES(., performance_monitor)
|
||||
STD_EXCEPTION_PSERIES(., performance_monitor)
|
||||
|
||||
/*
|
||||
* An interrupt came in while soft-disabled; clear EE in SRR1,
|
||||
|
|
|
|||
|
|
@ -12,23 +12,23 @@
|
|||
* Here comes the ppc64 implementation of the IOMAP
|
||||
* interfaces.
|
||||
*/
|
||||
unsigned int fastcall ioread8(void __iomem *addr)
|
||||
unsigned int ioread8(void __iomem *addr)
|
||||
{
|
||||
return readb(addr);
|
||||
}
|
||||
unsigned int fastcall ioread16(void __iomem *addr)
|
||||
unsigned int ioread16(void __iomem *addr)
|
||||
{
|
||||
return readw(addr);
|
||||
}
|
||||
unsigned int fastcall ioread16be(void __iomem *addr)
|
||||
unsigned int ioread16be(void __iomem *addr)
|
||||
{
|
||||
return in_be16(addr);
|
||||
}
|
||||
unsigned int fastcall ioread32(void __iomem *addr)
|
||||
unsigned int ioread32(void __iomem *addr)
|
||||
{
|
||||
return readl(addr);
|
||||
}
|
||||
unsigned int fastcall ioread32be(void __iomem *addr)
|
||||
unsigned int ioread32be(void __iomem *addr)
|
||||
{
|
||||
return in_be32(addr);
|
||||
}
|
||||
|
|
@ -38,23 +38,23 @@ EXPORT_SYMBOL(ioread16be);
|
|||
EXPORT_SYMBOL(ioread32);
|
||||
EXPORT_SYMBOL(ioread32be);
|
||||
|
||||
void fastcall iowrite8(u8 val, void __iomem *addr)
|
||||
void iowrite8(u8 val, void __iomem *addr)
|
||||
{
|
||||
writeb(val, addr);
|
||||
}
|
||||
void fastcall iowrite16(u16 val, void __iomem *addr)
|
||||
void iowrite16(u16 val, void __iomem *addr)
|
||||
{
|
||||
writew(val, addr);
|
||||
}
|
||||
void fastcall iowrite16be(u16 val, void __iomem *addr)
|
||||
void iowrite16be(u16 val, void __iomem *addr)
|
||||
{
|
||||
out_be16(addr, val);
|
||||
}
|
||||
void fastcall iowrite32(u32 val, void __iomem *addr)
|
||||
void iowrite32(u32 val, void __iomem *addr)
|
||||
{
|
||||
writel(val, addr);
|
||||
}
|
||||
void fastcall iowrite32be(u32 val, void __iomem *addr)
|
||||
void iowrite32be(u32 val, void __iomem *addr)
|
||||
{
|
||||
out_be32(addr, val);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -281,10 +281,10 @@ void do_IRQ(struct pt_regs *regs)
|
|||
|
||||
/*
|
||||
* Every platform is required to implement ppc_md.get_irq.
|
||||
* This function will either return an irq number or -1 to
|
||||
* This function will either return an irq number or NO_IRQ to
|
||||
* indicate there are no more pending.
|
||||
* The value -2 is for buggy hardware and means that this IRQ
|
||||
* has already been handled. -- Tom
|
||||
* The value NO_IRQ_IGNORE is for buggy hardware and means that this
|
||||
* IRQ has already been handled. -- Tom
|
||||
*/
|
||||
irq = ppc_md.get_irq();
|
||||
|
||||
|
|
@ -604,6 +604,8 @@ unsigned int irq_create_mapping(struct irq_host *host,
|
|||
*/
|
||||
virq = irq_find_mapping(host, hwirq);
|
||||
if (virq != IRQ_NONE) {
|
||||
if (host->ops->remap)
|
||||
host->ops->remap(host, virq, hwirq);
|
||||
pr_debug("irq: -> existing mapping on virq %d\n", virq);
|
||||
return virq;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -46,8 +46,8 @@ int __kprobes arch_prepare_kprobe(struct kprobe *p)
|
|||
if ((unsigned long)p->addr & 0x03) {
|
||||
printk("Attempt to register kprobe at an unaligned address\n");
|
||||
ret = -EINVAL;
|
||||
} else if (IS_MTMSRD(insn) || IS_RFID(insn)) {
|
||||
printk("Cannot register a kprobe on rfid or mtmsrd\n");
|
||||
} else if (IS_MTMSRD(insn) || IS_RFID(insn) || IS_RFI(insn)) {
|
||||
printk("Cannot register a kprobe on rfi/rfid or mtmsr[d]\n");
|
||||
ret = -EINVAL;
|
||||
}
|
||||
|
||||
|
|
@ -483,8 +483,12 @@ int __kprobes setjmp_pre_handler(struct kprobe *p, struct pt_regs *regs)
|
|||
memcpy(&kcb->jprobe_saved_regs, regs, sizeof(struct pt_regs));
|
||||
|
||||
/* setup return addr to the jprobe handler routine */
|
||||
#ifdef CONFIG_PPC64
|
||||
regs->nip = (unsigned long)(((func_descr_t *)jp->entry)->entry);
|
||||
regs->gpr[2] = (unsigned long)(((func_descr_t *)jp->entry)->toc);
|
||||
#else
|
||||
regs->nip = (unsigned long)jp->entry;
|
||||
#endif
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -439,6 +439,10 @@ static ssize_t lparcfg_write(struct file *file, const char __user * buf,
|
|||
|
||||
ssize_t retval = -ENOMEM;
|
||||
|
||||
if (!firmware_has_feature(FW_FEATURE_SPLPAR) ||
|
||||
firmware_has_feature(FW_FEATURE_ISERIES))
|
||||
return -EINVAL;
|
||||
|
||||
kbuf = kmalloc(count, GFP_KERNEL);
|
||||
if (!kbuf)
|
||||
goto out;
|
||||
|
|
@ -517,7 +521,7 @@ static int pseries_lparcfg_data(struct seq_file *m, void *v)
|
|||
static ssize_t lparcfg_write(struct file *file, const char __user * buf,
|
||||
size_t count, loff_t * off)
|
||||
{
|
||||
return count;
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_PPC_PSERIES */
|
||||
|
|
@ -570,6 +574,7 @@ static int lparcfg_open(struct inode *inode, struct file *file)
|
|||
struct file_operations lparcfg_fops = {
|
||||
.owner = THIS_MODULE,
|
||||
.read = seq_read,
|
||||
.write = lparcfg_write,
|
||||
.open = lparcfg_open,
|
||||
.release = single_release,
|
||||
};
|
||||
|
|
@ -581,10 +586,8 @@ int __init lparcfg_init(void)
|
|||
|
||||
/* Allow writing if we have FW_FEATURE_SPLPAR */
|
||||
if (firmware_has_feature(FW_FEATURE_SPLPAR) &&
|
||||
!firmware_has_feature(FW_FEATURE_ISERIES)) {
|
||||
lparcfg_fops.write = lparcfg_write;
|
||||
!firmware_has_feature(FW_FEATURE_ISERIES))
|
||||
mode |= S_IWUSR;
|
||||
}
|
||||
|
||||
ent = create_proc_entry("ppc64/lparcfg", mode, NULL);
|
||||
if (ent) {
|
||||
|
|
|
|||
|
|
@ -311,6 +311,46 @@ _GLOBAL(real_writeb)
|
|||
blr
|
||||
#endif /* defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE) */
|
||||
|
||||
#ifdef CONFIG_PPC_PASEMI
|
||||
|
||||
/* No support in all binutils for these yet, so use defines */
|
||||
#define LBZCIX(RT,RA,RB) .long (0x7c0006aa|(RT<<21)|(RA<<16)|(RB << 11))
|
||||
#define STBCIX(RS,RA,RB) .long (0x7c0007aa|(RS<<21)|(RA<<16)|(RB << 11))
|
||||
|
||||
|
||||
_GLOBAL(real_205_readb)
|
||||
mfmsr r7
|
||||
ori r0,r7,MSR_DR
|
||||
xori r0,r0,MSR_DR
|
||||
sync
|
||||
mtmsrd r0
|
||||
sync
|
||||
isync
|
||||
LBZCIX(r3,0,r3)
|
||||
isync
|
||||
mtmsrd r7
|
||||
sync
|
||||
isync
|
||||
blr
|
||||
|
||||
_GLOBAL(real_205_writeb)
|
||||
mfmsr r7
|
||||
ori r0,r7,MSR_DR
|
||||
xori r0,r0,MSR_DR
|
||||
sync
|
||||
mtmsrd r0
|
||||
sync
|
||||
isync
|
||||
STBCIX(r3,0,r4)
|
||||
isync
|
||||
mtmsrd r7
|
||||
sync
|
||||
isync
|
||||
blr
|
||||
|
||||
#endif /* CONFIG_PPC_PASEMI */
|
||||
|
||||
|
||||
#ifdef CONFIG_CPU_FREQ_PMAC64
|
||||
/*
|
||||
* SCOM access functions for 970 (FX only for now)
|
||||
|
|
|
|||
|
|
@ -224,7 +224,12 @@ int apply_relocate_add(Elf32_Shdr *sechdrs,
|
|||
/* Low half of the symbol */
|
||||
*(uint16_t *)location = value;
|
||||
break;
|
||||
|
||||
|
||||
case R_PPC_ADDR16_HI:
|
||||
/* Higher half of the symbol */
|
||||
*(uint16_t *)location = (value >> 16);
|
||||
break;
|
||||
|
||||
case R_PPC_ADDR16_HA:
|
||||
/* Sign-adjusted lower 16 bits: PPC ELF ABI says:
|
||||
(((x >> 16) + ((x & 0x8000) ? 1 : 0))) & 0xFFFF.
|
||||
|
|
|
|||
|
|
@ -1450,7 +1450,6 @@ int pci_read_irq_line(struct pci_dev *pci_dev)
|
|||
return -1;
|
||||
}
|
||||
pci_dev->irq = virq;
|
||||
pci_write_config_byte(pci_dev, PCI_INTERRUPT_LINE, virq);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1323,7 +1323,6 @@ int pci_read_irq_line(struct pci_dev *pci_dev)
|
|||
DBG(" -> mapped to linux irq %d\n", virq);
|
||||
|
||||
pci_dev->irq = virq;
|
||||
pci_write_config_byte(pci_dev, PCI_INTERRUPT_LINE, virq);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -17,40 +17,25 @@
|
|||
#include <linux/module.h>
|
||||
|
||||
#include <asm/processor.h>
|
||||
#include <asm/cputable.h>
|
||||
#include <asm/pmc.h>
|
||||
|
||||
#ifndef MMCR0_PMA0
|
||||
#define MMCR0_PMA0 0
|
||||
#endif
|
||||
|
||||
static void dummy_perf(struct pt_regs *regs)
|
||||
{
|
||||
#if defined(CONFIG_FSL_BOOKE) && !defined(CONFIG_E200)
|
||||
static void dummy_perf(struct pt_regs *regs)
|
||||
{
|
||||
unsigned int pmgc0 = mfpmr(PMRN_PMGC0);
|
||||
|
||||
pmgc0 &= ~PMGC0_PMIE;
|
||||
mtpmr(PMRN_PMGC0, pmgc0);
|
||||
}
|
||||
mtpmr(PMRN_PMGC0, mfpmr(PMRN_PMGC0) & ~PMGC0_PMIE);
|
||||
#elif defined(CONFIG_PPC64) || defined(CONFIG_6xx)
|
||||
|
||||
#ifndef MMCR0_PMAO
|
||||
#define MMCR0_PMAO 0
|
||||
#endif
|
||||
|
||||
/* Ensure exceptions are disabled */
|
||||
static void dummy_perf(struct pt_regs *regs)
|
||||
{
|
||||
unsigned int mmcr0 = mfspr(SPRN_MMCR0);
|
||||
|
||||
mmcr0 &= ~(MMCR0_PMXE|MMCR0_PMAO);
|
||||
mtspr(SPRN_MMCR0, mmcr0);
|
||||
}
|
||||
if (cur_cpu_spec->pmc_type == PPC_PMC_IBM)
|
||||
mtspr(SPRN_MMCR0, mfspr(SPRN_MMCR0) & ~(MMCR0_PMXE|MMCR0_PMA0));
|
||||
#else
|
||||
/* Ensure exceptions are disabled */
|
||||
static void dummy_perf(struct pt_regs *regs)
|
||||
{
|
||||
unsigned int mmcr0 = mfspr(SPRN_MMCR0);
|
||||
|
||||
mmcr0 &= ~(MMCR0_PMXE);
|
||||
mtspr(SPRN_MMCR0, mmcr0);
|
||||
}
|
||||
mtspr(SPRN_MMCR0, mfspr(SPRN_MMCR0) & ~MMCR0_PMXE);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
static DEFINE_SPINLOCK(pmc_owner_lock);
|
||||
static void *pmc_owner_caller; /* mostly for debugging */
|
||||
|
|
|
|||
|
|
@ -44,6 +44,7 @@
|
|||
#include <asm/btext.h>
|
||||
#include <asm/div64.h>
|
||||
#include <asm/signal.h>
|
||||
#include <asm/dcr.h>
|
||||
|
||||
#ifdef CONFIG_8xx
|
||||
#include <asm/commproc.h>
|
||||
|
|
|
|||
|
|
@ -1221,8 +1221,7 @@ struct device_node *of_find_node_by_name(struct device_node *from,
|
|||
if (np->name != NULL && strcasecmp(np->name, name) == 0
|
||||
&& of_node_get(np))
|
||||
break;
|
||||
if (from)
|
||||
of_node_put(from);
|
||||
of_node_put(from);
|
||||
read_unlock(&devtree_lock);
|
||||
return np;
|
||||
}
|
||||
|
|
@ -1250,8 +1249,7 @@ struct device_node *of_find_node_by_type(struct device_node *from,
|
|||
if (np->type != 0 && strcasecmp(np->type, type) == 0
|
||||
&& of_node_get(np))
|
||||
break;
|
||||
if (from)
|
||||
of_node_put(from);
|
||||
of_node_put(from);
|
||||
read_unlock(&devtree_lock);
|
||||
return np;
|
||||
}
|
||||
|
|
@ -1285,8 +1283,7 @@ struct device_node *of_find_compatible_node(struct device_node *from,
|
|||
if (device_is_compatible(np, compatible) && of_node_get(np))
|
||||
break;
|
||||
}
|
||||
if (from)
|
||||
of_node_put(from);
|
||||
of_node_put(from);
|
||||
read_unlock(&devtree_lock);
|
||||
return np;
|
||||
}
|
||||
|
|
@ -1329,8 +1326,7 @@ struct device_node *of_find_node_by_phandle(phandle handle)
|
|||
for (np = allnodes; np != 0; np = np->allnext)
|
||||
if (np->linux_phandle == handle)
|
||||
break;
|
||||
if (np)
|
||||
of_node_get(np);
|
||||
of_node_get(np);
|
||||
read_unlock(&devtree_lock);
|
||||
return np;
|
||||
}
|
||||
|
|
@ -1353,8 +1349,7 @@ struct device_node *of_find_all_nodes(struct device_node *prev)
|
|||
for (; np != 0; np = np->allnext)
|
||||
if (of_node_get(np))
|
||||
break;
|
||||
if (prev)
|
||||
of_node_put(prev);
|
||||
of_node_put(prev);
|
||||
read_unlock(&devtree_lock);
|
||||
return np;
|
||||
}
|
||||
|
|
@ -1399,8 +1394,7 @@ struct device_node *of_get_next_child(const struct device_node *node,
|
|||
for (; next != 0; next = next->sibling)
|
||||
if (of_node_get(next))
|
||||
break;
|
||||
if (prev)
|
||||
of_node_put(prev);
|
||||
of_node_put(prev);
|
||||
read_unlock(&devtree_lock);
|
||||
return next;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -532,16 +532,22 @@ void do_syscall_trace_enter(struct pt_regs *regs)
|
|||
&& (current->ptrace & PT_PTRACED))
|
||||
do_syscall_trace();
|
||||
|
||||
if (unlikely(current->audit_context))
|
||||
audit_syscall_entry(
|
||||
#ifdef CONFIG_PPC32
|
||||
AUDIT_ARCH_PPC,
|
||||
#else
|
||||
test_thread_flag(TIF_32BIT)?AUDIT_ARCH_PPC:AUDIT_ARCH_PPC64,
|
||||
if (unlikely(current->audit_context)) {
|
||||
#ifdef CONFIG_PPC64
|
||||
if (!test_thread_flag(TIF_32BIT))
|
||||
audit_syscall_entry(AUDIT_ARCH_PPC64,
|
||||
regs->gpr[0],
|
||||
regs->gpr[3], regs->gpr[4],
|
||||
regs->gpr[5], regs->gpr[6]);
|
||||
else
|
||||
#endif
|
||||
regs->gpr[0],
|
||||
regs->gpr[3], regs->gpr[4],
|
||||
regs->gpr[5], regs->gpr[6]);
|
||||
audit_syscall_entry(AUDIT_ARCH_PPC,
|
||||
regs->gpr[0],
|
||||
regs->gpr[3] & 0xffffffff,
|
||||
regs->gpr[4] & 0xffffffff,
|
||||
regs->gpr[5] & 0xffffffff,
|
||||
regs->gpr[6] & 0xffffffff);
|
||||
}
|
||||
}
|
||||
|
||||
void do_syscall_trace_leave(struct pt_regs *regs)
|
||||
|
|
|
|||
|
|
@ -65,6 +65,7 @@ int have_of = 1;
|
|||
|
||||
#ifdef CONFIG_VGA_CONSOLE
|
||||
unsigned long vgacon_remap_base;
|
||||
EXPORT_SYMBOL(vgacon_remap_base);
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -169,6 +169,11 @@ static ssize_t __attribute_used__ \
|
|||
return count; \
|
||||
}
|
||||
|
||||
|
||||
/* Let's define all possible registers, we'll only hook up the ones
|
||||
* that are implemented on the current processor
|
||||
*/
|
||||
|
||||
SYSFS_PMCSETUP(mmcr0, SPRN_MMCR0);
|
||||
SYSFS_PMCSETUP(mmcr1, SPRN_MMCR1);
|
||||
SYSFS_PMCSETUP(mmcra, SPRN_MMCRA);
|
||||
|
|
@ -184,55 +189,87 @@ SYSFS_PMCSETUP(purr, SPRN_PURR);
|
|||
SYSFS_PMCSETUP(spurr, SPRN_SPURR);
|
||||
SYSFS_PMCSETUP(dscr, SPRN_DSCR);
|
||||
|
||||
static SYSDEV_ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0);
|
||||
static SYSDEV_ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1);
|
||||
SYSFS_PMCSETUP(pa6t_pmc0, PA6T_SPRN_PMC0);
|
||||
SYSFS_PMCSETUP(pa6t_pmc1, PA6T_SPRN_PMC1);
|
||||
SYSFS_PMCSETUP(pa6t_pmc2, PA6T_SPRN_PMC2);
|
||||
SYSFS_PMCSETUP(pa6t_pmc3, PA6T_SPRN_PMC3);
|
||||
SYSFS_PMCSETUP(pa6t_pmc4, PA6T_SPRN_PMC4);
|
||||
SYSFS_PMCSETUP(pa6t_pmc5, PA6T_SPRN_PMC5);
|
||||
|
||||
|
||||
static SYSDEV_ATTR(mmcra, 0600, show_mmcra, store_mmcra);
|
||||
static SYSDEV_ATTR(pmc1, 0600, show_pmc1, store_pmc1);
|
||||
static SYSDEV_ATTR(pmc2, 0600, show_pmc2, store_pmc2);
|
||||
static SYSDEV_ATTR(pmc3, 0600, show_pmc3, store_pmc3);
|
||||
static SYSDEV_ATTR(pmc4, 0600, show_pmc4, store_pmc4);
|
||||
static SYSDEV_ATTR(pmc5, 0600, show_pmc5, store_pmc5);
|
||||
static SYSDEV_ATTR(pmc6, 0600, show_pmc6, store_pmc6);
|
||||
static SYSDEV_ATTR(pmc7, 0600, show_pmc7, store_pmc7);
|
||||
static SYSDEV_ATTR(pmc8, 0600, show_pmc8, store_pmc8);
|
||||
static SYSDEV_ATTR(purr, 0600, show_purr, NULL);
|
||||
static SYSDEV_ATTR(spurr, 0600, show_spurr, NULL);
|
||||
static SYSDEV_ATTR(dscr, 0600, show_dscr, store_dscr);
|
||||
static SYSDEV_ATTR(purr, 0600, show_purr, store_purr);
|
||||
|
||||
static struct sysdev_attribute ibm_common_attrs[] = {
|
||||
_SYSDEV_ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
|
||||
_SYSDEV_ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
|
||||
};
|
||||
|
||||
static struct sysdev_attribute ibm_pmc_attrs[] = {
|
||||
_SYSDEV_ATTR(pmc1, 0600, show_pmc1, store_pmc1),
|
||||
_SYSDEV_ATTR(pmc2, 0600, show_pmc2, store_pmc2),
|
||||
_SYSDEV_ATTR(pmc3, 0600, show_pmc3, store_pmc3),
|
||||
_SYSDEV_ATTR(pmc4, 0600, show_pmc4, store_pmc4),
|
||||
_SYSDEV_ATTR(pmc5, 0600, show_pmc5, store_pmc5),
|
||||
_SYSDEV_ATTR(pmc6, 0600, show_pmc6, store_pmc6),
|
||||
_SYSDEV_ATTR(pmc7, 0600, show_pmc7, store_pmc7),
|
||||
_SYSDEV_ATTR(pmc8, 0600, show_pmc8, store_pmc8),
|
||||
};
|
||||
|
||||
static struct sysdev_attribute pa6t_attrs[] = {
|
||||
_SYSDEV_ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
|
||||
_SYSDEV_ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
|
||||
_SYSDEV_ATTR(pmc0, 0600, show_pa6t_pmc0, store_pa6t_pmc0),
|
||||
_SYSDEV_ATTR(pmc1, 0600, show_pa6t_pmc1, store_pa6t_pmc1),
|
||||
_SYSDEV_ATTR(pmc2, 0600, show_pa6t_pmc2, store_pa6t_pmc2),
|
||||
_SYSDEV_ATTR(pmc3, 0600, show_pa6t_pmc3, store_pa6t_pmc3),
|
||||
_SYSDEV_ATTR(pmc4, 0600, show_pa6t_pmc4, store_pa6t_pmc4),
|
||||
_SYSDEV_ATTR(pmc5, 0600, show_pa6t_pmc5, store_pa6t_pmc5),
|
||||
};
|
||||
|
||||
|
||||
static void register_cpu_online(unsigned int cpu)
|
||||
{
|
||||
struct cpu *c = &per_cpu(cpu_devices, cpu);
|
||||
struct sys_device *s = &c->sysdev;
|
||||
struct sysdev_attribute *attrs, *pmc_attrs;
|
||||
int i, nattrs;
|
||||
|
||||
if (!firmware_has_feature(FW_FEATURE_ISERIES) &&
|
||||
cpu_has_feature(CPU_FTR_SMT))
|
||||
sysdev_create_file(s, &attr_smt_snooze_delay);
|
||||
|
||||
/* PMC stuff */
|
||||
switch (cur_cpu_spec->pmc_type) {
|
||||
case PPC_PMC_IBM:
|
||||
attrs = ibm_common_attrs;
|
||||
nattrs = sizeof(ibm_common_attrs) / sizeof(struct sysdev_attribute);
|
||||
pmc_attrs = ibm_pmc_attrs;
|
||||
break;
|
||||
case PPC_PMC_PA6T:
|
||||
/* PA Semi starts counting at PMC0 */
|
||||
attrs = pa6t_attrs;
|
||||
nattrs = sizeof(pa6t_attrs) / sizeof(struct sysdev_attribute);
|
||||
pmc_attrs = NULL;
|
||||
break;
|
||||
default:
|
||||
attrs = NULL;
|
||||
nattrs = 0;
|
||||
pmc_attrs = NULL;
|
||||
}
|
||||
|
||||
sysdev_create_file(s, &attr_mmcr0);
|
||||
sysdev_create_file(s, &attr_mmcr1);
|
||||
for (i = 0; i < nattrs; i++)
|
||||
sysdev_create_file(s, &attrs[i]);
|
||||
|
||||
if (pmc_attrs)
|
||||
for (i = 0; i < cur_cpu_spec->num_pmcs; i++)
|
||||
sysdev_create_file(s, &pmc_attrs[i]);
|
||||
|
||||
if (cpu_has_feature(CPU_FTR_MMCRA))
|
||||
sysdev_create_file(s, &attr_mmcra);
|
||||
|
||||
if (cur_cpu_spec->num_pmcs >= 1)
|
||||
sysdev_create_file(s, &attr_pmc1);
|
||||
if (cur_cpu_spec->num_pmcs >= 2)
|
||||
sysdev_create_file(s, &attr_pmc2);
|
||||
if (cur_cpu_spec->num_pmcs >= 3)
|
||||
sysdev_create_file(s, &attr_pmc3);
|
||||
if (cur_cpu_spec->num_pmcs >= 4)
|
||||
sysdev_create_file(s, &attr_pmc4);
|
||||
if (cur_cpu_spec->num_pmcs >= 5)
|
||||
sysdev_create_file(s, &attr_pmc5);
|
||||
if (cur_cpu_spec->num_pmcs >= 6)
|
||||
sysdev_create_file(s, &attr_pmc6);
|
||||
if (cur_cpu_spec->num_pmcs >= 7)
|
||||
sysdev_create_file(s, &attr_pmc7);
|
||||
if (cur_cpu_spec->num_pmcs >= 8)
|
||||
sysdev_create_file(s, &attr_pmc8);
|
||||
|
||||
if (cpu_has_feature(CPU_FTR_PURR))
|
||||
sysdev_create_file(s, &attr_purr);
|
||||
|
||||
|
|
@ -248,6 +285,8 @@ static void unregister_cpu_online(unsigned int cpu)
|
|||
{
|
||||
struct cpu *c = &per_cpu(cpu_devices, cpu);
|
||||
struct sys_device *s = &c->sysdev;
|
||||
struct sysdev_attribute *attrs, *pmc_attrs;
|
||||
int i, nattrs;
|
||||
|
||||
BUG_ON(!c->hotpluggable);
|
||||
|
||||
|
|
@ -256,30 +295,34 @@ static void unregister_cpu_online(unsigned int cpu)
|
|||
sysdev_remove_file(s, &attr_smt_snooze_delay);
|
||||
|
||||
/* PMC stuff */
|
||||
switch (cur_cpu_spec->pmc_type) {
|
||||
case PPC_PMC_IBM:
|
||||
attrs = ibm_common_attrs;
|
||||
nattrs = sizeof(ibm_common_attrs) / sizeof(struct sysdev_attribute);
|
||||
pmc_attrs = ibm_pmc_attrs;
|
||||
break;
|
||||
case PPC_PMC_PA6T:
|
||||
/* PA Semi starts counting at PMC0 */
|
||||
attrs = pa6t_attrs;
|
||||
nattrs = sizeof(pa6t_attrs) / sizeof(struct sysdev_attribute);
|
||||
pmc_attrs = NULL;
|
||||
break;
|
||||
default:
|
||||
attrs = NULL;
|
||||
nattrs = 0;
|
||||
pmc_attrs = NULL;
|
||||
}
|
||||
|
||||
sysdev_remove_file(s, &attr_mmcr0);
|
||||
sysdev_remove_file(s, &attr_mmcr1);
|
||||
for (i = 0; i < nattrs; i++)
|
||||
sysdev_remove_file(s, &attrs[i]);
|
||||
|
||||
if (pmc_attrs)
|
||||
for (i = 0; i < cur_cpu_spec->num_pmcs; i++)
|
||||
sysdev_remove_file(s, &pmc_attrs[i]);
|
||||
|
||||
if (cpu_has_feature(CPU_FTR_MMCRA))
|
||||
sysdev_remove_file(s, &attr_mmcra);
|
||||
|
||||
if (cur_cpu_spec->num_pmcs >= 1)
|
||||
sysdev_remove_file(s, &attr_pmc1);
|
||||
if (cur_cpu_spec->num_pmcs >= 2)
|
||||
sysdev_remove_file(s, &attr_pmc2);
|
||||
if (cur_cpu_spec->num_pmcs >= 3)
|
||||
sysdev_remove_file(s, &attr_pmc3);
|
||||
if (cur_cpu_spec->num_pmcs >= 4)
|
||||
sysdev_remove_file(s, &attr_pmc4);
|
||||
if (cur_cpu_spec->num_pmcs >= 5)
|
||||
sysdev_remove_file(s, &attr_pmc5);
|
||||
if (cur_cpu_spec->num_pmcs >= 6)
|
||||
sysdev_remove_file(s, &attr_pmc6);
|
||||
if (cur_cpu_spec->num_pmcs >= 7)
|
||||
sysdev_remove_file(s, &attr_pmc7);
|
||||
if (cur_cpu_spec->num_pmcs >= 8)
|
||||
sysdev_remove_file(s, &attr_pmc8);
|
||||
|
||||
if (cpu_has_feature(CPU_FTR_PURR))
|
||||
sysdev_remove_file(s, &attr_purr);
|
||||
|
||||
|
|
|
|||
|
|
@ -174,7 +174,7 @@ void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
|
|||
* generate the same exception over and over again and we get
|
||||
* nowhere. Better to kill it and let the kernel panic.
|
||||
*/
|
||||
if (current->pid == 1) {
|
||||
if (is_init(current)) {
|
||||
__sighandler_t handler;
|
||||
|
||||
spin_lock_irq(¤t->sighand->siglock);
|
||||
|
|
@ -535,34 +535,40 @@ static void emulate_single_step(struct pt_regs *regs)
|
|||
}
|
||||
}
|
||||
|
||||
static void parse_fpe(struct pt_regs *regs)
|
||||
static inline int __parse_fpscr(unsigned long fpscr)
|
||||
{
|
||||
int code = 0;
|
||||
unsigned long fpscr;
|
||||
|
||||
flush_fp_to_thread(current);
|
||||
|
||||
fpscr = current->thread.fpscr.val;
|
||||
int ret = 0;
|
||||
|
||||
/* Invalid operation */
|
||||
if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX))
|
||||
code = FPE_FLTINV;
|
||||
ret = FPE_FLTINV;
|
||||
|
||||
/* Overflow */
|
||||
else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX))
|
||||
code = FPE_FLTOVF;
|
||||
ret = FPE_FLTOVF;
|
||||
|
||||
/* Underflow */
|
||||
else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX))
|
||||
code = FPE_FLTUND;
|
||||
ret = FPE_FLTUND;
|
||||
|
||||
/* Divide by zero */
|
||||
else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX))
|
||||
code = FPE_FLTDIV;
|
||||
ret = FPE_FLTDIV;
|
||||
|
||||
/* Inexact result */
|
||||
else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX))
|
||||
code = FPE_FLTRES;
|
||||
ret = FPE_FLTRES;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void parse_fpe(struct pt_regs *regs)
|
||||
{
|
||||
int code = 0;
|
||||
|
||||
flush_fp_to_thread(current);
|
||||
|
||||
code = __parse_fpscr(current->thread.fpscr.val);
|
||||
|
||||
_exception(SIGFPE, regs, code, regs->nip);
|
||||
}
|
||||
|
|
@ -739,20 +745,7 @@ void __kprobes program_check_exception(struct pt_regs *regs)
|
|||
extern int do_mathemu(struct pt_regs *regs);
|
||||
|
||||
/* We can now get here via a FP Unavailable exception if the core
|
||||
* has no FPU, in that case no reason flags will be set */
|
||||
#ifdef CONFIG_MATH_EMULATION
|
||||
/* (reason & REASON_ILLEGAL) would be the obvious thing here,
|
||||
* but there seems to be a hardware bug on the 405GP (RevD)
|
||||
* that means ESR is sometimes set incorrectly - either to
|
||||
* ESR_DST (!?) or 0. In the process of chasing this with the
|
||||
* hardware people - not sure if it can happen on any illegal
|
||||
* instruction or only on FP instructions, whether there is a
|
||||
* pattern to occurences etc. -dgibson 31/Mar/2003 */
|
||||
if (!(reason & REASON_TRAP) && do_mathemu(regs) == 0) {
|
||||
emulate_single_step(regs);
|
||||
return;
|
||||
}
|
||||
#endif /* CONFIG_MATH_EMULATION */
|
||||
* has no FPU, in that case the reason flags will be 0 */
|
||||
|
||||
if (reason & REASON_FP) {
|
||||
/* IEEE FP exception */
|
||||
|
|
@ -778,6 +771,31 @@ void __kprobes program_check_exception(struct pt_regs *regs)
|
|||
|
||||
local_irq_enable();
|
||||
|
||||
#ifdef CONFIG_MATH_EMULATION
|
||||
/* (reason & REASON_ILLEGAL) would be the obvious thing here,
|
||||
* but there seems to be a hardware bug on the 405GP (RevD)
|
||||
* that means ESR is sometimes set incorrectly - either to
|
||||
* ESR_DST (!?) or 0. In the process of chasing this with the
|
||||
* hardware people - not sure if it can happen on any illegal
|
||||
* instruction or only on FP instructions, whether there is a
|
||||
* pattern to occurences etc. -dgibson 31/Mar/2003 */
|
||||
switch (do_mathemu(regs)) {
|
||||
case 0:
|
||||
emulate_single_step(regs);
|
||||
return;
|
||||
case 1: {
|
||||
int code = 0;
|
||||
code = __parse_fpscr(current->thread.fpscr.val);
|
||||
_exception(SIGFPE, regs, code, regs->nip);
|
||||
return;
|
||||
}
|
||||
case -EFAULT:
|
||||
_exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
|
||||
return;
|
||||
}
|
||||
/* fall through on any other errors */
|
||||
#endif /* CONFIG_MATH_EMULATION */
|
||||
|
||||
/* Try to emulate it if we should. */
|
||||
if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) {
|
||||
switch (emulate_instruction(regs)) {
|
||||
|
|
@ -891,18 +909,39 @@ void SoftwareEmulation(struct pt_regs *regs)
|
|||
|
||||
#ifdef CONFIG_MATH_EMULATION
|
||||
errcode = do_mathemu(regs);
|
||||
|
||||
switch (errcode) {
|
||||
case 0:
|
||||
emulate_single_step(regs);
|
||||
return;
|
||||
case 1: {
|
||||
int code = 0;
|
||||
code = __parse_fpscr(current->thread.fpscr.val);
|
||||
_exception(SIGFPE, regs, code, regs->nip);
|
||||
return;
|
||||
}
|
||||
case -EFAULT:
|
||||
_exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
|
||||
return;
|
||||
default:
|
||||
_exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
|
||||
return;
|
||||
}
|
||||
|
||||
#else
|
||||
errcode = Soft_emulate_8xx(regs);
|
||||
#endif
|
||||
if (errcode) {
|
||||
if (errcode > 0)
|
||||
_exception(SIGFPE, regs, 0, 0);
|
||||
else if (errcode == -EFAULT)
|
||||
_exception(SIGSEGV, regs, 0, 0);
|
||||
else
|
||||
_exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
|
||||
} else
|
||||
switch (errcode) {
|
||||
case 0:
|
||||
emulate_single_step(regs);
|
||||
return;
|
||||
case 1:
|
||||
_exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
|
||||
return;
|
||||
case -EFAULT:
|
||||
_exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#endif /* CONFIG_8xx */
|
||||
|
||||
|
|
|
|||
|
|
@ -45,6 +45,10 @@ void __init udbg_early_init(void)
|
|||
#elif defined(CONFIG_PPC_EARLY_DEBUG_ISERIES)
|
||||
/* For iSeries - hit Ctrl-x Ctrl-x to see the output */
|
||||
udbg_init_iseries();
|
||||
#elif defined(CONFIG_PPC_EARLY_DEBUG_BEAT)
|
||||
udbg_init_debug_beat();
|
||||
#elif defined(CONFIG_PPC_EARLY_DEBUG_PAS_REALMODE)
|
||||
udbg_init_pas_realmode();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -14,6 +14,8 @@
|
|||
|
||||
extern u8 real_readb(volatile u8 __iomem *addr);
|
||||
extern void real_writeb(u8 data, volatile u8 __iomem *addr);
|
||||
extern u8 real_205_readb(volatile u8 __iomem *addr);
|
||||
extern void real_205_writeb(u8 data, volatile u8 __iomem *addr);
|
||||
|
||||
struct NS16550 {
|
||||
/* this struct must be packed */
|
||||
|
|
@ -167,3 +169,25 @@ void __init udbg_init_maple_realmode(void)
|
|||
udbg_getc_poll = NULL;
|
||||
}
|
||||
#endif /* CONFIG_PPC_MAPLE */
|
||||
|
||||
#ifdef CONFIG_PPC_PASEMI
|
||||
void udbg_pas_real_putc(char c)
|
||||
{
|
||||
if (udbg_comport) {
|
||||
while ((real_205_readb(&udbg_comport->lsr) & LSR_THRE) == 0)
|
||||
/* wait for idle */;
|
||||
real_205_writeb(c, &udbg_comport->thr); eieio();
|
||||
if (c == '\n')
|
||||
udbg_pas_real_putc('\r');
|
||||
}
|
||||
}
|
||||
|
||||
void udbg_init_pas_realmode(void)
|
||||
{
|
||||
udbg_comport = (volatile struct NS16550 __iomem *)0xfcff03f8;
|
||||
|
||||
udbg_putc = udbg_pas_real_putc;
|
||||
udbg_getc = NULL;
|
||||
udbg_getc_poll = NULL;
|
||||
}
|
||||
#endif /* CONFIG_PPC_MAPLE */
|
||||
|
|
|
|||
|
|
@ -199,10 +199,8 @@ EXPORT_SYMBOL(vio_unregister_driver);
|
|||
/* vio_dev refcount hit 0 */
|
||||
static void __devinit vio_dev_release(struct device *dev)
|
||||
{
|
||||
if (dev->archdata.of_node) {
|
||||
/* XXX should free TCE table */
|
||||
of_node_put(dev->archdata.of_node);
|
||||
}
|
||||
/* XXX should free TCE table */
|
||||
of_node_put(dev->archdata.of_node);
|
||||
kfree(to_vio_dev(dev));
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -16,13 +16,15 @@ obj-$(CONFIG_PPC64) += checksum_64.o copypage_64.o copyuser_64.o \
|
|||
strcase.o
|
||||
obj-$(CONFIG_QUICC_ENGINE) += rheap.o
|
||||
obj-$(CONFIG_XMON) += sstep.o
|
||||
obj-$(CONFIG_KPROBES) += sstep.o
|
||||
obj-$(CONFIG_NOT_COHERENT_CACHE) += dma-noncoherent.o
|
||||
|
||||
ifeq ($(CONFIG_PPC64),y)
|
||||
obj-$(CONFIG_SMP) += locks.o
|
||||
obj-$(CONFIG_DEBUG_KERNEL) += sstep.o
|
||||
endif
|
||||
|
||||
# Temporary hack until we have migrated to asm-powerpc
|
||||
ifeq ($(CONFIG_PPC_MERGE),y)
|
||||
obj-$(CONFIG_8xx) += rheap.o
|
||||
obj-$(CONFIG_CPM2) += rheap.o
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -22,37 +22,13 @@
|
|||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/signal.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/ptrace.h>
|
||||
#include <linux/mman.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/swap.h>
|
||||
#include <linux/stddef.h>
|
||||
#include <linux/vmalloc.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/bootmem.h>
|
||||
#include <linux/highmem.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/hardirq.h>
|
||||
|
||||
#include <asm/pgalloc.h>
|
||||
#include <asm/prom.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/mmu_context.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/mmu.h>
|
||||
#include <asm/uaccess.h>
|
||||
#include <asm/smp.h>
|
||||
#include <asm/machdep.h>
|
||||
|
||||
int map_page(unsigned long va, phys_addr_t pa, int flags);
|
||||
|
||||
#include <asm/tlbflush.h>
|
||||
|
||||
|
|
@ -14,6 +14,7 @@
|
|||
*/
|
||||
#include <linux/types.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
|
|
@ -85,7 +86,8 @@ static int grow(rh_info_t * info, int max_blocks)
|
|||
info->flags &= ~RHIF_STATIC_BLOCK;
|
||||
|
||||
/* add all new blocks to the free list */
|
||||
for (i = 0, blk = block + info->max_blocks; i < new_blocks; i++, blk++)
|
||||
blk = block + info->max_blocks - new_blocks;
|
||||
for (i = 0; i < new_blocks; i++, blk++)
|
||||
list_add(&blk->list, &info->empty_list);
|
||||
|
||||
return 0;
|
||||
|
|
@ -670,7 +672,7 @@ void rh_dump(rh_info_t * info)
|
|||
int maxnr;
|
||||
int i, nr;
|
||||
|
||||
maxnr = sizeof(st) / sizeof(st[0]);
|
||||
maxnr = ARRAY_SIZE(st);
|
||||
|
||||
printk(KERN_INFO
|
||||
"info @0x%p (%d slots empty / %d max)\n",
|
||||
|
|
|
|||
|
|
@ -1014,7 +1014,6 @@ repeat:
|
|||
|
||||
/* Primary is full, try the secondary */
|
||||
if (unlikely(slot == -1)) {
|
||||
new_pte |= _PAGE_F_SECOND;
|
||||
hpte_group = ((~hash & htab_hash_mask) *
|
||||
HPTES_PER_GROUP) & ~0x7UL;
|
||||
slot = ppc_md.hpte_insert(hpte_group, va, pa, rflags,
|
||||
|
|
@ -1033,7 +1032,7 @@ repeat:
|
|||
if (unlikely(slot == -2))
|
||||
panic("hash_huge_page: pte_insert failed\n");
|
||||
|
||||
new_pte |= (slot << 12) & _PAGE_F_GIX;
|
||||
new_pte |= (slot << 12) & (_PAGE_F_SECOND | _PAGE_F_GIX);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -61,10 +61,6 @@ unsigned long memory_limit;
|
|||
extern void hash_preload(struct mm_struct *mm, unsigned long ea,
|
||||
unsigned long access, unsigned long trap);
|
||||
|
||||
/*
|
||||
* This is called by /dev/mem to know if a given address has to
|
||||
* be mapped non-cacheable or not
|
||||
*/
|
||||
int page_is_ram(unsigned long pfn)
|
||||
{
|
||||
unsigned long paddr = (pfn << PAGE_SHIFT);
|
||||
|
|
@ -490,19 +486,19 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
|
|||
!cpu_has_feature(CPU_FTR_NOEXECUTE) &&
|
||||
pfn_valid(pfn)) {
|
||||
struct page *page = pfn_to_page(pfn);
|
||||
#ifdef CONFIG_8xx
|
||||
/* On 8xx, cache control instructions (particularly
|
||||
* "dcbst" from flush_dcache_icache) fault as write
|
||||
* operation if there is an unpopulated TLB entry
|
||||
* for the address in question. To workaround that,
|
||||
* we invalidate the TLB here, thus avoiding dcbst
|
||||
* misbehaviour.
|
||||
*/
|
||||
_tlbie(address);
|
||||
#endif
|
||||
if (!PageReserved(page)
|
||||
&& !test_bit(PG_arch_1, &page->flags)) {
|
||||
if (vma->vm_mm == current->active_mm) {
|
||||
#ifdef CONFIG_8xx
|
||||
/* On 8xx, cache control instructions (particularly
|
||||
* "dcbst" from flush_dcache_icache) fault as write
|
||||
* operation if there is an unpopulated TLB entry
|
||||
* for the address in question. To workaround that,
|
||||
* we invalidate the TLB here, thus avoiding dcbst
|
||||
* misbehaviour.
|
||||
*/
|
||||
_tlbie(address);
|
||||
#endif
|
||||
__flush_dcache_icache((void *) address);
|
||||
} else
|
||||
flush_dcache_icache_page(page);
|
||||
|
|
|
|||
|
|
@ -294,11 +294,8 @@ void __init mapin_ram(void)
|
|||
}
|
||||
}
|
||||
|
||||
/* is x a power of 2? */
|
||||
#define is_power_of_2(x) ((x) != 0 && (((x) & ((x) - 1)) == 0))
|
||||
|
||||
/* is x a power of 4? */
|
||||
#define is_power_of_4(x) ((x) != 0 && (((x) & (x-1)) == 0) && (ffs(x) & 1))
|
||||
#define is_power_of_4(x) is_power_of_2(x) && (ffs(x) & 1))
|
||||
|
||||
/*
|
||||
* Set up a mapping for a block of I/O.
|
||||
|
|
|
|||
|
|
@ -149,6 +149,8 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
|
|||
#ifdef CONFIG_PPC64
|
||||
#ifdef CONFIG_PPC_CELL_NATIVE
|
||||
case PPC_OPROFILE_CELL:
|
||||
if (firmware_has_feature(FW_FEATURE_LPAR))
|
||||
return -ENODEV;
|
||||
model = &op_model_cell;
|
||||
break;
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -137,9 +137,9 @@ static void fsl7450_start(struct op_counter_config *ctr)
|
|||
|
||||
for (i = 0; i < NUM_CTRS; ++i) {
|
||||
if (ctr[i].enabled)
|
||||
ctr_write(i, reset_value[i]);
|
||||
classic_ctr_write(i, reset_value[i]);
|
||||
else
|
||||
ctr_write(i, 0);
|
||||
classic_ctr_write(i, 0);
|
||||
}
|
||||
|
||||
/* Clear the freeze bit, and enable the interrupt.
|
||||
|
|
@ -179,13 +179,13 @@ static void fsl7450_handle_interrupt(struct pt_regs *regs,
|
|||
is_kernel = is_kernel_addr(pc);
|
||||
|
||||
for (i = 0; i < NUM_CTRS; ++i) {
|
||||
val = ctr_read(i);
|
||||
val = classic_ctr_read(i);
|
||||
if (val < 0) {
|
||||
if (oprofile_running && ctr[i].enabled) {
|
||||
oprofile_add_ext_sample(pc, regs, i, is_kernel);
|
||||
ctr_write(i, reset_value[i]);
|
||||
classic_ctr_write(i, reset_value[i]);
|
||||
} else {
|
||||
ctr_write(i, 0);
|
||||
classic_ctr_write(i, 0);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -32,6 +32,87 @@ static unsigned long reset_value[OP_MAX_COUNTER];
|
|||
static int num_counters;
|
||||
static int oprofile_running;
|
||||
|
||||
static inline u32 get_pmlca(int ctr)
|
||||
{
|
||||
u32 pmlca;
|
||||
|
||||
switch (ctr) {
|
||||
case 0:
|
||||
pmlca = mfpmr(PMRN_PMLCA0);
|
||||
break;
|
||||
case 1:
|
||||
pmlca = mfpmr(PMRN_PMLCA1);
|
||||
break;
|
||||
case 2:
|
||||
pmlca = mfpmr(PMRN_PMLCA2);
|
||||
break;
|
||||
case 3:
|
||||
pmlca = mfpmr(PMRN_PMLCA3);
|
||||
break;
|
||||
default:
|
||||
panic("Bad ctr number\n");
|
||||
}
|
||||
|
||||
return pmlca;
|
||||
}
|
||||
|
||||
static inline void set_pmlca(int ctr, u32 pmlca)
|
||||
{
|
||||
switch (ctr) {
|
||||
case 0:
|
||||
mtpmr(PMRN_PMLCA0, pmlca);
|
||||
break;
|
||||
case 1:
|
||||
mtpmr(PMRN_PMLCA1, pmlca);
|
||||
break;
|
||||
case 2:
|
||||
mtpmr(PMRN_PMLCA2, pmlca);
|
||||
break;
|
||||
case 3:
|
||||
mtpmr(PMRN_PMLCA3, pmlca);
|
||||
break;
|
||||
default:
|
||||
panic("Bad ctr number\n");
|
||||
}
|
||||
}
|
||||
|
||||
static inline unsigned int ctr_read(unsigned int i)
|
||||
{
|
||||
switch(i) {
|
||||
case 0:
|
||||
return mfpmr(PMRN_PMC0);
|
||||
case 1:
|
||||
return mfpmr(PMRN_PMC1);
|
||||
case 2:
|
||||
return mfpmr(PMRN_PMC2);
|
||||
case 3:
|
||||
return mfpmr(PMRN_PMC3);
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
static inline void ctr_write(unsigned int i, unsigned int val)
|
||||
{
|
||||
switch(i) {
|
||||
case 0:
|
||||
mtpmr(PMRN_PMC0, val);
|
||||
break;
|
||||
case 1:
|
||||
mtpmr(PMRN_PMC1, val);
|
||||
break;
|
||||
case 2:
|
||||
mtpmr(PMRN_PMC2, val);
|
||||
break;
|
||||
case 3:
|
||||
mtpmr(PMRN_PMC3, val);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static void init_pmc_stop(int ctr)
|
||||
{
|
||||
u32 pmlca = (PMLCA_FC | PMLCA_FCS | PMLCA_FCU |
|
||||
|
|
|
|||
|
|
@ -121,9 +121,9 @@ static void power4_start(struct op_counter_config *ctr)
|
|||
|
||||
for (i = 0; i < cur_cpu_spec->num_pmcs; ++i) {
|
||||
if (ctr[i].enabled) {
|
||||
ctr_write(i, reset_value[i]);
|
||||
classic_ctr_write(i, reset_value[i]);
|
||||
} else {
|
||||
ctr_write(i, 0);
|
||||
classic_ctr_write(i, 0);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -254,13 +254,13 @@ static void power4_handle_interrupt(struct pt_regs *regs,
|
|||
mtmsrd(mfmsr() | MSR_PMM);
|
||||
|
||||
for (i = 0; i < cur_cpu_spec->num_pmcs; ++i) {
|
||||
val = ctr_read(i);
|
||||
val = classic_ctr_read(i);
|
||||
if (val < 0) {
|
||||
if (oprofile_running && ctr[i].enabled) {
|
||||
oprofile_add_ext_sample(pc, regs, i, is_kernel);
|
||||
ctr_write(i, reset_value[i]);
|
||||
classic_ctr_write(i, reset_value[i]);
|
||||
} else {
|
||||
ctr_write(i, 0);
|
||||
classic_ctr_write(i, 0);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -137,10 +137,10 @@ static void rs64_start(struct op_counter_config *ctr)
|
|||
|
||||
for (i = 0; i < num_counters; ++i) {
|
||||
if (ctr[i].enabled) {
|
||||
ctr_write(i, reset_value[i]);
|
||||
classic_ctr_write(i, reset_value[i]);
|
||||
ctrl_write(i, ctr[i].event);
|
||||
} else {
|
||||
ctr_write(i, 0);
|
||||
classic_ctr_write(i, 0);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -186,13 +186,13 @@ static void rs64_handle_interrupt(struct pt_regs *regs,
|
|||
mtmsrd(mfmsr() | MSR_PMM);
|
||||
|
||||
for (i = 0; i < num_counters; ++i) {
|
||||
val = ctr_read(i);
|
||||
val = classic_ctr_read(i);
|
||||
if (val < 0) {
|
||||
if (ctr[i].enabled) {
|
||||
oprofile_add_ext_sample(pc, regs, i, is_kernel);
|
||||
ctr_write(i, reset_value[i]);
|
||||
classic_ctr_write(i, reset_value[i]);
|
||||
} else {
|
||||
ctr_write(i, 0);
|
||||
classic_ctr_write(i, 0);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -3,6 +3,7 @@
|
|||
#
|
||||
ifeq ($(CONFIG_PPC_MERGE),y)
|
||||
obj-y += mpc52xx_pic.o mpc52xx_common.o
|
||||
obj-$(CONFIG_PCI) += mpc52xx_pci.o
|
||||
endif
|
||||
|
||||
obj-$(CONFIG_PPC_EFIKA) += efika-setup.o efika-pci.o
|
||||
|
|
|
|||
|
|
@ -107,6 +107,12 @@ static void __init lite52xx_setup_arch(void)
|
|||
mpc52xx_setup_cpu(); /* Generic */
|
||||
lite52xx_setup_cpu(); /* Platorm specific */
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
np = of_find_node_by_type(np, "pci");
|
||||
if (np)
|
||||
mpc52xx_add_bridge(np);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_BLK_DEV_INITRD
|
||||
if (initrd_start)
|
||||
ROOT_DEV = Root_RAM0;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,412 @@
|
|||
/*
|
||||
* PCI code for the Freescale MPC52xx embedded CPU.
|
||||
*
|
||||
* Copyright (C) 2006 Secret Lab Technologies Ltd.
|
||||
* Grant Likely <grant.likely@secretlab.ca>
|
||||
* Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#undef DEBUG
|
||||
|
||||
#include <asm/pci.h>
|
||||
#include <asm/mpc52xx.h>
|
||||
#include <asm/delay.h>
|
||||
#include <asm/machdep.h>
|
||||
#include <linux/kernel.h>
|
||||
|
||||
|
||||
/* ======================================================================== */
|
||||
/* PCI windows config */
|
||||
/* ======================================================================== */
|
||||
|
||||
#define MPC52xx_PCI_TARGET_IO 0xf0000000
|
||||
#define MPC52xx_PCI_TARGET_MEM 0x00000000
|
||||
|
||||
|
||||
/* ======================================================================== */
|
||||
/* Structures mapping & Defines for PCI Unit */
|
||||
/* ======================================================================== */
|
||||
|
||||
#define MPC52xx_PCI_GSCR_BM 0x40000000
|
||||
#define MPC52xx_PCI_GSCR_PE 0x20000000
|
||||
#define MPC52xx_PCI_GSCR_SE 0x10000000
|
||||
#define MPC52xx_PCI_GSCR_XLB2PCI_MASK 0x07000000
|
||||
#define MPC52xx_PCI_GSCR_XLB2PCI_SHIFT 24
|
||||
#define MPC52xx_PCI_GSCR_IPG2PCI_MASK 0x00070000
|
||||
#define MPC52xx_PCI_GSCR_IPG2PCI_SHIFT 16
|
||||
#define MPC52xx_PCI_GSCR_BME 0x00004000
|
||||
#define MPC52xx_PCI_GSCR_PEE 0x00002000
|
||||
#define MPC52xx_PCI_GSCR_SEE 0x00001000
|
||||
#define MPC52xx_PCI_GSCR_PR 0x00000001
|
||||
|
||||
|
||||
#define MPC52xx_PCI_IWBTAR_TRANSLATION(proc_ad,pci_ad,size) \
|
||||
( ( (proc_ad) & 0xff000000 ) | \
|
||||
( (((size) - 1) >> 8) & 0x00ff0000 ) | \
|
||||
( ((pci_ad) >> 16) & 0x0000ff00 ) )
|
||||
|
||||
#define MPC52xx_PCI_IWCR_PACK(win0,win1,win2) (((win0) << 24) | \
|
||||
((win1) << 16) | \
|
||||
((win2) << 8))
|
||||
|
||||
#define MPC52xx_PCI_IWCR_DISABLE 0x0
|
||||
#define MPC52xx_PCI_IWCR_ENABLE 0x1
|
||||
#define MPC52xx_PCI_IWCR_READ 0x0
|
||||
#define MPC52xx_PCI_IWCR_READ_LINE 0x2
|
||||
#define MPC52xx_PCI_IWCR_READ_MULTI 0x4
|
||||
#define MPC52xx_PCI_IWCR_MEM 0x0
|
||||
#define MPC52xx_PCI_IWCR_IO 0x8
|
||||
|
||||
#define MPC52xx_PCI_TCR_P 0x01000000
|
||||
#define MPC52xx_PCI_TCR_LD 0x00010000
|
||||
|
||||
#define MPC52xx_PCI_TBATR_DISABLE 0x0
|
||||
#define MPC52xx_PCI_TBATR_ENABLE 0x1
|
||||
|
||||
struct mpc52xx_pci {
|
||||
u32 idr; /* PCI + 0x00 */
|
||||
u32 scr; /* PCI + 0x04 */
|
||||
u32 ccrir; /* PCI + 0x08 */
|
||||
u32 cr1; /* PCI + 0x0C */
|
||||
u32 bar0; /* PCI + 0x10 */
|
||||
u32 bar1; /* PCI + 0x14 */
|
||||
u8 reserved1[16]; /* PCI + 0x18 */
|
||||
u32 ccpr; /* PCI + 0x28 */
|
||||
u32 sid; /* PCI + 0x2C */
|
||||
u32 erbar; /* PCI + 0x30 */
|
||||
u32 cpr; /* PCI + 0x34 */
|
||||
u8 reserved2[4]; /* PCI + 0x38 */
|
||||
u32 cr2; /* PCI + 0x3C */
|
||||
u8 reserved3[32]; /* PCI + 0x40 */
|
||||
u32 gscr; /* PCI + 0x60 */
|
||||
u32 tbatr0; /* PCI + 0x64 */
|
||||
u32 tbatr1; /* PCI + 0x68 */
|
||||
u32 tcr; /* PCI + 0x6C */
|
||||
u32 iw0btar; /* PCI + 0x70 */
|
||||
u32 iw1btar; /* PCI + 0x74 */
|
||||
u32 iw2btar; /* PCI + 0x78 */
|
||||
u8 reserved4[4]; /* PCI + 0x7C */
|
||||
u32 iwcr; /* PCI + 0x80 */
|
||||
u32 icr; /* PCI + 0x84 */
|
||||
u32 isr; /* PCI + 0x88 */
|
||||
u32 arb; /* PCI + 0x8C */
|
||||
u8 reserved5[104]; /* PCI + 0x90 */
|
||||
u32 car; /* PCI + 0xF8 */
|
||||
u8 reserved6[4]; /* PCI + 0xFC */
|
||||
};
|
||||
|
||||
|
||||
/* ======================================================================== */
|
||||
/* PCI configuration acess */
|
||||
/* ======================================================================== */
|
||||
|
||||
static int
|
||||
mpc52xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
|
||||
int offset, int len, u32 *val)
|
||||
{
|
||||
struct pci_controller *hose = bus->sysdata;
|
||||
u32 value;
|
||||
|
||||
if (ppc_md.pci_exclude_device)
|
||||
if (ppc_md.pci_exclude_device(bus->number, devfn))
|
||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
|
||||
out_be32(hose->cfg_addr,
|
||||
(1 << 31) |
|
||||
((bus->number - hose->bus_offset) << 16) |
|
||||
(devfn << 8) |
|
||||
(offset & 0xfc));
|
||||
mb();
|
||||
|
||||
#if defined(CONFIG_PPC_MPC5200_BUGFIX)
|
||||
if (bus->number != hose->bus_offset) {
|
||||
/* workaround for the bug 435 of the MPC5200 (L25R);
|
||||
* Don't do 32 bits config access during type-1 cycles */
|
||||
switch (len) {
|
||||
case 1:
|
||||
value = in_8(((u8 __iomem *)hose->cfg_data) +
|
||||
(offset & 3));
|
||||
break;
|
||||
case 2:
|
||||
value = in_le16(((u16 __iomem *)hose->cfg_data) +
|
||||
((offset>>1) & 1));
|
||||
break;
|
||||
|
||||
default:
|
||||
value = in_le16((u16 __iomem *)hose->cfg_data) |
|
||||
(in_le16(((u16 __iomem *)hose->cfg_data) + 1) << 16);
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
#endif
|
||||
{
|
||||
value = in_le32(hose->cfg_data);
|
||||
|
||||
if (len != 4) {
|
||||
value >>= ((offset & 0x3) << 3);
|
||||
value &= 0xffffffff >> (32 - (len << 3));
|
||||
}
|
||||
}
|
||||
|
||||
*val = value;
|
||||
|
||||
out_be32(hose->cfg_addr, 0);
|
||||
mb();
|
||||
|
||||
return PCIBIOS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
static int
|
||||
mpc52xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
|
||||
int offset, int len, u32 val)
|
||||
{
|
||||
struct pci_controller *hose = bus->sysdata;
|
||||
u32 value, mask;
|
||||
|
||||
if (ppc_md.pci_exclude_device)
|
||||
if (ppc_md.pci_exclude_device(bus->number, devfn))
|
||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
|
||||
out_be32(hose->cfg_addr,
|
||||
(1 << 31) |
|
||||
((bus->number - hose->bus_offset) << 16) |
|
||||
(devfn << 8) |
|
||||
(offset & 0xfc));
|
||||
mb();
|
||||
|
||||
#if defined(CONFIG_PPC_MPC5200_BUGFIX)
|
||||
if (bus->number != hose->bus_offset) {
|
||||
/* workaround for the bug 435 of the MPC5200 (L25R);
|
||||
* Don't do 32 bits config access during type-1 cycles */
|
||||
switch (len) {
|
||||
case 1:
|
||||
out_8(((u8 __iomem *)hose->cfg_data) +
|
||||
(offset & 3), val);
|
||||
break;
|
||||
case 2:
|
||||
out_le16(((u16 __iomem *)hose->cfg_data) +
|
||||
((offset>>1) & 1), val);
|
||||
break;
|
||||
|
||||
default:
|
||||
out_le16((u16 __iomem *)hose->cfg_data,
|
||||
(u16)val);
|
||||
out_le16(((u16 __iomem *)hose->cfg_data) + 1,
|
||||
(u16)(val>>16));
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
#endif
|
||||
{
|
||||
if (len != 4) {
|
||||
value = in_le32(hose->cfg_data);
|
||||
|
||||
offset = (offset & 0x3) << 3;
|
||||
mask = (0xffffffff >> (32 - (len << 3)));
|
||||
mask <<= offset;
|
||||
|
||||
value &= ~mask;
|
||||
val = value | ((val << offset) & mask);
|
||||
}
|
||||
|
||||
out_le32(hose->cfg_data, val);
|
||||
}
|
||||
mb();
|
||||
|
||||
out_be32(hose->cfg_addr, 0);
|
||||
mb();
|
||||
|
||||
return PCIBIOS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
static struct pci_ops mpc52xx_pci_ops = {
|
||||
.read = mpc52xx_pci_read_config,
|
||||
.write = mpc52xx_pci_write_config
|
||||
};
|
||||
|
||||
|
||||
/* ======================================================================== */
|
||||
/* PCI setup */
|
||||
/* ======================================================================== */
|
||||
|
||||
static void __init
|
||||
mpc52xx_pci_setup(struct pci_controller *hose,
|
||||
struct mpc52xx_pci __iomem *pci_regs)
|
||||
{
|
||||
struct resource *res;
|
||||
u32 tmp;
|
||||
int iwcr0 = 0, iwcr1 = 0, iwcr2 = 0;
|
||||
|
||||
pr_debug("mpc52xx_pci_setup(hose=%p, pci_regs=%p)\n", hose, pci_regs);
|
||||
|
||||
/* pci_process_bridge_OF_ranges() found all our addresses for us;
|
||||
* now store them in the right places */
|
||||
hose->cfg_addr = &pci_regs->car;
|
||||
hose->cfg_data = hose->io_base_virt;
|
||||
|
||||
/* Control regs */
|
||||
tmp = in_be32(&pci_regs->scr);
|
||||
tmp |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
|
||||
out_be32(&pci_regs->scr, tmp);
|
||||
|
||||
/* Memory windows */
|
||||
res = &hose->mem_resources[0];
|
||||
if (res->flags) {
|
||||
pr_debug("mem_resource[0] = {.start=%x, .end=%x, .flags=%lx}\n",
|
||||
res->start, res->end, res->flags);
|
||||
out_be32(&pci_regs->iw0btar,
|
||||
MPC52xx_PCI_IWBTAR_TRANSLATION(res->start, res->start,
|
||||
res->end - res->start + 1));
|
||||
iwcr0 = MPC52xx_PCI_IWCR_ENABLE | MPC52xx_PCI_IWCR_MEM;
|
||||
if (res->flags & IORESOURCE_PREFETCH)
|
||||
iwcr0 |= MPC52xx_PCI_IWCR_READ_MULTI;
|
||||
else
|
||||
iwcr0 |= MPC52xx_PCI_IWCR_READ;
|
||||
}
|
||||
|
||||
res = &hose->mem_resources[1];
|
||||
if (res->flags) {
|
||||
pr_debug("mem_resource[1] = {.start=%x, .end=%x, .flags=%lx}\n",
|
||||
res->start, res->end, res->flags);
|
||||
out_be32(&pci_regs->iw1btar,
|
||||
MPC52xx_PCI_IWBTAR_TRANSLATION(res->start, res->start,
|
||||
res->end - res->start + 1));
|
||||
iwcr1 = MPC52xx_PCI_IWCR_ENABLE | MPC52xx_PCI_IWCR_MEM;
|
||||
if (res->flags & IORESOURCE_PREFETCH)
|
||||
iwcr1 |= MPC52xx_PCI_IWCR_READ_MULTI;
|
||||
else
|
||||
iwcr1 |= MPC52xx_PCI_IWCR_READ;
|
||||
}
|
||||
|
||||
/* IO resources */
|
||||
res = &hose->io_resource;
|
||||
if (!res) {
|
||||
printk(KERN_ERR "%s: Didn't find IO resources\n", __FILE__);
|
||||
return;
|
||||
}
|
||||
pr_debug(".io_resource={.start=%x,.end=%x,.flags=%lx} "
|
||||
".io_base_phys=0x%p\n",
|
||||
res->start, res->end, res->flags, (void*)hose->io_base_phys);
|
||||
out_be32(&pci_regs->iw2btar,
|
||||
MPC52xx_PCI_IWBTAR_TRANSLATION(hose->io_base_phys,
|
||||
res->start,
|
||||
res->end - res->start + 1));
|
||||
iwcr2 = MPC52xx_PCI_IWCR_ENABLE | MPC52xx_PCI_IWCR_IO;
|
||||
|
||||
/* Set all the IWCR fields at once; they're in the same reg */
|
||||
out_be32(&pci_regs->iwcr, MPC52xx_PCI_IWCR_PACK(iwcr0, iwcr1, iwcr2));
|
||||
|
||||
out_be32(&pci_regs->tbatr0,
|
||||
MPC52xx_PCI_TBATR_ENABLE | MPC52xx_PCI_TARGET_IO );
|
||||
out_be32(&pci_regs->tbatr1,
|
||||
MPC52xx_PCI_TBATR_ENABLE | MPC52xx_PCI_TARGET_MEM );
|
||||
|
||||
out_be32(&pci_regs->tcr, MPC52xx_PCI_TCR_LD);
|
||||
|
||||
tmp = in_be32(&pci_regs->gscr);
|
||||
#if 0
|
||||
/* Reset the exteral bus ( internal PCI controller is NOT resetted ) */
|
||||
/* Not necessary and can be a bad thing if for example the bootloader
|
||||
is displaying a splash screen or ... Just left here for
|
||||
documentation purpose if anyone need it */
|
||||
out_be32(&pci_regs->gscr, tmp | MPC52xx_PCI_GSCR_PR);
|
||||
udelay(50);
|
||||
#endif
|
||||
|
||||
/* Make sure the PCI bridge is out of reset */
|
||||
out_be32(&pci_regs->gscr, tmp & ~MPC52xx_PCI_GSCR_PR);
|
||||
}
|
||||
|
||||
static void
|
||||
mpc52xx_pci_fixup_resources(struct pci_dev *dev)
|
||||
{
|
||||
int i;
|
||||
|
||||
pr_debug("mpc52xx_pci_fixup_resources() %.4x:%.4x\n",
|
||||
dev->vendor, dev->device);
|
||||
|
||||
/* We don't rely on boot loader for PCI and resets all
|
||||
devices */
|
||||
for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
|
||||
struct resource *res = &dev->resource[i];
|
||||
if (res->end > res->start) { /* Only valid resources */
|
||||
res->end -= res->start;
|
||||
res->start = 0;
|
||||
res->flags |= IORESOURCE_UNSET;
|
||||
}
|
||||
}
|
||||
|
||||
/* The PCI Host bridge of MPC52xx has a prefetch memory resource
|
||||
fixed to 1Gb. Doesn't fit in the resource system so we remove it */
|
||||
if ( (dev->vendor == PCI_VENDOR_ID_MOTOROLA) &&
|
||||
( dev->device == PCI_DEVICE_ID_MOTOROLA_MPC5200
|
||||
|| dev->device == PCI_DEVICE_ID_MOTOROLA_MPC5200B) ) {
|
||||
struct resource *res = &dev->resource[1];
|
||||
res->start = res->end = res->flags = 0;
|
||||
}
|
||||
}
|
||||
|
||||
int __init
|
||||
mpc52xx_add_bridge(struct device_node *node)
|
||||
{
|
||||
int len;
|
||||
struct mpc52xx_pci __iomem *pci_regs;
|
||||
struct pci_controller *hose;
|
||||
const int *bus_range;
|
||||
struct resource rsrc;
|
||||
|
||||
pr_debug("Adding MPC52xx PCI host bridge %s\n", node->full_name);
|
||||
|
||||
pci_assign_all_buses = 1;
|
||||
|
||||
if (of_address_to_resource(node, 0, &rsrc) != 0) {
|
||||
printk(KERN_ERR "Can't get %s resources\n", node->full_name);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
bus_range = get_property(node, "bus-range", &len);
|
||||
if (bus_range == NULL || len < 2 * sizeof(int)) {
|
||||
printk(KERN_WARNING "Can't get %s bus-range, assume bus 0\n",
|
||||
node->full_name);
|
||||
bus_range = NULL;
|
||||
}
|
||||
|
||||
/* There are some PCI quirks on the 52xx, register the hook to
|
||||
* fix them. */
|
||||
ppc_md.pcibios_fixup_resources = mpc52xx_pci_fixup_resources;
|
||||
|
||||
/* Alloc and initialize the pci controller. Values in the device
|
||||
* tree are needed to configure the 52xx PCI controller. Rather
|
||||
* than parse the tree here, let pci_process_bridge_OF_ranges()
|
||||
* do it for us and extract the values after the fact */
|
||||
hose = pcibios_alloc_controller();
|
||||
if (!hose)
|
||||
return -ENOMEM;
|
||||
|
||||
hose->arch_data = node;
|
||||
hose->set_cfg_type = 1;
|
||||
|
||||
hose->first_busno = bus_range ? bus_range[0] : 0;
|
||||
hose->last_busno = bus_range ? bus_range[1] : 0xff;
|
||||
|
||||
hose->bus_offset = 0;
|
||||
hose->ops = &mpc52xx_pci_ops;
|
||||
|
||||
pci_regs = ioremap(rsrc.start, rsrc.end - rsrc.start + 1);
|
||||
if (!pci_regs)
|
||||
return -ENOMEM;
|
||||
|
||||
pci_process_bridge_OF_ranges(hose, node, 1);
|
||||
|
||||
/* Finish setting up PCI using values obtained by
|
||||
* pci_proces_bridge_OF_ranges */
|
||||
mpc52xx_pci_setup(hose, pci_regs);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -50,7 +50,7 @@
|
|||
#include <sysdev/fsl_soc.h>
|
||||
#include <sysdev/cpm2_pic.h>
|
||||
|
||||
#include "pq2ads_pd.h"
|
||||
#include "pq2ads.h"
|
||||
|
||||
static int __init get_freq(char *name, unsigned long *val)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -51,7 +51,7 @@
|
|||
#include <sysdev/fsl_soc.h>
|
||||
#include <../sysdev/cpm2_pic.h>
|
||||
|
||||
#include "pq2ads_pd.h"
|
||||
#include "pq2ads.h"
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
static uint pci_clk_frq;
|
||||
|
|
|
|||
|
|
@ -22,6 +22,7 @@
|
|||
#ifndef __MACH_ADS8260_DEFS
|
||||
#define __MACH_ADS8260_DEFS
|
||||
|
||||
#include <linux/seq_file.h>
|
||||
#include <asm/ppcboot.h>
|
||||
|
||||
/* For our show_cpuinfo hooks. */
|
||||
|
|
@ -46,12 +47,12 @@
|
|||
#define BCSR1_RS232_EN1 ((uint)0x02000000) /* 0 ==enable */
|
||||
#define BCSR1_RS232_EN2 ((uint)0x01000000) /* 0 ==enable */
|
||||
#define BCSR3_FETHIEN2 ((uint)0x10000000) /* 0 == enable*/
|
||||
#define BCSR3_FETH2_RS ((uint)0x80000000) /* 0 == reset */
|
||||
#define BCSR3_FETH2_RST ((uint)0x80000000) /* 0 == reset */
|
||||
|
||||
/* cpm serial driver works with constants below */
|
||||
|
||||
#define SIU_INT_SMC1 ((uint)0x04+CPM_IRQ_OFFSET)
|
||||
#define SIU_INT_SMC2i ((uint)0x05+CPM_IRQ_OFFSET)
|
||||
#define SIU_INT_SMC2 ((uint)0x05+CPM_IRQ_OFFSET)
|
||||
#define SIU_INT_SCC1 ((uint)0x28+CPM_IRQ_OFFSET)
|
||||
#define SIU_INT_SCC2 ((uint)0x29+CPM_IRQ_OFFSET)
|
||||
#define SIU_INT_SCC3 ((uint)0x2a+CPM_IRQ_OFFSET)
|
||||
|
|
|
|||
|
|
@ -18,23 +18,36 @@
|
|||
|
||||
#include "mpc83xx.h"
|
||||
|
||||
static __be32 __iomem *restart_reg_base;
|
||||
|
||||
static int __init mpc83xx_restart_init(void)
|
||||
{
|
||||
/* map reset restart_reg_baseister space */
|
||||
restart_reg_base = ioremap(get_immrbase() + 0x900, 0xff);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
arch_initcall(mpc83xx_restart_init);
|
||||
|
||||
void mpc83xx_restart(char *cmd)
|
||||
{
|
||||
#define RST_OFFSET 0x00000900
|
||||
#define RST_PROT_REG 0x00000018
|
||||
#define RST_CTRL_REG 0x0000001c
|
||||
__be32 __iomem *reg;
|
||||
|
||||
/* map reset register space */
|
||||
reg = ioremap(get_immrbase() + 0x900, 0xff);
|
||||
|
||||
local_irq_disable();
|
||||
|
||||
/* enable software reset "RSTE" */
|
||||
out_be32(reg + (RST_PROT_REG >> 2), 0x52535445);
|
||||
if (restart_reg_base) {
|
||||
/* enable software reset "RSTE" */
|
||||
out_be32(restart_reg_base + (RST_PROT_REG >> 2), 0x52535445);
|
||||
|
||||
/* set software hard reset */
|
||||
out_be32(restart_reg_base + (RST_CTRL_REG >> 2), 0x2);
|
||||
} else {
|
||||
printk (KERN_EMERG "Error: Restart registers not mapped, spinning!\n");
|
||||
}
|
||||
|
||||
/* set software hard reset */
|
||||
out_be32(reg + (RST_CTRL_REG >> 2), 0x2);
|
||||
for (;;) ;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -25,6 +25,7 @@
|
|||
#include <linux/initrd.h>
|
||||
|
||||
#include <asm/of_device.h>
|
||||
#include <asm/of_platform.h>
|
||||
#include <asm/system.h>
|
||||
#include <asm/atomic.h>
|
||||
#include <asm/time.h>
|
||||
|
|
@ -153,7 +154,7 @@ static int __init mpc832x_declare_of_platform_devices(void)
|
|||
}
|
||||
device_initcall(mpc832x_declare_of_platform_devices);
|
||||
|
||||
void __init mpc832x_sys_init_IRQ(void)
|
||||
static void __init mpc832x_sys_init_IRQ(void)
|
||||
{
|
||||
|
||||
struct device_node *np;
|
||||
|
|
|
|||
|
|
@ -81,7 +81,7 @@ static void __init mpc834x_itx_setup_arch(void)
|
|||
#endif
|
||||
}
|
||||
|
||||
void __init mpc834x_itx_init_IRQ(void)
|
||||
static void __init mpc834x_itx_init_IRQ(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
|
||||
|
|
|
|||
|
|
@ -79,7 +79,7 @@ static void __init mpc834x_sys_setup_arch(void)
|
|||
#endif
|
||||
}
|
||||
|
||||
void __init mpc834x_sys_init_IRQ(void)
|
||||
static void __init mpc834x_sys_init_IRQ(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
|
||||
|
|
|
|||
|
|
@ -31,6 +31,7 @@
|
|||
#include <linux/initrd.h>
|
||||
|
||||
#include <asm/of_device.h>
|
||||
#include <asm/of_platform.h>
|
||||
#include <asm/system.h>
|
||||
#include <asm/atomic.h>
|
||||
#include <asm/time.h>
|
||||
|
|
@ -158,7 +159,7 @@ static int __init mpc8360_declare_of_platform_devices(void)
|
|||
}
|
||||
device_initcall(mpc8360_declare_of_platform_devices);
|
||||
|
||||
void __init mpc8360_sys_init_IRQ(void)
|
||||
static void __init mpc8360_sys_init_IRQ(void)
|
||||
{
|
||||
|
||||
struct device_node *np;
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@ choice
|
|||
config MPC8641_HPCN
|
||||
bool "Freescale MPC8641 HPCN"
|
||||
select PPC_I8259
|
||||
select DEFAULT_UIMAGE
|
||||
help
|
||||
This option enables support for the MPC8641 HPCN board.
|
||||
|
||||
|
|
|
|||
|
|
@ -65,7 +65,6 @@ smp_86xx_kick_cpu(int nr)
|
|||
pr_debug("smp_86xx_kick_cpu: kick CPU #%d\n", nr);
|
||||
|
||||
local_irq_save(flags);
|
||||
local_irq_disable();
|
||||
|
||||
/* Save reset vector */
|
||||
save_vector = *vector;
|
||||
|
|
|
|||
|
|
@ -1,105 +1,16 @@
|
|||
menu "Platform support"
|
||||
depends on PPC_8xx
|
||||
|
||||
config FADS
|
||||
bool
|
||||
|
||||
config CPM1
|
||||
bool
|
||||
|
||||
choice
|
||||
prompt "8xx Machine Type"
|
||||
depends on 8xx
|
||||
default RPXLITE
|
||||
|
||||
config RPXLITE
|
||||
bool "RPX-Lite"
|
||||
---help---
|
||||
Single-board computers based around the PowerPC MPC8xx chips and
|
||||
intended for embedded applications. The following types are
|
||||
supported:
|
||||
|
||||
RPX-Lite:
|
||||
Embedded Planet RPX Lite. PC104 form-factor SBC based on the MPC823.
|
||||
|
||||
RPX-Classic:
|
||||
Embedded Planet RPX Classic Low-fat. Credit-card-size SBC based on
|
||||
the MPC 860
|
||||
|
||||
BSE-IP:
|
||||
Bright Star Engineering ip-Engine.
|
||||
|
||||
TQM823L:
|
||||
TQM850L:
|
||||
TQM855L:
|
||||
TQM860L:
|
||||
MPC8xx based family of mini modules, half credit card size,
|
||||
up to 64 MB of RAM, 8 MB Flash, (Fast) Ethernet, 2 x serial ports,
|
||||
2 x CAN bus interface, ...
|
||||
Manufacturer: TQ Components, www.tq-group.de
|
||||
Date of Release: October (?) 1999
|
||||
End of Life: not yet :-)
|
||||
URL:
|
||||
- module: <http://www.denx.de/PDF/TQM8xxLHWM201.pdf>
|
||||
- starter kit: <http://www.denx.de/PDF/STK8xxLHWM201.pdf>
|
||||
- images: <http://www.denx.de/embedded-ppc-en.html>
|
||||
|
||||
FPS850L:
|
||||
FingerPrint Sensor System (based on TQM850L)
|
||||
Manufacturer: IKENDI AG, <http://www.ikendi.com/>
|
||||
Date of Release: November 1999
|
||||
End of life: end 2000 ?
|
||||
URL: see TQM850L
|
||||
|
||||
IVMS8:
|
||||
MPC860 based board used in the "Integrated Voice Mail System",
|
||||
Small Version (8 voice channels)
|
||||
Manufacturer: Speech Design, <http://www.speech-design.de/>
|
||||
Date of Release: December 2000 (?)
|
||||
End of life: -
|
||||
URL: <http://www.speech-design.de/>
|
||||
|
||||
IVML24:
|
||||
MPC860 based board used in the "Integrated Voice Mail System",
|
||||
Large Version (24 voice channels)
|
||||
Manufacturer: Speech Design, <http://www.speech-design.de/>
|
||||
Date of Release: March 2001 (?)
|
||||
End of life: -
|
||||
URL: <http://www.speech-design.de/>
|
||||
|
||||
HERMES:
|
||||
Hermes-Pro ISDN/LAN router with integrated 8 x hub
|
||||
Manufacturer: Multidata Gesellschaft fur Datentechnik und Informatik
|
||||
<http://www.multidata.de/>
|
||||
Date of Release: 2000 (?)
|
||||
End of life: -
|
||||
URL: <http://www.multidata.de/english/products/hpro.htm>
|
||||
|
||||
IP860:
|
||||
VMEBus IP (Industry Pack) carrier board with MPC860
|
||||
Manufacturer: MicroSys GmbH, <http://www.microsys.de/>
|
||||
Date of Release: ?
|
||||
End of life: -
|
||||
URL: <http://www.microsys.de/html/ip860.html>
|
||||
|
||||
PCU_E:
|
||||
PCU = Peripheral Controller Unit, Extended
|
||||
Manufacturer: Siemens AG, ICN (Information and Communication Networks)
|
||||
<http://www.siemens.de/page/1,3771,224315-1-999_2_226207-0,00.html>
|
||||
Date of Release: April 2001
|
||||
End of life: August 2001
|
||||
URL: n. a.
|
||||
|
||||
config RPXCLASSIC
|
||||
bool "RPX-Classic"
|
||||
help
|
||||
The RPX-Classic is a single-board computer based on the Motorola
|
||||
MPC860. It features 16MB of DRAM and a variable amount of flash,
|
||||
I2C EEPROM, thermal monitoring, a PCMCIA slot, a DIP switch and two
|
||||
LEDs. Variants with Ethernet ports exist. Say Y here to support it
|
||||
directly.
|
||||
|
||||
config BSEIP
|
||||
bool "BSE-IP"
|
||||
help
|
||||
Say Y here to support the Bright Star Engineering ipEngine SBC.
|
||||
This is a credit-card-sized device featuring a MPC823 processor,
|
||||
26MB DRAM, 4MB flash, Ethernet, a 16K-gate FPGA, USB, an LCD/video
|
||||
controller, and two RS232 ports.
|
||||
default MPC885ADS
|
||||
|
||||
config MPC8XXFADS
|
||||
bool "FADS"
|
||||
|
|
@ -107,111 +18,59 @@ config MPC8XXFADS
|
|||
|
||||
config MPC86XADS
|
||||
bool "MPC86XADS"
|
||||
select CPM1
|
||||
help
|
||||
MPC86x Application Development System by Freescale Semiconductor.
|
||||
The MPC86xADS is meant to serve as a platform for s/w and h/w
|
||||
development around the MPC86X processor families.
|
||||
select FADS
|
||||
|
||||
config MPC885ADS
|
||||
bool "MPC885ADS"
|
||||
select CPM1
|
||||
help
|
||||
Freescale Semiconductor MPC885 Application Development System (ADS).
|
||||
Also known as DUET.
|
||||
The MPC885ADS is meant to serve as a platform for s/w and h/w
|
||||
development around the MPC885 processor family.
|
||||
|
||||
config TQM823L
|
||||
bool "TQM823L"
|
||||
help
|
||||
Say Y here to support the TQM823L, one of an MPC8xx-based family of
|
||||
mini SBCs (half credit-card size) from TQ Components first released
|
||||
in late 1999. Technical references are at
|
||||
<http://www.denx.de/PDF/TQM8xxLHWM201.pdf>, and
|
||||
<http://www.denx.de/PDF/STK8xxLHWM201.pdf>, and an image at
|
||||
<http://www.denx.de/embedded-ppc-en.html>.
|
||||
|
||||
config TQM850L
|
||||
bool "TQM850L"
|
||||
help
|
||||
Say Y here to support the TQM850L, one of an MPC8xx-based family of
|
||||
mini SBCs (half credit-card size) from TQ Components first released
|
||||
in late 1999. Technical references are at
|
||||
<http://www.denx.de/PDF/TQM8xxLHWM201.pdf>, and
|
||||
<http://www.denx.de/PDF/STK8xxLHWM201.pdf>, and an image at
|
||||
<http://www.denx.de/embedded-ppc-en.html>.
|
||||
|
||||
config TQM855L
|
||||
bool "TQM855L"
|
||||
help
|
||||
Say Y here to support the TQM855L, one of an MPC8xx-based family of
|
||||
mini SBCs (half credit-card size) from TQ Components first released
|
||||
in late 1999. Technical references are at
|
||||
<http://www.denx.de/PDF/TQM8xxLHWM201.pdf>, and
|
||||
<http://www.denx.de/PDF/STK8xxLHWM201.pdf>, and an image at
|
||||
<http://www.denx.de/embedded-ppc-en.html>.
|
||||
|
||||
config TQM860L
|
||||
bool "TQM860L"
|
||||
help
|
||||
Say Y here to support the TQM860L, one of an MPC8xx-based family of
|
||||
mini SBCs (half credit-card size) from TQ Components first released
|
||||
in late 1999. Technical references are at
|
||||
<http://www.denx.de/PDF/TQM8xxLHWM201.pdf>, and
|
||||
<http://www.denx.de/PDF/STK8xxLHWM201.pdf>, and an image at
|
||||
<http://www.denx.de/embedded-ppc-en.html>.
|
||||
|
||||
config FPS850L
|
||||
bool "FPS850L"
|
||||
|
||||
config IVMS8
|
||||
bool "IVMS8"
|
||||
help
|
||||
Say Y here to support the Integrated Voice-Mail Small 8-channel SBC
|
||||
from Speech Design, released March 2001. The manufacturer's website
|
||||
is at <http://www.speech-design.de/>.
|
||||
|
||||
config IVML24
|
||||
bool "IVML24"
|
||||
help
|
||||
Say Y here to support the Integrated Voice-Mail Large 24-channel SBC
|
||||
from Speech Design, released March 2001. The manufacturer's website
|
||||
is at <http://www.speech-design.de/>.
|
||||
|
||||
config HERMES_PRO
|
||||
bool "HERMES"
|
||||
|
||||
config IP860
|
||||
bool "IP860"
|
||||
|
||||
config LWMON
|
||||
bool "LWMON"
|
||||
|
||||
config PCU_E
|
||||
bool "PCU_E"
|
||||
|
||||
config CCM
|
||||
bool "CCM"
|
||||
|
||||
config LANTEC
|
||||
bool "LANTEC"
|
||||
|
||||
config MBX
|
||||
bool "MBX"
|
||||
help
|
||||
MBX is a line of Motorola single-board computer based around the
|
||||
MPC821 and MPC860 processors, and intended for embedded-controller
|
||||
applications. Say Y here to support these boards directly.
|
||||
|
||||
config WINCEPT
|
||||
bool "WinCept"
|
||||
help
|
||||
The Wincept 100/110 is a Motorola single-board computer based on the
|
||||
MPC821 PowerPC, introduced in 1998 and designed to be used in
|
||||
thin-client machines. Say Y to support it directly.
|
||||
|
||||
endchoice
|
||||
|
||||
menu "Freescale Ethernet driver platform-specific options"
|
||||
depends on (FS_ENET && MPC885ADS)
|
||||
|
||||
config MPC8xx_SECOND_ETH
|
||||
bool "Second Ethernet channel"
|
||||
depends on MPC885ADS
|
||||
default y
|
||||
help
|
||||
This enables support for second Ethernet on MPC885ADS and MPC86xADS boards.
|
||||
The latter will use SCC1, for 885ADS you can select it below.
|
||||
|
||||
choice
|
||||
prompt "Second Ethernet channel"
|
||||
depends on MPC8xx_SECOND_ETH
|
||||
default MPC8xx_SECOND_ETH_FEC2
|
||||
|
||||
config MPC8xx_SECOND_ETH_FEC2
|
||||
bool "FEC2"
|
||||
depends on MPC885ADS
|
||||
help
|
||||
Enable FEC2 to serve as 2-nd Ethernet channel. Note that SMC2
|
||||
(often 2-nd UART) will not work if this is enabled.
|
||||
|
||||
config MPC8xx_SECOND_ETH_SCC3
|
||||
bool "SCC3"
|
||||
depends on MPC885ADS
|
||||
help
|
||||
Enable SCC3 to serve as 2-nd Ethernet channel. Note that SMC1
|
||||
(often 1-nd UART) will not work if this is enabled.
|
||||
|
||||
endchoice
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
|
||||
#
|
||||
# MPC8xx Communication options
|
||||
#
|
||||
|
|
@ -219,79 +78,6 @@ endchoice
|
|||
menu "MPC8xx CPM Options"
|
||||
depends on 8xx
|
||||
|
||||
config SCC_ENET
|
||||
bool "CPM SCC Ethernet"
|
||||
depends on NET_ETHERNET
|
||||
help
|
||||
Enable Ethernet support via the Motorola MPC8xx serial
|
||||
communications controller.
|
||||
|
||||
choice
|
||||
prompt "SCC used for Ethernet"
|
||||
depends on SCC_ENET
|
||||
default SCC1_ENET
|
||||
|
||||
config SCC1_ENET
|
||||
bool "SCC1"
|
||||
help
|
||||
Use MPC8xx serial communications controller 1 to drive Ethernet
|
||||
(default).
|
||||
|
||||
config SCC2_ENET
|
||||
bool "SCC2"
|
||||
help
|
||||
Use MPC8xx serial communications controller 2 to drive Ethernet.
|
||||
|
||||
config SCC3_ENET
|
||||
bool "SCC3"
|
||||
help
|
||||
Use MPC8xx serial communications controller 3 to drive Ethernet.
|
||||
|
||||
endchoice
|
||||
|
||||
config FEC_ENET
|
||||
bool "860T FEC Ethernet"
|
||||
depends on NET_ETHERNET
|
||||
help
|
||||
Enable Ethernet support via the Fast Ethernet Controller (FCC) on
|
||||
the Motorola MPC8260.
|
||||
|
||||
config USE_MDIO
|
||||
bool "Use MDIO for PHY configuration"
|
||||
depends on FEC_ENET
|
||||
help
|
||||
On some boards the hardware configuration of the ethernet PHY can be
|
||||
used without any software interaction over the MDIO interface, so
|
||||
all MII code can be omitted. Say N here if unsure or if you don't
|
||||
need link status reports.
|
||||
|
||||
config FEC_AM79C874
|
||||
bool "Support AMD79C874 PHY"
|
||||
depends on USE_MDIO
|
||||
|
||||
config FEC_LXT970
|
||||
bool "Support LXT970 PHY"
|
||||
depends on USE_MDIO
|
||||
|
||||
config FEC_LXT971
|
||||
bool "Support LXT971 PHY"
|
||||
depends on USE_MDIO
|
||||
|
||||
config FEC_QS6612
|
||||
bool "Support QS6612 PHY"
|
||||
depends on USE_MDIO
|
||||
|
||||
config ENET_BIG_BUFFERS
|
||||
bool "Use Big CPM Ethernet Buffers"
|
||||
depends on SCC_ENET || FEC_ENET
|
||||
help
|
||||
Allocate large buffers for MPC8xx Ethernet. Increases throughput
|
||||
and decreases the likelihood of dropped packets, but costs memory.
|
||||
|
||||
config HTDMSOUND
|
||||
bool "Embedded Planet HIOX Audio"
|
||||
depends on SOUND=y
|
||||
|
||||
# This doesn't really belong here, but it is convenient to ask
|
||||
# 8xx specific questions.
|
||||
comment "Generic MPC8xx Options"
|
||||
|
|
|
|||
|
|
@ -0,0 +1,6 @@
|
|||
#
|
||||
# Makefile for the PowerPC 8xx linux kernel.
|
||||
#
|
||||
obj-$(CONFIG_PPC_8xx) += m8xx_setup.o
|
||||
obj-$(CONFIG_MPC885ADS) += mpc885ads_setup.o
|
||||
obj-$(CONFIG_MPC86XADS) += mpc86xads_setup.o
|
||||
|
|
@ -0,0 +1,303 @@
|
|||
/*
|
||||
* Copyright (C) 1995 Linus Torvalds
|
||||
* Adapted from 'alpha' version by Gary Thomas
|
||||
* Modified by Cort Dougan (cort@cs.nmt.edu)
|
||||
* Modified for MBX using prep/chrp/pmac functions by Dan (dmalek@jlc.net)
|
||||
* Further modified for generic 8xx by Dan.
|
||||
*/
|
||||
|
||||
/*
|
||||
* bootup setup stuff..
|
||||
*/
|
||||
|
||||
#include <linux/errno.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/stddef.h>
|
||||
#include <linux/unistd.h>
|
||||
#include <linux/ptrace.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/user.h>
|
||||
#include <linux/a.out.h>
|
||||
#include <linux/tty.h>
|
||||
#include <linux/major.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/reboot.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/initrd.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/bootmem.h>
|
||||
#include <linux/seq_file.h>
|
||||
#include <linux/root_dev.h>
|
||||
#include <linux/time.h>
|
||||
#include <linux/rtc.h>
|
||||
|
||||
#include <asm/mmu.h>
|
||||
#include <asm/reg.h>
|
||||
#include <asm/residual.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/mpc8xx.h>
|
||||
#include <asm/8xx_immap.h>
|
||||
#include <asm/machdep.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/time.h>
|
||||
#include <asm/prom.h>
|
||||
#include <asm/fs_pd.h>
|
||||
#include <mm/mmu_decl.h>
|
||||
|
||||
#include "sysdev/mpc8xx_pic.h"
|
||||
|
||||
void m8xx_calibrate_decr(void);
|
||||
extern void m8xx_wdt_handler_install(bd_t *bp);
|
||||
extern int cpm_pic_init(void);
|
||||
extern int cpm_get_irq(void);
|
||||
|
||||
/* A place holder for time base interrupts, if they are ever enabled. */
|
||||
irqreturn_t timebase_interrupt(int irq, void * dev)
|
||||
{
|
||||
printk ("timebase_interrupt()\n");
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static struct irqaction tbint_irqaction = {
|
||||
.handler = timebase_interrupt,
|
||||
.mask = CPU_MASK_NONE,
|
||||
.name = "tbint",
|
||||
};
|
||||
|
||||
/* per-board overridable init_internal_rtc() function. */
|
||||
void __init __attribute__ ((weak))
|
||||
init_internal_rtc(void)
|
||||
{
|
||||
sit8xx_t *sys_tmr = (sit8xx_t *) immr_map(im_sit);
|
||||
|
||||
/* Disable the RTC one second and alarm interrupts. */
|
||||
clrbits16(&sys_tmr->sit_rtcsc, (RTCSC_SIE | RTCSC_ALE));
|
||||
|
||||
/* Enable the RTC */
|
||||
setbits16(&sys_tmr->sit_rtcsc, (RTCSC_RTF | RTCSC_RTE));
|
||||
immr_unmap(sys_tmr);
|
||||
}
|
||||
|
||||
static int __init get_freq(char *name, unsigned long *val)
|
||||
{
|
||||
struct device_node *cpu;
|
||||
unsigned int *fp;
|
||||
int found = 0;
|
||||
|
||||
/* The cpu node should have timebase and clock frequency properties */
|
||||
cpu = of_find_node_by_type(NULL, "cpu");
|
||||
|
||||
if (cpu) {
|
||||
fp = (unsigned int *)get_property(cpu, name, NULL);
|
||||
if (fp) {
|
||||
found = 1;
|
||||
*val = *fp++;
|
||||
}
|
||||
|
||||
of_node_put(cpu);
|
||||
}
|
||||
|
||||
return found;
|
||||
}
|
||||
|
||||
/* The decrementer counts at the system (internal) clock frequency divided by
|
||||
* sixteen, or external oscillator divided by four. We force the processor
|
||||
* to use system clock divided by sixteen.
|
||||
*/
|
||||
void __init mpc8xx_calibrate_decr(void)
|
||||
{
|
||||
struct device_node *cpu;
|
||||
cark8xx_t *clk_r1;
|
||||
car8xx_t *clk_r2;
|
||||
sitk8xx_t *sys_tmr1;
|
||||
sit8xx_t *sys_tmr2;
|
||||
int irq, virq;
|
||||
|
||||
clk_r1 = (cark8xx_t *) immr_map(im_clkrstk);
|
||||
|
||||
/* Unlock the SCCR. */
|
||||
out_be32(&clk_r1->cark_sccrk, ~KAPWR_KEY);
|
||||
out_be32(&clk_r1->cark_sccrk, KAPWR_KEY);
|
||||
immr_unmap(clk_r1);
|
||||
|
||||
/* Force all 8xx processors to use divide by 16 processor clock. */
|
||||
clk_r2 = (car8xx_t *) immr_map(im_clkrst);
|
||||
setbits32(&clk_r2->car_sccr, 0x02000000);
|
||||
immr_unmap(clk_r2);
|
||||
|
||||
/* Processor frequency is MHz.
|
||||
*/
|
||||
ppc_tb_freq = 50000000;
|
||||
if (!get_freq("bus-frequency", &ppc_tb_freq)) {
|
||||
printk(KERN_ERR "WARNING: Estimating decrementer frequency "
|
||||
"(not found)\n");
|
||||
}
|
||||
ppc_tb_freq /= 16;
|
||||
ppc_proc_freq = 50000000;
|
||||
if (!get_freq("clock-frequency", &ppc_proc_freq))
|
||||
printk(KERN_ERR "WARNING: Estimating processor frequency"
|
||||
"(not found)\n");
|
||||
|
||||
printk("Decrementer Frequency = 0x%lx\n", ppc_tb_freq);
|
||||
|
||||
/* Perform some more timer/timebase initialization. This used
|
||||
* to be done elsewhere, but other changes caused it to get
|
||||
* called more than once....that is a bad thing.
|
||||
*
|
||||
* First, unlock all of the registers we are going to modify.
|
||||
* To protect them from corruption during power down, registers
|
||||
* that are maintained by keep alive power are "locked". To
|
||||
* modify these registers we have to write the key value to
|
||||
* the key location associated with the register.
|
||||
* Some boards power up with these unlocked, while others
|
||||
* are locked. Writing anything (including the unlock code?)
|
||||
* to the unlocked registers will lock them again. So, here
|
||||
* we guarantee the registers are locked, then we unlock them
|
||||
* for our use.
|
||||
*/
|
||||
sys_tmr1 = (sitk8xx_t *) immr_map(im_sitk);
|
||||
out_be32(&sys_tmr1->sitk_tbscrk, ~KAPWR_KEY);
|
||||
out_be32(&sys_tmr1->sitk_rtcsck, ~KAPWR_KEY);
|
||||
out_be32(&sys_tmr1->sitk_tbk, ~KAPWR_KEY);
|
||||
out_be32(&sys_tmr1->sitk_tbscrk, KAPWR_KEY);
|
||||
out_be32(&sys_tmr1->sitk_rtcsck, KAPWR_KEY);
|
||||
out_be32(&sys_tmr1->sitk_tbk, KAPWR_KEY);
|
||||
immr_unmap(sys_tmr1);
|
||||
|
||||
init_internal_rtc();
|
||||
|
||||
/* Enabling the decrementer also enables the timebase interrupts
|
||||
* (or from the other point of view, to get decrementer interrupts
|
||||
* we have to enable the timebase). The decrementer interrupt
|
||||
* is wired into the vector table, nothing to do here for that.
|
||||
*/
|
||||
cpu = of_find_node_by_type(NULL, "cpu");
|
||||
virq= irq_of_parse_and_map(cpu, 0);
|
||||
irq = irq_map[virq].hwirq;
|
||||
|
||||
sys_tmr2 = (sit8xx_t *) immr_map(im_sit);
|
||||
out_be16(&sys_tmr2->sit_tbscr, ((1 << (7 - (irq/2))) << 8) |
|
||||
(TBSCR_TBF | TBSCR_TBE));
|
||||
immr_unmap(sys_tmr2);
|
||||
|
||||
if (setup_irq(virq, &tbint_irqaction))
|
||||
panic("Could not allocate timer IRQ!");
|
||||
|
||||
#ifdef CONFIG_8xx_WDT
|
||||
/* Install watchdog timer handler early because it might be
|
||||
* already enabled by the bootloader
|
||||
*/
|
||||
m8xx_wdt_handler_install(binfo);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* The RTC on the MPC8xx is an internal register.
|
||||
* We want to protect this during power down, so we need to unlock,
|
||||
* modify, and re-lock.
|
||||
*/
|
||||
|
||||
int mpc8xx_set_rtc_time(struct rtc_time *tm)
|
||||
{
|
||||
sitk8xx_t *sys_tmr1;
|
||||
sit8xx_t *sys_tmr2;
|
||||
int time;
|
||||
|
||||
sys_tmr1 = (sitk8xx_t *) immr_map(im_sitk);
|
||||
sys_tmr2 = (sit8xx_t *) immr_map(im_sit);
|
||||
time = mktime(tm->tm_year+1900, tm->tm_mon+1, tm->tm_mday,
|
||||
tm->tm_hour, tm->tm_min, tm->tm_sec);
|
||||
|
||||
out_be32(&sys_tmr1->sitk_rtck, KAPWR_KEY);
|
||||
out_be32(&sys_tmr2->sit_rtc, time);
|
||||
out_be32(&sys_tmr1->sitk_rtck, ~KAPWR_KEY);
|
||||
|
||||
immr_unmap(sys_tmr2);
|
||||
immr_unmap(sys_tmr1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void mpc8xx_get_rtc_time(struct rtc_time *tm)
|
||||
{
|
||||
unsigned long data;
|
||||
sit8xx_t *sys_tmr = (sit8xx_t *) immr_map(im_sit);
|
||||
|
||||
/* Get time from the RTC. */
|
||||
data = in_be32(&sys_tmr->sit_rtc);
|
||||
to_tm(data, tm);
|
||||
tm->tm_year -= 1900;
|
||||
tm->tm_mon -= 1;
|
||||
immr_unmap(sys_tmr);
|
||||
return;
|
||||
}
|
||||
|
||||
void mpc8xx_restart(char *cmd)
|
||||
{
|
||||
__volatile__ unsigned char dummy;
|
||||
car8xx_t * clk_r = (car8xx_t *) immr_map(im_clkrst);
|
||||
|
||||
|
||||
local_irq_disable();
|
||||
|
||||
setbits32(&clk_r->car_plprcr, 0x00000080);
|
||||
/* Clear the ME bit in MSR to cause checkstop on machine check
|
||||
*/
|
||||
mtmsr(mfmsr() & ~0x1000);
|
||||
|
||||
dummy = in_8(&clk_r->res[0]);
|
||||
printk("Restart failed\n");
|
||||
while(1);
|
||||
}
|
||||
|
||||
void mpc8xx_show_cpuinfo(struct seq_file *m)
|
||||
{
|
||||
struct device_node *root;
|
||||
uint memsize = total_memory;
|
||||
const char *model = "";
|
||||
|
||||
seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
|
||||
|
||||
root = of_find_node_by_path("/");
|
||||
if (root)
|
||||
model = get_property(root, "model", NULL);
|
||||
seq_printf(m, "Machine\t\t: %s\n", model);
|
||||
of_node_put(root);
|
||||
|
||||
seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
|
||||
}
|
||||
|
||||
static void cpm_cascade(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
int cascade_irq;
|
||||
|
||||
if ((cascade_irq = cpm_get_irq()) >= 0) {
|
||||
struct irq_desc *cdesc = irq_desc + cascade_irq;
|
||||
|
||||
generic_handle_irq(cascade_irq);
|
||||
cdesc->chip->eoi(cascade_irq);
|
||||
}
|
||||
desc->chip->eoi(irq);
|
||||
}
|
||||
|
||||
/* Initialize the internal interrupt controller. The number of
|
||||
* interrupts supported can vary with the processor type, and the
|
||||
* 82xx family can have up to 64.
|
||||
* External interrupts can be either edge or level triggered, and
|
||||
* need to be initialized by the appropriate driver.
|
||||
*/
|
||||
void __init m8xx_pic_init(void)
|
||||
{
|
||||
int irq;
|
||||
|
||||
if (mpc8xx_pic_init()) {
|
||||
printk(KERN_ERR "Failed interrupt 8xx controller initialization\n");
|
||||
return;
|
||||
}
|
||||
|
||||
irq = cpm_pic_init();
|
||||
if (irq != NO_IRQ)
|
||||
set_irq_chained_handler(irq, cpm_cascade);
|
||||
}
|
||||
|
|
@ -0,0 +1,95 @@
|
|||
/*
|
||||
* A collection of structures, addresses, and values associated with
|
||||
* the Freescale MPC86xADS board.
|
||||
* Copied from the FADS stuff.
|
||||
*
|
||||
* Author: MontaVista Software, Inc.
|
||||
* source@mvista.com
|
||||
*
|
||||
* 2005 (c) MontaVista Software, Inc. This file is licensed under the
|
||||
* terms of the GNU General Public License version 2. This program is licensed
|
||||
* "as is" without any warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifdef __KERNEL__
|
||||
#ifndef __ASM_MPC86XADS_H__
|
||||
#define __ASM_MPC86XADS_H__
|
||||
|
||||
#include <asm/ppcboot.h>
|
||||
#include <sysdev/fsl_soc.h>
|
||||
|
||||
/* U-Boot maps BCSR to 0xff080000 */
|
||||
#define BCSR_ADDR ((uint)0xff080000)
|
||||
#define BCSR_SIZE ((uint)32)
|
||||
#define BCSR0 ((uint)(BCSR_ADDR + 0x00))
|
||||
#define BCSR1 ((uint)(BCSR_ADDR + 0x04))
|
||||
#define BCSR2 ((uint)(BCSR_ADDR + 0x08))
|
||||
#define BCSR3 ((uint)(BCSR_ADDR + 0x0c))
|
||||
#define BCSR4 ((uint)(BCSR_ADDR + 0x10))
|
||||
|
||||
#define CFG_PHYDEV_ADDR ((uint)0xff0a0000)
|
||||
#define BCSR5 ((uint)(CFG_PHYDEV_ADDR + 0x300))
|
||||
|
||||
#define IMAP_ADDR (get_immrbase())
|
||||
#define IMAP_SIZE ((uint)(64 * 1024))
|
||||
|
||||
#define MPC8xx_CPM_OFFSET (0x9c0)
|
||||
#define CPM_MAP_ADDR (get_immrbase() + MPC8xx_CPM_OFFSET)
|
||||
#define CPM_IRQ_OFFSET 16 // for compability with cpm_uart driver
|
||||
|
||||
#define PCMCIA_MEM_ADDR (uint)0xff020000)
|
||||
#define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
|
||||
|
||||
/* Bits of interest in the BCSRs.
|
||||
*/
|
||||
#define BCSR1_ETHEN ((uint)0x20000000)
|
||||
#define BCSR1_IRDAEN ((uint)0x10000000)
|
||||
#define BCSR1_RS232EN_1 ((uint)0x01000000)
|
||||
#define BCSR1_PCCEN ((uint)0x00800000)
|
||||
#define BCSR1_PCCVCC0 ((uint)0x00400000)
|
||||
#define BCSR1_PCCVPP0 ((uint)0x00200000)
|
||||
#define BCSR1_PCCVPP1 ((uint)0x00100000)
|
||||
#define BCSR1_PCCVPP_MASK (BCSR1_PCCVPP0 | BCSR1_PCCVPP1)
|
||||
#define BCSR1_RS232EN_2 ((uint)0x00040000)
|
||||
#define BCSR1_PCCVCC1 ((uint)0x00010000)
|
||||
#define BCSR1_PCCVCC_MASK (BCSR1_PCCVCC0 | BCSR1_PCCVCC1)
|
||||
|
||||
#define BCSR4_ETH10_RST ((uint)0x80000000) /* 10Base-T PHY reset*/
|
||||
#define BCSR4_USB_LO_SPD ((uint)0x04000000)
|
||||
#define BCSR4_USB_VCC ((uint)0x02000000)
|
||||
#define BCSR4_USB_FULL_SPD ((uint)0x00040000)
|
||||
#define BCSR4_USB_EN ((uint)0x00020000)
|
||||
|
||||
#define BCSR5_MII2_EN 0x40
|
||||
#define BCSR5_MII2_RST 0x20
|
||||
#define BCSR5_T1_RST 0x10
|
||||
#define BCSR5_ATM155_RST 0x08
|
||||
#define BCSR5_ATM25_RST 0x04
|
||||
#define BCSR5_MII1_EN 0x02
|
||||
#define BCSR5_MII1_RST 0x01
|
||||
|
||||
/* Interrupt level assignments */
|
||||
#define PHY_INTERRUPT SIU_IRQ7 /* PHY link change interrupt */
|
||||
#define SIU_INT_FEC1 SIU_LEVEL1 /* FEC1 interrupt */
|
||||
#define FEC_INTERRUPT SIU_INT_FEC1 /* FEC interrupt */
|
||||
|
||||
/* We don't use the 8259 */
|
||||
#define NR_8259_INTS 0
|
||||
|
||||
/* CPM Ethernet through SCC1 */
|
||||
#define PA_ENET_RXD ((ushort)0x0001)
|
||||
#define PA_ENET_TXD ((ushort)0x0002)
|
||||
#define PA_ENET_TCLK ((ushort)0x0100)
|
||||
#define PA_ENET_RCLK ((ushort)0x0200)
|
||||
#define PB_ENET_TENA ((uint)0x00001000)
|
||||
#define PC_ENET_CLSN ((ushort)0x0010)
|
||||
#define PC_ENET_RENA ((ushort)0x0020)
|
||||
|
||||
/* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to
|
||||
* SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
|
||||
*/
|
||||
#define SICR_ENET_MASK ((uint)0x000000ff)
|
||||
#define SICR_ENET_CLKRT ((uint)0x0000002c)
|
||||
|
||||
#endif /* __ASM_MPC86XADS_H__ */
|
||||
#endif /* __KERNEL__ */
|
||||
|
|
@ -0,0 +1,301 @@
|
|||
/*arch/ppc/platforms/mpc86xads-setup.c
|
||||
*
|
||||
* Platform setup for the Freescale mpc86xads board
|
||||
*
|
||||
* Vitaly Bordug <vbordug@ru.mvista.com>
|
||||
*
|
||||
* Copyright 2005 MontaVista Software Inc.
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/param.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/root_dev.h>
|
||||
|
||||
#include <linux/fs_enet_pd.h>
|
||||
#include <linux/fs_uart_pd.h>
|
||||
#include <linux/mii.h>
|
||||
|
||||
#include <asm/delay.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/machdep.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/system.h>
|
||||
#include <asm/time.h>
|
||||
#include <asm/ppcboot.h>
|
||||
#include <asm/mpc8xx.h>
|
||||
#include <asm/8xx_immap.h>
|
||||
#include <asm/commproc.h>
|
||||
#include <asm/fs_pd.h>
|
||||
#include <asm/prom.h>
|
||||
|
||||
extern void cpm_reset(void);
|
||||
extern void mpc8xx_show_cpuinfo(struct seq_file*);
|
||||
extern void mpc8xx_restart(char *cmd);
|
||||
extern void mpc8xx_calibrate_decr(void);
|
||||
extern int mpc8xx_set_rtc_time(struct rtc_time *tm);
|
||||
extern void mpc8xx_get_rtc_time(struct rtc_time *tm);
|
||||
extern void m8xx_pic_init(void);
|
||||
extern unsigned int mpc8xx_get_irq(void);
|
||||
|
||||
static void init_smc1_uart_ioports(struct fs_uart_platform_info* fpi);
|
||||
static void init_smc2_uart_ioports(struct fs_uart_platform_info* fpi);
|
||||
static void init_scc1_ioports(struct fs_platform_info* ptr);
|
||||
|
||||
void __init mpc86xads_board_setup(void)
|
||||
{
|
||||
cpm8xx_t *cp;
|
||||
unsigned int *bcsr_io;
|
||||
u8 tmpval8;
|
||||
|
||||
bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
|
||||
cp = (cpm8xx_t *)immr_map(im_cpm);
|
||||
|
||||
if (bcsr_io == NULL) {
|
||||
printk(KERN_CRIT "Could not remap BCSR\n");
|
||||
return;
|
||||
}
|
||||
#ifdef CONFIG_SERIAL_CPM_SMC1
|
||||
clrbits32(bcsr_io, BCSR1_RS232EN_1);
|
||||
clrbits32(&cp->cp_simode, 0xe0000000 >> 17); /* brg1 */
|
||||
tmpval8 = in_8(&(cp->cp_smc[0].smc_smcm)) | (SMCM_RX | SMCM_TX);
|
||||
out_8(&(cp->cp_smc[0].smc_smcm), tmpval8);
|
||||
clrbits16(&cp->cp_smc[0].smc_smcmr, SMCMR_REN | SMCMR_TEN);
|
||||
#else
|
||||
setbits32(bcsr_io,BCSR1_RS232EN_1);
|
||||
out_be16(&cp->cp_smc[0].smc_smcmr, 0);
|
||||
out_8(&cp->cp_smc[0].smc_smce, 0);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SERIAL_CPM_SMC2
|
||||
clrbits32(bcsr_io,BCSR1_RS232EN_2);
|
||||
clrbits32(&cp->cp_simode, 0xe0000000 >> 1);
|
||||
setbits32(&cp->cp_simode, 0x20000000 >> 1); /* brg2 */
|
||||
tmpval8 = in_8(&(cp->cp_smc[1].smc_smcm)) | (SMCM_RX | SMCM_TX);
|
||||
out_8(&(cp->cp_smc[1].smc_smcm), tmpval8);
|
||||
clrbits16(&cp->cp_smc[1].smc_smcmr, SMCMR_REN | SMCMR_TEN);
|
||||
|
||||
init_smc2_uart_ioports(0);
|
||||
#else
|
||||
setbits32(bcsr_io,BCSR1_RS232EN_2);
|
||||
out_be16(&cp->cp_smc[1].smc_smcmr, 0);
|
||||
out_8(&cp->cp_smc[1].smc_smce, 0);
|
||||
#endif
|
||||
immr_unmap(cp);
|
||||
iounmap(bcsr_io);
|
||||
}
|
||||
|
||||
|
||||
static void init_fec1_ioports(struct fs_platform_info* ptr)
|
||||
{
|
||||
iop8xx_t *io_port = (iop8xx_t *)immr_map(im_ioport);
|
||||
|
||||
/* configure FEC1 pins */
|
||||
|
||||
setbits16(&io_port->iop_pdpar, 0x1fff);
|
||||
setbits16(&io_port->iop_pddir, 0x1fff);
|
||||
|
||||
immr_unmap(io_port);
|
||||
}
|
||||
|
||||
void init_fec_ioports(struct fs_platform_info *fpi)
|
||||
{
|
||||
int fec_no = fs_get_fec_index(fpi->fs_no);
|
||||
|
||||
switch (fec_no) {
|
||||
case 0:
|
||||
init_fec1_ioports(fpi);
|
||||
break;
|
||||
default:
|
||||
printk(KERN_ERR "init_fec_ioports: invalid FEC number\n");
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
static void init_scc1_ioports(struct fs_platform_info* fpi)
|
||||
{
|
||||
unsigned *bcsr_io;
|
||||
iop8xx_t *io_port;
|
||||
cpm8xx_t *cp;
|
||||
|
||||
bcsr_io = ioremap(BCSR_ADDR, BCSR_SIZE);
|
||||
io_port = (iop8xx_t *)immr_map(im_ioport);
|
||||
cp = (cpm8xx_t *)immr_map(im_cpm);
|
||||
|
||||
if (bcsr_io == NULL) {
|
||||
printk(KERN_CRIT "Could not remap BCSR\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* Configure port A pins for Txd and Rxd.
|
||||
*/
|
||||
setbits16(&io_port->iop_papar, PA_ENET_RXD | PA_ENET_TXD);
|
||||
clrbits16(&io_port->iop_padir, PA_ENET_RXD | PA_ENET_TXD);
|
||||
clrbits16(&io_port->iop_paodr, PA_ENET_TXD);
|
||||
|
||||
/* Configure port C pins to enable CLSN and RENA.
|
||||
*/
|
||||
clrbits16(&io_port->iop_pcpar, PC_ENET_CLSN | PC_ENET_RENA);
|
||||
clrbits16(&io_port->iop_pcdir, PC_ENET_CLSN | PC_ENET_RENA);
|
||||
setbits16(&io_port->iop_pcso, PC_ENET_CLSN | PC_ENET_RENA);
|
||||
|
||||
/* Configure port A for TCLK and RCLK.
|
||||
*/
|
||||
setbits16(&io_port->iop_papar, PA_ENET_TCLK | PA_ENET_RCLK);
|
||||
clrbits16(&io_port->iop_padir, PA_ENET_TCLK | PA_ENET_RCLK);
|
||||
clrbits32(&cp->cp_pbpar, PB_ENET_TENA);
|
||||
clrbits32(&cp->cp_pbdir, PB_ENET_TENA);
|
||||
|
||||
/* Configure Serial Interface clock routing.
|
||||
* First, clear all SCC bits to zero, then set the ones we want.
|
||||
*/
|
||||
clrbits32(&cp->cp_sicr, SICR_ENET_MASK);
|
||||
setbits32(&cp->cp_sicr, SICR_ENET_CLKRT);
|
||||
|
||||
/* In the original SCC enet driver the following code is placed at
|
||||
the end of the initialization */
|
||||
setbits32(&cp->cp_pbpar, PB_ENET_TENA);
|
||||
setbits32(&cp->cp_pbdir, PB_ENET_TENA);
|
||||
|
||||
clrbits32(bcsr_io+1, BCSR1_ETHEN);
|
||||
iounmap(bcsr_io);
|
||||
immr_unmap(cp);
|
||||
immr_unmap(io_port);
|
||||
}
|
||||
|
||||
void init_scc_ioports(struct fs_platform_info *fpi)
|
||||
{
|
||||
int scc_no = fs_get_scc_index(fpi->fs_no);
|
||||
|
||||
switch (scc_no) {
|
||||
case 0:
|
||||
init_scc1_ioports(fpi);
|
||||
break;
|
||||
default:
|
||||
printk(KERN_ERR "init_scc_ioports: invalid SCC number\n");
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
static void init_smc1_uart_ioports(struct fs_uart_platform_info* ptr)
|
||||
{
|
||||
unsigned *bcsr_io;
|
||||
cpm8xx_t *cp = (cpm8xx_t *)immr_map(im_cpm);
|
||||
|
||||
setbits32(&cp->cp_pbpar, 0x000000c0);
|
||||
clrbits32(&cp->cp_pbdir, 0x000000c0);
|
||||
clrbits16(&cp->cp_pbodr, 0x00c0);
|
||||
immr_unmap(cp);
|
||||
|
||||
bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
|
||||
|
||||
if (bcsr_io == NULL) {
|
||||
printk(KERN_CRIT "Could not remap BCSR1\n");
|
||||
return;
|
||||
}
|
||||
clrbits32(bcsr_io,BCSR1_RS232EN_1);
|
||||
iounmap(bcsr_io);
|
||||
}
|
||||
|
||||
static void init_smc2_uart_ioports(struct fs_uart_platform_info* fpi)
|
||||
{
|
||||
unsigned *bcsr_io;
|
||||
cpm8xx_t *cp = (cpm8xx_t *)immr_map(im_cpm);
|
||||
|
||||
setbits32(&cp->cp_pbpar, 0x00000c00);
|
||||
clrbits32(&cp->cp_pbdir, 0x00000c00);
|
||||
clrbits16(&cp->cp_pbodr, 0x0c00);
|
||||
immr_unmap(cp);
|
||||
|
||||
bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
|
||||
|
||||
if (bcsr_io == NULL) {
|
||||
printk(KERN_CRIT "Could not remap BCSR1\n");
|
||||
return;
|
||||
}
|
||||
clrbits32(bcsr_io,BCSR1_RS232EN_2);
|
||||
iounmap(bcsr_io);
|
||||
}
|
||||
|
||||
void init_smc_ioports(struct fs_uart_platform_info *data)
|
||||
{
|
||||
int smc_no = fs_uart_id_fsid2smc(data->fs_no);
|
||||
|
||||
switch (smc_no) {
|
||||
case 0:
|
||||
init_smc1_uart_ioports(data);
|
||||
data->brg = data->clk_rx;
|
||||
break;
|
||||
case 1:
|
||||
init_smc2_uart_ioports(data);
|
||||
data->brg = data->clk_rx;
|
||||
break;
|
||||
default:
|
||||
printk(KERN_ERR "init_scc_ioports: invalid SCC number\n");
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
int platform_device_skip(char *model, int id)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __init mpc86xads_setup_arch(void)
|
||||
{
|
||||
struct device_node *cpu;
|
||||
|
||||
cpu = of_find_node_by_type(NULL, "cpu");
|
||||
if (cpu != 0) {
|
||||
const unsigned int *fp;
|
||||
|
||||
fp = get_property(cpu, "clock-frequency", NULL);
|
||||
if (fp != 0)
|
||||
loops_per_jiffy = *fp / HZ;
|
||||
else
|
||||
loops_per_jiffy = 50000000 / HZ;
|
||||
of_node_put(cpu);
|
||||
}
|
||||
|
||||
cpm_reset();
|
||||
|
||||
mpc86xads_board_setup();
|
||||
|
||||
ROOT_DEV = Root_NFS;
|
||||
}
|
||||
|
||||
static int __init mpc86xads_probe(void)
|
||||
{
|
||||
char *model = of_get_flat_dt_prop(of_get_flat_dt_root(),
|
||||
"model", NULL);
|
||||
if (model == NULL)
|
||||
return 0;
|
||||
if (strcmp(model, "MPC866ADS"))
|
||||
return 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
define_machine(mpc86x_ads) {
|
||||
.name = "MPC86x ADS",
|
||||
.probe = mpc86xads_probe,
|
||||
.setup_arch = mpc86xads_setup_arch,
|
||||
.init_IRQ = m8xx_pic_init,
|
||||
.show_cpuinfo = mpc8xx_show_cpuinfo,
|
||||
.get_irq = mpc8xx_get_irq,
|
||||
.restart = mpc8xx_restart,
|
||||
.calibrate_decr = mpc8xx_calibrate_decr,
|
||||
.set_rtc_time = mpc8xx_set_rtc_time,
|
||||
.get_rtc_time = mpc8xx_get_rtc_time,
|
||||
};
|
||||
|
|
@ -0,0 +1,95 @@
|
|||
/*
|
||||
* A collection of structures, addresses, and values associated with
|
||||
* the Freescale MPC885ADS board.
|
||||
* Copied from the FADS stuff.
|
||||
*
|
||||
* Author: MontaVista Software, Inc.
|
||||
* source@mvista.com
|
||||
*
|
||||
* 2005 (c) MontaVista Software, Inc. This file is licensed under the
|
||||
* terms of the GNU General Public License version 2. This program is licensed
|
||||
* "as is" without any warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifdef __KERNEL__
|
||||
#ifndef __ASM_MPC885ADS_H__
|
||||
#define __ASM_MPC885ADS_H__
|
||||
|
||||
#include <asm/ppcboot.h>
|
||||
#include <sysdev/fsl_soc.h>
|
||||
|
||||
/* U-Boot maps BCSR to 0xff080000 */
|
||||
#define BCSR_ADDR ((uint)0xff080000)
|
||||
#define BCSR_SIZE ((uint)32)
|
||||
#define BCSR0 ((uint)(BCSR_ADDR + 0x00))
|
||||
#define BCSR1 ((uint)(BCSR_ADDR + 0x04))
|
||||
#define BCSR2 ((uint)(BCSR_ADDR + 0x08))
|
||||
#define BCSR3 ((uint)(BCSR_ADDR + 0x0c))
|
||||
#define BCSR4 ((uint)(BCSR_ADDR + 0x10))
|
||||
|
||||
#define CFG_PHYDEV_ADDR ((uint)0xff0a0000)
|
||||
#define BCSR5 ((uint)(CFG_PHYDEV_ADDR + 0x300))
|
||||
|
||||
#define IMAP_ADDR (get_immrbase())
|
||||
#define IMAP_SIZE ((uint)(64 * 1024))
|
||||
|
||||
#define MPC8xx_CPM_OFFSET (0x9c0)
|
||||
#define CPM_MAP_ADDR (get_immrbase() + MPC8xx_CPM_OFFSET)
|
||||
#define CPM_IRQ_OFFSET 16 // for compability with cpm_uart driver
|
||||
|
||||
#define PCMCIA_MEM_ADDR (uint)0xff020000)
|
||||
#define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
|
||||
|
||||
/* Bits of interest in the BCSRs.
|
||||
*/
|
||||
#define BCSR1_ETHEN ((uint)0x20000000)
|
||||
#define BCSR1_IRDAEN ((uint)0x10000000)
|
||||
#define BCSR1_RS232EN_1 ((uint)0x01000000)
|
||||
#define BCSR1_PCCEN ((uint)0x00800000)
|
||||
#define BCSR1_PCCVCC0 ((uint)0x00400000)
|
||||
#define BCSR1_PCCVPP0 ((uint)0x00200000)
|
||||
#define BCSR1_PCCVPP1 ((uint)0x00100000)
|
||||
#define BCSR1_PCCVPP_MASK (BCSR1_PCCVPP0 | BCSR1_PCCVPP1)
|
||||
#define BCSR1_RS232EN_2 ((uint)0x00040000)
|
||||
#define BCSR1_PCCVCC1 ((uint)0x00010000)
|
||||
#define BCSR1_PCCVCC_MASK (BCSR1_PCCVCC0 | BCSR1_PCCVCC1)
|
||||
|
||||
#define BCSR4_ETH10_RST ((uint)0x80000000) /* 10Base-T PHY reset*/
|
||||
#define BCSR4_USB_LO_SPD ((uint)0x04000000)
|
||||
#define BCSR4_USB_VCC ((uint)0x02000000)
|
||||
#define BCSR4_USB_FULL_SPD ((uint)0x00040000)
|
||||
#define BCSR4_USB_EN ((uint)0x00020000)
|
||||
|
||||
#define BCSR5_MII2_EN 0x40
|
||||
#define BCSR5_MII2_RST 0x20
|
||||
#define BCSR5_T1_RST 0x10
|
||||
#define BCSR5_ATM155_RST 0x08
|
||||
#define BCSR5_ATM25_RST 0x04
|
||||
#define BCSR5_MII1_EN 0x02
|
||||
#define BCSR5_MII1_RST 0x01
|
||||
|
||||
/* Interrupt level assignments */
|
||||
#define PHY_INTERRUPT SIU_IRQ7 /* PHY link change interrupt */
|
||||
#define SIU_INT_FEC1 SIU_LEVEL1 /* FEC1 interrupt */
|
||||
#define SIU_INT_FEC2 SIU_LEVEL3 /* FEC2 interrupt */
|
||||
#define FEC_INTERRUPT SIU_INT_FEC1 /* FEC interrupt */
|
||||
|
||||
/* We don't use the 8259 */
|
||||
#define NR_8259_INTS 0
|
||||
|
||||
/* CPM Ethernet through SCC3 */
|
||||
#define PA_ENET_RXD ((ushort)0x0040)
|
||||
#define PA_ENET_TXD ((ushort)0x0080)
|
||||
#define PE_ENET_TCLK ((uint)0x00004000)
|
||||
#define PE_ENET_RCLK ((uint)0x00008000)
|
||||
#define PE_ENET_TENA ((uint)0x00000010)
|
||||
#define PC_ENET_CLSN ((ushort)0x0400)
|
||||
#define PC_ENET_RENA ((ushort)0x0800)
|
||||
|
||||
/* Control bits in the SICR to route TCLK (CLK5) and RCLK (CLK6) to
|
||||
* SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero */
|
||||
#define SICR_ENET_MASK ((uint)0x00ff0000)
|
||||
#define SICR_ENET_CLKRT ((uint)0x002c0000)
|
||||
|
||||
#endif /* __ASM_MPC885ADS_H__ */
|
||||
#endif /* __KERNEL__ */
|
||||
|
|
@ -0,0 +1,387 @@
|
|||
/*arch/ppc/platforms/mpc885ads-setup.c
|
||||
*
|
||||
* Platform setup for the Freescale mpc885ads board
|
||||
*
|
||||
* Vitaly Bordug <vbordug@ru.mvista.com>
|
||||
*
|
||||
* Copyright 2005 MontaVista Software Inc.
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/param.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/root_dev.h>
|
||||
|
||||
#include <linux/fs_enet_pd.h>
|
||||
#include <linux/fs_uart_pd.h>
|
||||
#include <linux/mii.h>
|
||||
|
||||
#include <asm/delay.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/machdep.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/system.h>
|
||||
#include <asm/time.h>
|
||||
#include <asm/ppcboot.h>
|
||||
#include <asm/mpc8xx.h>
|
||||
#include <asm/8xx_immap.h>
|
||||
#include <asm/commproc.h>
|
||||
#include <asm/fs_pd.h>
|
||||
#include <asm/prom.h>
|
||||
|
||||
extern void cpm_reset(void);
|
||||
extern void mpc8xx_show_cpuinfo(struct seq_file*);
|
||||
extern void mpc8xx_restart(char *cmd);
|
||||
extern void mpc8xx_calibrate_decr(void);
|
||||
extern int mpc8xx_set_rtc_time(struct rtc_time *tm);
|
||||
extern void mpc8xx_get_rtc_time(struct rtc_time *tm);
|
||||
extern void m8xx_pic_init(void);
|
||||
extern unsigned int mpc8xx_get_irq(void);
|
||||
|
||||
static void init_smc1_uart_ioports(struct fs_uart_platform_info* fpi);
|
||||
static void init_smc2_uart_ioports(struct fs_uart_platform_info* fpi);
|
||||
static void init_scc3_ioports(struct fs_platform_info* ptr);
|
||||
|
||||
void __init mpc885ads_board_setup(void)
|
||||
{
|
||||
cpm8xx_t *cp;
|
||||
unsigned int *bcsr_io;
|
||||
u8 tmpval8;
|
||||
|
||||
#ifdef CONFIG_FS_ENET
|
||||
iop8xx_t *io_port;
|
||||
#endif
|
||||
|
||||
bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
|
||||
cp = (cpm8xx_t *)immr_map(im_cpm);
|
||||
|
||||
if (bcsr_io == NULL) {
|
||||
printk(KERN_CRIT "Could not remap BCSR\n");
|
||||
return;
|
||||
}
|
||||
#ifdef CONFIG_SERIAL_CPM_SMC1
|
||||
clrbits32(bcsr_io, BCSR1_RS232EN_1);
|
||||
clrbits32(&cp->cp_simode, 0xe0000000 >> 17); /* brg1 */
|
||||
tmpval8 = in_8(&(cp->cp_smc[0].smc_smcm)) | (SMCM_RX | SMCM_TX);
|
||||
out_8(&(cp->cp_smc[0].smc_smcm), tmpval8);
|
||||
clrbits16(&cp->cp_smc[0].smc_smcmr, SMCMR_REN | SMCMR_TEN); /* brg1 */
|
||||
#else
|
||||
setbits32(bcsr_io,BCSR1_RS232EN_1);
|
||||
out_be16(&cp->cp_smc[0].smc_smcmr, 0);
|
||||
out_8(&cp->cp_smc[0].smc_smce, 0);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SERIAL_CPM_SMC2
|
||||
clrbits32(bcsr_io,BCSR1_RS232EN_2);
|
||||
clrbits32(&cp->cp_simode, 0xe0000000 >> 1);
|
||||
setbits32(&cp->cp_simode, 0x20000000 >> 1); /* brg2 */
|
||||
tmpval8 = in_8(&(cp->cp_smc[1].smc_smcm)) | (SMCM_RX | SMCM_TX);
|
||||
out_8(&(cp->cp_smc[1].smc_smcm), tmpval8);
|
||||
clrbits16(&cp->cp_smc[1].smc_smcmr, SMCMR_REN | SMCMR_TEN);
|
||||
|
||||
init_smc2_uart_ioports(0);
|
||||
#else
|
||||
setbits32(bcsr_io,BCSR1_RS232EN_2);
|
||||
out_be16(&cp->cp_smc[1].smc_smcmr, 0);
|
||||
out_8(&cp->cp_smc[1].smc_smce, 0);
|
||||
#endif
|
||||
immr_unmap(cp);
|
||||
iounmap(bcsr_io);
|
||||
|
||||
#ifdef CONFIG_FS_ENET
|
||||
/* use MDC for MII (common) */
|
||||
io_port = (iop8xx_t*)immr_map(im_ioport);
|
||||
setbits16(&io_port->iop_pdpar, 0x0080);
|
||||
clrbits16(&io_port->iop_pddir, 0x0080);
|
||||
|
||||
bcsr_io = ioremap(BCSR5, sizeof(unsigned long));
|
||||
clrbits32(bcsr_io,BCSR5_MII1_EN);
|
||||
clrbits32(bcsr_io,BCSR5_MII1_RST);
|
||||
#ifndef CONFIG_FC_ENET_HAS_SCC
|
||||
clrbits32(bcsr_io,BCSR5_MII2_EN);
|
||||
clrbits32(bcsr_io,BCSR5_MII2_RST);
|
||||
|
||||
#endif
|
||||
iounmap(bcsr_io);
|
||||
immr_unmap(io_port);
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
static void init_fec1_ioports(struct fs_platform_info* ptr)
|
||||
{
|
||||
cpm8xx_t *cp = (cpm8xx_t *)immr_map(im_cpm);
|
||||
iop8xx_t *io_port = (iop8xx_t *)immr_map(im_ioport);
|
||||
|
||||
/* configure FEC1 pins */
|
||||
setbits16(&io_port->iop_papar, 0xf830);
|
||||
setbits16(&io_port->iop_padir, 0x0830);
|
||||
clrbits16(&io_port->iop_padir, 0xf000);
|
||||
|
||||
setbits32(&cp->cp_pbpar, 0x00001001);
|
||||
clrbits32(&cp->cp_pbdir, 0x00001001);
|
||||
|
||||
setbits16(&io_port->iop_pcpar, 0x000c);
|
||||
clrbits16(&io_port->iop_pcdir, 0x000c);
|
||||
|
||||
setbits32(&cp->cp_pepar, 0x00000003);
|
||||
setbits32(&cp->cp_pedir, 0x00000003);
|
||||
clrbits32(&cp->cp_peso, 0x00000003);
|
||||
clrbits32(&cp->cp_cptr, 0x00000100);
|
||||
|
||||
immr_unmap(io_port);
|
||||
immr_unmap(cp);
|
||||
}
|
||||
|
||||
|
||||
static void init_fec2_ioports(struct fs_platform_info* ptr)
|
||||
{
|
||||
cpm8xx_t *cp = (cpm8xx_t *)immr_map(im_cpm);
|
||||
iop8xx_t *io_port = (iop8xx_t *)immr_map(im_ioport);
|
||||
|
||||
/* configure FEC2 pins */
|
||||
setbits32(&cp->cp_pepar, 0x0003fffc);
|
||||
setbits32(&cp->cp_pedir, 0x0003fffc);
|
||||
clrbits32(&cp->cp_peso, 0x000087fc);
|
||||
setbits32(&cp->cp_peso, 0x00037800);
|
||||
clrbits32(&cp->cp_cptr, 0x00000080);
|
||||
|
||||
immr_unmap(io_port);
|
||||
immr_unmap(cp);
|
||||
}
|
||||
|
||||
void init_fec_ioports(struct fs_platform_info *fpi)
|
||||
{
|
||||
int fec_no = fs_get_fec_index(fpi->fs_no);
|
||||
|
||||
switch (fec_no) {
|
||||
case 0:
|
||||
init_fec1_ioports(fpi);
|
||||
break;
|
||||
case 1:
|
||||
init_fec2_ioports(fpi);
|
||||
break;
|
||||
default:
|
||||
printk(KERN_ERR "init_fec_ioports: invalid FEC number\n");
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
static void init_scc3_ioports(struct fs_platform_info* fpi)
|
||||
{
|
||||
unsigned *bcsr_io;
|
||||
iop8xx_t *io_port;
|
||||
cpm8xx_t *cp;
|
||||
|
||||
bcsr_io = ioremap(BCSR_ADDR, BCSR_SIZE);
|
||||
io_port = (iop8xx_t *)immr_map(im_ioport);
|
||||
cp = (cpm8xx_t *)immr_map(im_cpm);
|
||||
|
||||
if (bcsr_io == NULL) {
|
||||
printk(KERN_CRIT "Could not remap BCSR\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* Enable the PHY.
|
||||
*/
|
||||
clrbits32(bcsr_io+4, BCSR4_ETH10_RST);
|
||||
udelay(1000);
|
||||
setbits32(bcsr_io+4, BCSR4_ETH10_RST);
|
||||
/* Configure port A pins for Txd and Rxd.
|
||||
*/
|
||||
setbits16(&io_port->iop_papar, PA_ENET_RXD | PA_ENET_TXD);
|
||||
clrbits16(&io_port->iop_padir, PA_ENET_RXD | PA_ENET_TXD);
|
||||
|
||||
/* Configure port C pins to enable CLSN and RENA.
|
||||
*/
|
||||
clrbits16(&io_port->iop_pcpar, PC_ENET_CLSN | PC_ENET_RENA);
|
||||
clrbits16(&io_port->iop_pcdir, PC_ENET_CLSN | PC_ENET_RENA);
|
||||
setbits16(&io_port->iop_pcso, PC_ENET_CLSN | PC_ENET_RENA);
|
||||
|
||||
/* Configure port E for TCLK and RCLK.
|
||||
*/
|
||||
setbits32(&cp->cp_pepar, PE_ENET_TCLK | PE_ENET_RCLK);
|
||||
clrbits32(&cp->cp_pepar, PE_ENET_TENA);
|
||||
clrbits32(&cp->cp_pedir,
|
||||
PE_ENET_TCLK | PE_ENET_RCLK | PE_ENET_TENA);
|
||||
clrbits32(&cp->cp_peso, PE_ENET_TCLK | PE_ENET_RCLK);
|
||||
setbits32(&cp->cp_peso, PE_ENET_TENA);
|
||||
|
||||
/* Configure Serial Interface clock routing.
|
||||
* First, clear all SCC bits to zero, then set the ones we want.
|
||||
*/
|
||||
clrbits32(&cp->cp_sicr, SICR_ENET_MASK);
|
||||
setbits32(&cp->cp_sicr, SICR_ENET_CLKRT);
|
||||
|
||||
/* Disable Rx and Tx. SMC1 sshould be stopped if SCC3 eternet are used.
|
||||
*/
|
||||
clrbits16(&cp->cp_smc[0].smc_smcmr, SMCMR_REN | SMCMR_TEN);
|
||||
/* On the MPC885ADS SCC ethernet PHY is initialized in the full duplex mode
|
||||
* by H/W setting after reset. SCC ethernet controller support only half duplex.
|
||||
* This discrepancy of modes causes a lot of carrier lost errors.
|
||||
*/
|
||||
|
||||
/* In the original SCC enet driver the following code is placed at
|
||||
the end of the initialization */
|
||||
setbits32(&cp->cp_pepar, PE_ENET_TENA);
|
||||
clrbits32(&cp->cp_pedir, PE_ENET_TENA);
|
||||
setbits32(&cp->cp_peso, PE_ENET_TENA);
|
||||
|
||||
setbits32(bcsr_io+4, BCSR1_ETHEN);
|
||||
iounmap(bcsr_io);
|
||||
immr_unmap(io_port);
|
||||
immr_unmap(cp);
|
||||
}
|
||||
|
||||
void init_scc_ioports(struct fs_platform_info *fpi)
|
||||
{
|
||||
int scc_no = fs_get_scc_index(fpi->fs_no);
|
||||
|
||||
switch (scc_no) {
|
||||
case 2:
|
||||
init_scc3_ioports(fpi);
|
||||
break;
|
||||
default:
|
||||
printk(KERN_ERR "init_scc_ioports: invalid SCC number\n");
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
static void init_smc1_uart_ioports(struct fs_uart_platform_info* ptr)
|
||||
{
|
||||
unsigned *bcsr_io;
|
||||
cpm8xx_t *cp;
|
||||
|
||||
cp = (cpm8xx_t *)immr_map(im_cpm);
|
||||
setbits32(&cp->cp_pepar, 0x000000c0);
|
||||
clrbits32(&cp->cp_pedir, 0x000000c0);
|
||||
clrbits32(&cp->cp_peso, 0x00000040);
|
||||
setbits32(&cp->cp_peso, 0x00000080);
|
||||
immr_unmap(cp);
|
||||
|
||||
bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
|
||||
|
||||
if (bcsr_io == NULL) {
|
||||
printk(KERN_CRIT "Could not remap BCSR1\n");
|
||||
return;
|
||||
}
|
||||
clrbits32(bcsr_io,BCSR1_RS232EN_1);
|
||||
iounmap(bcsr_io);
|
||||
}
|
||||
|
||||
static void init_smc2_uart_ioports(struct fs_uart_platform_info* fpi)
|
||||
{
|
||||
unsigned *bcsr_io;
|
||||
cpm8xx_t *cp;
|
||||
|
||||
cp = (cpm8xx_t *)immr_map(im_cpm);
|
||||
setbits32(&cp->cp_pepar, 0x00000c00);
|
||||
clrbits32(&cp->cp_pedir, 0x00000c00);
|
||||
clrbits32(&cp->cp_peso, 0x00000400);
|
||||
setbits32(&cp->cp_peso, 0x00000800);
|
||||
immr_unmap(cp);
|
||||
|
||||
bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
|
||||
|
||||
if (bcsr_io == NULL) {
|
||||
printk(KERN_CRIT "Could not remap BCSR1\n");
|
||||
return;
|
||||
}
|
||||
clrbits32(bcsr_io,BCSR1_RS232EN_2);
|
||||
iounmap(bcsr_io);
|
||||
}
|
||||
|
||||
void init_smc_ioports(struct fs_uart_platform_info *data)
|
||||
{
|
||||
int smc_no = fs_uart_id_fsid2smc(data->fs_no);
|
||||
|
||||
switch (smc_no) {
|
||||
case 0:
|
||||
init_smc1_uart_ioports(data);
|
||||
data->brg = data->clk_rx;
|
||||
break;
|
||||
case 1:
|
||||
init_smc2_uart_ioports(data);
|
||||
data->brg = data->clk_rx;
|
||||
break;
|
||||
default:
|
||||
printk(KERN_ERR "init_scc_ioports: invalid SCC number\n");
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
int platform_device_skip(char *model, int id)
|
||||
{
|
||||
#ifdef CONFIG_MPC8xx_SECOND_ETH_SCC3
|
||||
const char *dev = "FEC";
|
||||
int n = 2;
|
||||
#else
|
||||
const char *dev = "SCC";
|
||||
int n = 3;
|
||||
#endif
|
||||
|
||||
if (!strcmp(model, dev) && n == id)
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __init mpc885ads_setup_arch(void)
|
||||
{
|
||||
struct device_node *cpu;
|
||||
|
||||
cpu = of_find_node_by_type(NULL, "cpu");
|
||||
if (cpu != 0) {
|
||||
const unsigned int *fp;
|
||||
|
||||
fp = get_property(cpu, "clock-frequency", NULL);
|
||||
if (fp != 0)
|
||||
loops_per_jiffy = *fp / HZ;
|
||||
else
|
||||
loops_per_jiffy = 50000000 / HZ;
|
||||
of_node_put(cpu);
|
||||
}
|
||||
|
||||
cpm_reset();
|
||||
|
||||
mpc885ads_board_setup();
|
||||
|
||||
ROOT_DEV = Root_NFS;
|
||||
}
|
||||
|
||||
static int __init mpc885ads_probe(void)
|
||||
{
|
||||
char *model = of_get_flat_dt_prop(of_get_flat_dt_root(),
|
||||
"model", NULL);
|
||||
if (model == NULL)
|
||||
return 0;
|
||||
if (strcmp(model, "MPC885ADS"))
|
||||
return 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
define_machine(mpc885_ads) {
|
||||
.name = "MPC885 ADS",
|
||||
.probe = mpc885ads_probe,
|
||||
.setup_arch = mpc885ads_setup_arch,
|
||||
.init_IRQ = m8xx_pic_init,
|
||||
.show_cpuinfo = mpc8xx_show_cpuinfo,
|
||||
.get_irq = mpc8xx_get_irq,
|
||||
.restart = mpc8xx_restart,
|
||||
.calibrate_decr = mpc8xx_calibrate_decr,
|
||||
.set_rtc_time = mpc8xx_set_rtc_time,
|
||||
.get_rtc_time = mpc8xx_get_rtc_time,
|
||||
};
|
||||
|
|
@ -8,6 +8,8 @@ endif
|
|||
obj-$(CONFIG_PPC_MPC52xx) += 52xx/
|
||||
obj-$(CONFIG_PPC_CHRP) += chrp/
|
||||
obj-$(CONFIG_4xx) += 4xx/
|
||||
obj-$(CONFIG_PPC_8xx) += 8xx/
|
||||
obj-$(CONFIG_PPC_82xx) += 82xx/
|
||||
obj-$(CONFIG_PPC_83xx) += 83xx/
|
||||
obj-$(CONFIG_PPC_85xx) += 85xx/
|
||||
obj-$(CONFIG_PPC_86xx) += 86xx/
|
||||
|
|
@ -17,4 +19,5 @@ obj-$(CONFIG_PPC_MAPLE) += maple/
|
|||
obj-$(CONFIG_PPC_PASEMI) += pasemi/
|
||||
obj-$(CONFIG_PPC_CELL) += cell/
|
||||
obj-$(CONFIG_PPC_PS3) += ps3/
|
||||
obj-$(CONFIG_PPC_CELLEB) += celleb/
|
||||
obj-$(CONFIG_EMBEDDED6xx) += embedded6xx/
|
||||
|
|
|
|||
|
|
@ -14,7 +14,12 @@ endif
|
|||
spufs-modular-$(CONFIG_SPU_FS) += spu_syscalls.o
|
||||
spu-priv1-$(CONFIG_PPC_CELL_NATIVE) += spu_priv1_mmio.o
|
||||
|
||||
spu-manage-$(CONFIG_PPC_CELLEB) += spu_manage.o
|
||||
spu-manage-$(CONFIG_PPC_CELL_NATIVE) += spu_manage.o
|
||||
|
||||
obj-$(CONFIG_SPU_BASE) += spu_callbacks.o spu_base.o \
|
||||
spu_coredump.o \
|
||||
$(spufs-modular-m) \
|
||||
$(spu-priv1-y) spufs/
|
||||
$(spu-priv1-y) \
|
||||
$(spu-manage-y) \
|
||||
spufs/
|
||||
|
|
|
|||
|
|
@ -170,9 +170,11 @@ int
|
|||
spu_irq_class_0_bottom(struct spu *spu)
|
||||
{
|
||||
unsigned long stat, mask;
|
||||
unsigned long flags;
|
||||
|
||||
spu->class_0_pending = 0;
|
||||
|
||||
spin_lock_irqsave(&spu->register_lock, flags);
|
||||
mask = spu_int_mask_get(spu, 0);
|
||||
stat = spu_int_stat_get(spu, 0);
|
||||
|
||||
|
|
@ -188,6 +190,7 @@ spu_irq_class_0_bottom(struct spu *spu)
|
|||
__spu_trap_error(spu);
|
||||
|
||||
spu_int_stat_clear(spu, 0, stat);
|
||||
spin_unlock_irqrestore(&spu->register_lock, flags);
|
||||
|
||||
return (stat & 0x7) ? -EIO : 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,420 @@
|
|||
/*
|
||||
* spu management operations for of based platforms
|
||||
*
|
||||
* (C) Copyright IBM Deutschland Entwicklung GmbH 2005
|
||||
* Copyright 2006 Sony Corp.
|
||||
* (C) Copyright 2007 TOSHIBA CORPORATION
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*/
|
||||
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/ptrace.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/wait.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/mutex.h>
|
||||
#include <linux/device.h>
|
||||
|
||||
#include <asm/spu.h>
|
||||
#include <asm/spu_priv1.h>
|
||||
#include <asm/firmware.h>
|
||||
#include <asm/prom.h>
|
||||
|
||||
#include "interrupt.h"
|
||||
|
||||
struct device_node *spu_devnode(struct spu *spu)
|
||||
{
|
||||
return spu->devnode;
|
||||
}
|
||||
|
||||
EXPORT_SYMBOL_GPL(spu_devnode);
|
||||
|
||||
static u64 __init find_spu_unit_number(struct device_node *spe)
|
||||
{
|
||||
const unsigned int *prop;
|
||||
int proplen;
|
||||
prop = get_property(spe, "unit-id", &proplen);
|
||||
if (proplen == 4)
|
||||
return (u64)*prop;
|
||||
|
||||
prop = get_property(spe, "reg", &proplen);
|
||||
if (proplen == 4)
|
||||
return (u64)*prop;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init cell_spuprop_present(struct spu *spu, struct device_node *spe,
|
||||
const char *prop)
|
||||
{
|
||||
const struct address_prop {
|
||||
unsigned long address;
|
||||
unsigned int len;
|
||||
} __attribute__((packed)) *p;
|
||||
int proplen;
|
||||
|
||||
unsigned long start_pfn, nr_pages;
|
||||
struct pglist_data *pgdata;
|
||||
struct zone *zone;
|
||||
int ret;
|
||||
|
||||
p = get_property(spe, prop, &proplen);
|
||||
WARN_ON(proplen != sizeof (*p));
|
||||
|
||||
start_pfn = p->address >> PAGE_SHIFT;
|
||||
nr_pages = ((unsigned long)p->len + PAGE_SIZE - 1) >> PAGE_SHIFT;
|
||||
|
||||
pgdata = NODE_DATA(spu->node);
|
||||
zone = pgdata->node_zones;
|
||||
|
||||
ret = __add_pages(zone, start_pfn, nr_pages);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void __iomem * __init map_spe_prop(struct spu *spu,
|
||||
struct device_node *n, const char *name)
|
||||
{
|
||||
const struct address_prop {
|
||||
unsigned long address;
|
||||
unsigned int len;
|
||||
} __attribute__((packed)) *prop;
|
||||
|
||||
const void *p;
|
||||
int proplen;
|
||||
void __iomem *ret = NULL;
|
||||
int err = 0;
|
||||
|
||||
p = get_property(n, name, &proplen);
|
||||
if (proplen != sizeof (struct address_prop))
|
||||
return NULL;
|
||||
|
||||
prop = p;
|
||||
|
||||
err = cell_spuprop_present(spu, n, name);
|
||||
if (err && (err != -EEXIST))
|
||||
goto out;
|
||||
|
||||
ret = ioremap(prop->address, prop->len);
|
||||
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void spu_unmap(struct spu *spu)
|
||||
{
|
||||
if (!firmware_has_feature(FW_FEATURE_LPAR))
|
||||
iounmap(spu->priv1);
|
||||
iounmap(spu->priv2);
|
||||
iounmap(spu->problem);
|
||||
iounmap((__force u8 __iomem *)spu->local_store);
|
||||
}
|
||||
|
||||
static int __init spu_map_interrupts_old(struct spu *spu,
|
||||
struct device_node *np)
|
||||
{
|
||||
unsigned int isrc;
|
||||
const u32 *tmp;
|
||||
int nid;
|
||||
|
||||
/* Get the interrupt source unit from the device-tree */
|
||||
tmp = get_property(np, "isrc", NULL);
|
||||
if (!tmp)
|
||||
return -ENODEV;
|
||||
isrc = tmp[0];
|
||||
|
||||
tmp = get_property(np->parent->parent, "node-id", NULL);
|
||||
if (!tmp) {
|
||||
printk(KERN_WARNING "%s: can't find node-id\n", __FUNCTION__);
|
||||
nid = spu->node;
|
||||
} else
|
||||
nid = tmp[0];
|
||||
|
||||
/* Add the node number */
|
||||
isrc |= nid << IIC_IRQ_NODE_SHIFT;
|
||||
|
||||
/* Now map interrupts of all 3 classes */
|
||||
spu->irqs[0] = irq_create_mapping(NULL, IIC_IRQ_CLASS_0 | isrc);
|
||||
spu->irqs[1] = irq_create_mapping(NULL, IIC_IRQ_CLASS_1 | isrc);
|
||||
spu->irqs[2] = irq_create_mapping(NULL, IIC_IRQ_CLASS_2 | isrc);
|
||||
|
||||
/* Right now, we only fail if class 2 failed */
|
||||
return spu->irqs[2] == NO_IRQ ? -EINVAL : 0;
|
||||
}
|
||||
|
||||
static int __init spu_map_device_old(struct spu *spu)
|
||||
{
|
||||
struct device_node *node = spu->devnode;
|
||||
const char *prop;
|
||||
int ret;
|
||||
|
||||
ret = -ENODEV;
|
||||
spu->name = get_property(node, "name", NULL);
|
||||
if (!spu->name)
|
||||
goto out;
|
||||
|
||||
prop = get_property(node, "local-store", NULL);
|
||||
if (!prop)
|
||||
goto out;
|
||||
spu->local_store_phys = *(unsigned long *)prop;
|
||||
|
||||
/* we use local store as ram, not io memory */
|
||||
spu->local_store = (void __force *)
|
||||
map_spe_prop(spu, node, "local-store");
|
||||
if (!spu->local_store)
|
||||
goto out;
|
||||
|
||||
prop = get_property(node, "problem", NULL);
|
||||
if (!prop)
|
||||
goto out_unmap;
|
||||
spu->problem_phys = *(unsigned long *)prop;
|
||||
|
||||
spu->problem = map_spe_prop(spu, node, "problem");
|
||||
if (!spu->problem)
|
||||
goto out_unmap;
|
||||
|
||||
spu->priv2 = map_spe_prop(spu, node, "priv2");
|
||||
if (!spu->priv2)
|
||||
goto out_unmap;
|
||||
|
||||
if (!firmware_has_feature(FW_FEATURE_LPAR)) {
|
||||
spu->priv1 = map_spe_prop(spu, node, "priv1");
|
||||
if (!spu->priv1)
|
||||
goto out_unmap;
|
||||
}
|
||||
|
||||
ret = 0;
|
||||
goto out;
|
||||
|
||||
out_unmap:
|
||||
spu_unmap(spu);
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int __init spu_map_interrupts(struct spu *spu, struct device_node *np)
|
||||
{
|
||||
struct of_irq oirq;
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
for (i=0; i < 3; i++) {
|
||||
ret = of_irq_map_one(np, i, &oirq);
|
||||
if (ret) {
|
||||
pr_debug("spu_new: failed to get irq %d\n", i);
|
||||
goto err;
|
||||
}
|
||||
ret = -EINVAL;
|
||||
pr_debug(" irq %d no 0x%x on %s\n", i, oirq.specifier[0],
|
||||
oirq.controller->full_name);
|
||||
spu->irqs[i] = irq_create_of_mapping(oirq.controller,
|
||||
oirq.specifier, oirq.size);
|
||||
if (spu->irqs[i] == NO_IRQ) {
|
||||
pr_debug("spu_new: failed to map it !\n");
|
||||
goto err;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
|
||||
err:
|
||||
pr_debug("failed to map irq %x for spu %s\n", *oirq.specifier,
|
||||
spu->name);
|
||||
for (; i >= 0; i--) {
|
||||
if (spu->irqs[i] != NO_IRQ)
|
||||
irq_dispose_mapping(spu->irqs[i]);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int spu_map_resource(struct spu *spu, int nr,
|
||||
void __iomem** virt, unsigned long *phys)
|
||||
{
|
||||
struct device_node *np = spu->devnode;
|
||||
unsigned long start_pfn, nr_pages;
|
||||
struct pglist_data *pgdata;
|
||||
struct zone *zone;
|
||||
struct resource resource = { };
|
||||
unsigned long len;
|
||||
int ret;
|
||||
|
||||
ret = of_address_to_resource(np, nr, &resource);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
if (phys)
|
||||
*phys = resource.start;
|
||||
len = resource.end - resource.start + 1;
|
||||
*virt = ioremap(resource.start, len);
|
||||
if (!*virt)
|
||||
ret = -EINVAL;
|
||||
|
||||
start_pfn = resource.start >> PAGE_SHIFT;
|
||||
nr_pages = (len + PAGE_SIZE - 1) >> PAGE_SHIFT;
|
||||
|
||||
pgdata = NODE_DATA(spu->node);
|
||||
zone = pgdata->node_zones;
|
||||
|
||||
ret = __add_pages(zone, start_pfn, nr_pages);
|
||||
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int __init spu_map_device(struct spu *spu)
|
||||
{
|
||||
struct device_node *np = spu->devnode;
|
||||
int ret = -ENODEV;
|
||||
|
||||
spu->name = get_property(np, "name", NULL);
|
||||
if (!spu->name)
|
||||
goto out;
|
||||
|
||||
ret = spu_map_resource(spu, 0, (void __iomem**)&spu->local_store,
|
||||
&spu->local_store_phys);
|
||||
if (ret) {
|
||||
pr_debug("spu_new: failed to map %s resource 0\n",
|
||||
np->full_name);
|
||||
goto out;
|
||||
}
|
||||
ret = spu_map_resource(spu, 1, (void __iomem**)&spu->problem,
|
||||
&spu->problem_phys);
|
||||
if (ret) {
|
||||
pr_debug("spu_new: failed to map %s resource 1\n",
|
||||
np->full_name);
|
||||
goto out_unmap;
|
||||
}
|
||||
ret = spu_map_resource(spu, 2, (void __iomem**)&spu->priv2, NULL);
|
||||
if (ret) {
|
||||
pr_debug("spu_new: failed to map %s resource 2\n",
|
||||
np->full_name);
|
||||
goto out_unmap;
|
||||
}
|
||||
if (!firmware_has_feature(FW_FEATURE_LPAR))
|
||||
ret = spu_map_resource(spu, 3,
|
||||
(void __iomem**)&spu->priv1, NULL);
|
||||
if (ret) {
|
||||
pr_debug("spu_new: failed to map %s resource 3\n",
|
||||
np->full_name);
|
||||
goto out_unmap;
|
||||
}
|
||||
pr_debug("spu_new: %s maps:\n", np->full_name);
|
||||
pr_debug(" local store : 0x%016lx -> 0x%p\n",
|
||||
spu->local_store_phys, spu->local_store);
|
||||
pr_debug(" problem state : 0x%016lx -> 0x%p\n",
|
||||
spu->problem_phys, spu->problem);
|
||||
pr_debug(" priv2 : 0x%p\n", spu->priv2);
|
||||
pr_debug(" priv1 : 0x%p\n", spu->priv1);
|
||||
|
||||
return 0;
|
||||
|
||||
out_unmap:
|
||||
spu_unmap(spu);
|
||||
out:
|
||||
pr_debug("failed to map spe %s: %d\n", spu->name, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int __init of_enumerate_spus(int (*fn)(void *data))
|
||||
{
|
||||
int ret;
|
||||
struct device_node *node;
|
||||
|
||||
ret = -ENODEV;
|
||||
for (node = of_find_node_by_type(NULL, "spe");
|
||||
node; node = of_find_node_by_type(node, "spe")) {
|
||||
ret = fn(node);
|
||||
if (ret) {
|
||||
printk(KERN_WARNING "%s: Error initializing %s\n",
|
||||
__FUNCTION__, node->name);
|
||||
break;
|
||||
}
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int __init of_create_spu(struct spu *spu, void *data)
|
||||
{
|
||||
int ret;
|
||||
struct device_node *spe = (struct device_node *)data;
|
||||
static int legacy_map = 0, legacy_irq = 0;
|
||||
|
||||
spu->devnode = of_node_get(spe);
|
||||
spu->spe_id = find_spu_unit_number(spe);
|
||||
|
||||
spu->node = of_node_to_nid(spe);
|
||||
if (spu->node >= MAX_NUMNODES) {
|
||||
printk(KERN_WARNING "SPE %s on node %d ignored,"
|
||||
" node number too big\n", spe->full_name, spu->node);
|
||||
printk(KERN_WARNING "Check if CONFIG_NUMA is enabled.\n");
|
||||
ret = -ENODEV;
|
||||
goto out;
|
||||
}
|
||||
|
||||
ret = spu_map_device(spu);
|
||||
if (ret) {
|
||||
if (!legacy_map) {
|
||||
legacy_map = 1;
|
||||
printk(KERN_WARNING "%s: Legacy device tree found, "
|
||||
"trying to map old style\n", __FUNCTION__);
|
||||
}
|
||||
ret = spu_map_device_old(spu);
|
||||
if (ret) {
|
||||
printk(KERN_ERR "Unable to map %s\n",
|
||||
spu->name);
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
|
||||
ret = spu_map_interrupts(spu, spe);
|
||||
if (ret) {
|
||||
if (!legacy_irq) {
|
||||
legacy_irq = 1;
|
||||
printk(KERN_WARNING "%s: Legacy device tree found, "
|
||||
"trying old style irq\n", __FUNCTION__);
|
||||
}
|
||||
ret = spu_map_interrupts_old(spu, spe);
|
||||
if (ret) {
|
||||
printk(KERN_ERR "%s: could not map interrupts",
|
||||
spu->name);
|
||||
goto out_unmap;
|
||||
}
|
||||
}
|
||||
|
||||
pr_debug("Using SPE %s %p %p %p %p %d\n", spu->name,
|
||||
spu->local_store, spu->problem, spu->priv1,
|
||||
spu->priv2, spu->number);
|
||||
goto out;
|
||||
|
||||
out_unmap:
|
||||
spu_unmap(spu);
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int of_destroy_spu(struct spu *spu)
|
||||
{
|
||||
spu_unmap(spu);
|
||||
of_node_put(spu->devnode);
|
||||
return 0;
|
||||
}
|
||||
|
||||
const struct spu_management_ops spu_management_of_ops = {
|
||||
.enumerate_spus = of_enumerate_spus,
|
||||
.create_spu = of_create_spu,
|
||||
.destroy_spu = of_destroy_spu,
|
||||
};
|
||||
|
|
@ -37,490 +37,112 @@
|
|||
#include "interrupt.h"
|
||||
#include "spu_priv1_mmio.h"
|
||||
|
||||
static DEFINE_MUTEX(add_spumem_mutex);
|
||||
|
||||
struct spu_pdata {
|
||||
struct device_node *devnode;
|
||||
struct spu_priv1 __iomem *priv1;
|
||||
};
|
||||
|
||||
static struct spu_pdata *spu_get_pdata(struct spu *spu)
|
||||
{
|
||||
BUG_ON(!spu->pdata);
|
||||
return spu->pdata;
|
||||
}
|
||||
|
||||
struct device_node *spu_devnode(struct spu *spu)
|
||||
{
|
||||
return spu_get_pdata(spu)->devnode;
|
||||
}
|
||||
|
||||
EXPORT_SYMBOL_GPL(spu_devnode);
|
||||
|
||||
static int __init cell_spuprop_present(struct spu *spu, struct device_node *spe,
|
||||
const char *prop)
|
||||
{
|
||||
const struct address_prop {
|
||||
unsigned long address;
|
||||
unsigned int len;
|
||||
} __attribute__((packed)) *p;
|
||||
int proplen;
|
||||
|
||||
unsigned long start_pfn, nr_pages;
|
||||
struct pglist_data *pgdata;
|
||||
struct zone *zone;
|
||||
int ret;
|
||||
|
||||
p = get_property(spe, prop, &proplen);
|
||||
WARN_ON(proplen != sizeof (*p));
|
||||
|
||||
start_pfn = p->address >> PAGE_SHIFT;
|
||||
nr_pages = ((unsigned long)p->len + PAGE_SIZE - 1) >> PAGE_SHIFT;
|
||||
|
||||
pgdata = NODE_DATA(spu->node);
|
||||
zone = pgdata->node_zones;
|
||||
|
||||
/* XXX rethink locking here */
|
||||
mutex_lock(&add_spumem_mutex);
|
||||
ret = __add_pages(zone, start_pfn, nr_pages);
|
||||
mutex_unlock(&add_spumem_mutex);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void __iomem * __init map_spe_prop(struct spu *spu,
|
||||
struct device_node *n, const char *name)
|
||||
{
|
||||
const struct address_prop {
|
||||
unsigned long address;
|
||||
unsigned int len;
|
||||
} __attribute__((packed)) *prop;
|
||||
|
||||
const void *p;
|
||||
int proplen;
|
||||
void __iomem *ret = NULL;
|
||||
int err = 0;
|
||||
|
||||
p = get_property(n, name, &proplen);
|
||||
if (proplen != sizeof (struct address_prop))
|
||||
return NULL;
|
||||
|
||||
prop = p;
|
||||
|
||||
err = cell_spuprop_present(spu, n, name);
|
||||
if (err && (err != -EEXIST))
|
||||
goto out;
|
||||
|
||||
ret = ioremap(prop->address, prop->len);
|
||||
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void spu_unmap(struct spu *spu)
|
||||
{
|
||||
iounmap(spu->priv2);
|
||||
iounmap(spu_get_pdata(spu)->priv1);
|
||||
iounmap(spu->problem);
|
||||
iounmap((__force u8 __iomem *)spu->local_store);
|
||||
}
|
||||
|
||||
static int __init spu_map_interrupts_old(struct spu *spu,
|
||||
struct device_node *np)
|
||||
{
|
||||
unsigned int isrc;
|
||||
const u32 *tmp;
|
||||
int nid;
|
||||
|
||||
/* Get the interrupt source unit from the device-tree */
|
||||
tmp = get_property(np, "isrc", NULL);
|
||||
if (!tmp)
|
||||
return -ENODEV;
|
||||
isrc = tmp[0];
|
||||
|
||||
tmp = get_property(np->parent->parent, "node-id", NULL);
|
||||
if (!tmp) {
|
||||
printk(KERN_WARNING "%s: can't find node-id\n", __FUNCTION__);
|
||||
nid = spu->node;
|
||||
} else
|
||||
nid = tmp[0];
|
||||
|
||||
/* Add the node number */
|
||||
isrc |= nid << IIC_IRQ_NODE_SHIFT;
|
||||
|
||||
/* Now map interrupts of all 3 classes */
|
||||
spu->irqs[0] = irq_create_mapping(NULL, IIC_IRQ_CLASS_0 | isrc);
|
||||
spu->irqs[1] = irq_create_mapping(NULL, IIC_IRQ_CLASS_1 | isrc);
|
||||
spu->irqs[2] = irq_create_mapping(NULL, IIC_IRQ_CLASS_2 | isrc);
|
||||
|
||||
/* Right now, we only fail if class 2 failed */
|
||||
return spu->irqs[2] == NO_IRQ ? -EINVAL : 0;
|
||||
}
|
||||
|
||||
static int __init spu_map_device_old(struct spu *spu, struct device_node *node)
|
||||
{
|
||||
const char *prop;
|
||||
int ret;
|
||||
|
||||
ret = -ENODEV;
|
||||
spu->name = get_property(node, "name", NULL);
|
||||
if (!spu->name)
|
||||
goto out;
|
||||
|
||||
prop = get_property(node, "local-store", NULL);
|
||||
if (!prop)
|
||||
goto out;
|
||||
spu->local_store_phys = *(unsigned long *)prop;
|
||||
|
||||
/* we use local store as ram, not io memory */
|
||||
spu->local_store = (void __force *)
|
||||
map_spe_prop(spu, node, "local-store");
|
||||
if (!spu->local_store)
|
||||
goto out;
|
||||
|
||||
prop = get_property(node, "problem", NULL);
|
||||
if (!prop)
|
||||
goto out_unmap;
|
||||
spu->problem_phys = *(unsigned long *)prop;
|
||||
|
||||
spu->problem= map_spe_prop(spu, node, "problem");
|
||||
if (!spu->problem)
|
||||
goto out_unmap;
|
||||
|
||||
spu_get_pdata(spu)->priv1= map_spe_prop(spu, node, "priv1");
|
||||
|
||||
spu->priv2= map_spe_prop(spu, node, "priv2");
|
||||
if (!spu->priv2)
|
||||
goto out_unmap;
|
||||
ret = 0;
|
||||
goto out;
|
||||
|
||||
out_unmap:
|
||||
spu_unmap(spu);
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int __init spu_map_interrupts(struct spu *spu, struct device_node *np)
|
||||
{
|
||||
struct of_irq oirq;
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
for (i=0; i < 3; i++) {
|
||||
ret = of_irq_map_one(np, i, &oirq);
|
||||
if (ret) {
|
||||
pr_debug("spu_new: failed to get irq %d\n", i);
|
||||
goto err;
|
||||
}
|
||||
ret = -EINVAL;
|
||||
pr_debug(" irq %d no 0x%x on %s\n", i, oirq.specifier[0],
|
||||
oirq.controller->full_name);
|
||||
spu->irqs[i] = irq_create_of_mapping(oirq.controller,
|
||||
oirq.specifier, oirq.size);
|
||||
if (spu->irqs[i] == NO_IRQ) {
|
||||
pr_debug("spu_new: failed to map it !\n");
|
||||
goto err;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
|
||||
err:
|
||||
pr_debug("failed to map irq %x for spu %s\n", *oirq.specifier,
|
||||
spu->name);
|
||||
for (; i >= 0; i--) {
|
||||
if (spu->irqs[i] != NO_IRQ)
|
||||
irq_dispose_mapping(spu->irqs[i]);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int spu_map_resource(struct spu *spu, int nr,
|
||||
void __iomem** virt, unsigned long *phys)
|
||||
{
|
||||
struct device_node *np = spu_get_pdata(spu)->devnode;
|
||||
unsigned long start_pfn, nr_pages;
|
||||
struct pglist_data *pgdata;
|
||||
struct zone *zone;
|
||||
struct resource resource = { };
|
||||
unsigned long len;
|
||||
int ret;
|
||||
|
||||
ret = of_address_to_resource(np, nr, &resource);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
if (phys)
|
||||
*phys = resource.start;
|
||||
len = resource.end - resource.start + 1;
|
||||
*virt = ioremap(resource.start, len);
|
||||
if (!*virt)
|
||||
ret = -EINVAL;
|
||||
|
||||
start_pfn = resource.start >> PAGE_SHIFT;
|
||||
nr_pages = (len + PAGE_SIZE - 1) >> PAGE_SHIFT;
|
||||
|
||||
pgdata = NODE_DATA(spu->node);
|
||||
zone = pgdata->node_zones;
|
||||
|
||||
/* XXX rethink locking here */
|
||||
mutex_lock(&add_spumem_mutex);
|
||||
ret = __add_pages(zone, start_pfn, nr_pages);
|
||||
mutex_unlock(&add_spumem_mutex);
|
||||
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int __init spu_map_device(struct spu *spu)
|
||||
{
|
||||
struct device_node *np = spu_get_pdata(spu)->devnode;
|
||||
int ret = -ENODEV;
|
||||
|
||||
spu->name = get_property(np, "name", NULL);
|
||||
if (!spu->name)
|
||||
goto out;
|
||||
|
||||
ret = spu_map_resource(spu, 0, (void __iomem**)&spu->local_store,
|
||||
&spu->local_store_phys);
|
||||
if (ret) {
|
||||
pr_debug("spu_new: failed to map %s resource 0\n",
|
||||
np->full_name);
|
||||
goto out;
|
||||
}
|
||||
ret = spu_map_resource(spu, 1, (void __iomem**)&spu->problem,
|
||||
&spu->problem_phys);
|
||||
if (ret) {
|
||||
pr_debug("spu_new: failed to map %s resource 1\n",
|
||||
np->full_name);
|
||||
goto out_unmap;
|
||||
}
|
||||
ret = spu_map_resource(spu, 2, (void __iomem**)&spu->priv2, NULL);
|
||||
if (ret) {
|
||||
pr_debug("spu_new: failed to map %s resource 2\n",
|
||||
np->full_name);
|
||||
goto out_unmap;
|
||||
}
|
||||
if (!firmware_has_feature(FW_FEATURE_LPAR))
|
||||
ret = spu_map_resource(spu, 3,
|
||||
(void __iomem**)&spu_get_pdata(spu)->priv1, NULL);
|
||||
if (ret) {
|
||||
pr_debug("spu_new: failed to map %s resource 3\n",
|
||||
np->full_name);
|
||||
goto out_unmap;
|
||||
}
|
||||
pr_debug("spu_new: %s maps:\n", np->full_name);
|
||||
pr_debug(" local store : 0x%016lx -> 0x%p\n",
|
||||
spu->local_store_phys, spu->local_store);
|
||||
pr_debug(" problem state : 0x%016lx -> 0x%p\n",
|
||||
spu->problem_phys, spu->problem);
|
||||
pr_debug(" priv2 : 0x%p\n", spu->priv2);
|
||||
pr_debug(" priv1 : 0x%p\n",
|
||||
spu_get_pdata(spu)->priv1);
|
||||
|
||||
return 0;
|
||||
|
||||
out_unmap:
|
||||
spu_unmap(spu);
|
||||
out:
|
||||
pr_debug("failed to map spe %s: %d\n", spu->name, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int __init of_enumerate_spus(int (*fn)(void *data))
|
||||
{
|
||||
int ret;
|
||||
struct device_node *node;
|
||||
|
||||
ret = -ENODEV;
|
||||
for (node = of_find_node_by_type(NULL, "spe");
|
||||
node; node = of_find_node_by_type(node, "spe")) {
|
||||
ret = fn(node);
|
||||
if (ret) {
|
||||
printk(KERN_WARNING "%s: Error initializing %s\n",
|
||||
__FUNCTION__, node->name);
|
||||
break;
|
||||
}
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int __init of_create_spu(struct spu *spu, void *data)
|
||||
{
|
||||
int ret;
|
||||
struct device_node *spe = (struct device_node *)data;
|
||||
|
||||
spu->pdata = kzalloc(sizeof(struct spu_pdata),
|
||||
GFP_KERNEL);
|
||||
if (!spu->pdata) {
|
||||
ret = -ENOMEM;
|
||||
goto out;
|
||||
}
|
||||
spu_get_pdata(spu)->devnode = of_node_get(spe);
|
||||
|
||||
spu->node = of_node_to_nid(spe);
|
||||
if (spu->node >= MAX_NUMNODES) {
|
||||
printk(KERN_WARNING "SPE %s on node %d ignored,"
|
||||
" node number too big\n", spe->full_name, spu->node);
|
||||
printk(KERN_WARNING "Check if CONFIG_NUMA is enabled.\n");
|
||||
ret = -ENODEV;
|
||||
goto out_free;
|
||||
}
|
||||
|
||||
ret = spu_map_device(spu);
|
||||
/* try old method */
|
||||
if (ret)
|
||||
ret = spu_map_device_old(spu, spe);
|
||||
if (ret)
|
||||
goto out_free;
|
||||
|
||||
ret = spu_map_interrupts(spu, spe);
|
||||
if (ret)
|
||||
ret = spu_map_interrupts_old(spu, spe);
|
||||
if (ret)
|
||||
goto out_unmap;
|
||||
|
||||
pr_debug(KERN_DEBUG "Using SPE %s %p %p %p %p %d\n", spu->name,
|
||||
spu->local_store, spu->problem, spu_get_pdata(spu)->priv1,
|
||||
spu->priv2, spu->number);
|
||||
goto out;
|
||||
|
||||
out_unmap:
|
||||
spu_unmap(spu);
|
||||
out_free:
|
||||
kfree(spu->pdata);
|
||||
spu->pdata = NULL;
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int of_destroy_spu(struct spu *spu)
|
||||
{
|
||||
spu_unmap(spu);
|
||||
of_node_put(spu_get_pdata(spu)->devnode);
|
||||
kfree(spu->pdata);
|
||||
spu->pdata = NULL;
|
||||
return 0;
|
||||
}
|
||||
|
||||
const struct spu_management_ops spu_management_of_ops = {
|
||||
.enumerate_spus = of_enumerate_spus,
|
||||
.create_spu = of_create_spu,
|
||||
.destroy_spu = of_destroy_spu,
|
||||
};
|
||||
|
||||
static void int_mask_and(struct spu *spu, int class, u64 mask)
|
||||
{
|
||||
u64 old_mask;
|
||||
|
||||
old_mask = in_be64(&spu_get_pdata(spu)->priv1->int_mask_RW[class]);
|
||||
out_be64(&spu_get_pdata(spu)->priv1->int_mask_RW[class],
|
||||
old_mask & mask);
|
||||
old_mask = in_be64(&spu->priv1->int_mask_RW[class]);
|
||||
out_be64(&spu->priv1->int_mask_RW[class], old_mask & mask);
|
||||
}
|
||||
|
||||
static void int_mask_or(struct spu *spu, int class, u64 mask)
|
||||
{
|
||||
u64 old_mask;
|
||||
|
||||
old_mask = in_be64(&spu_get_pdata(spu)->priv1->int_mask_RW[class]);
|
||||
out_be64(&spu_get_pdata(spu)->priv1->int_mask_RW[class],
|
||||
old_mask | mask);
|
||||
old_mask = in_be64(&spu->priv1->int_mask_RW[class]);
|
||||
out_be64(&spu->priv1->int_mask_RW[class], old_mask | mask);
|
||||
}
|
||||
|
||||
static void int_mask_set(struct spu *spu, int class, u64 mask)
|
||||
{
|
||||
out_be64(&spu_get_pdata(spu)->priv1->int_mask_RW[class], mask);
|
||||
out_be64(&spu->priv1->int_mask_RW[class], mask);
|
||||
}
|
||||
|
||||
static u64 int_mask_get(struct spu *spu, int class)
|
||||
{
|
||||
return in_be64(&spu_get_pdata(spu)->priv1->int_mask_RW[class]);
|
||||
return in_be64(&spu->priv1->int_mask_RW[class]);
|
||||
}
|
||||
|
||||
static void int_stat_clear(struct spu *spu, int class, u64 stat)
|
||||
{
|
||||
out_be64(&spu_get_pdata(spu)->priv1->int_stat_RW[class], stat);
|
||||
out_be64(&spu->priv1->int_stat_RW[class], stat);
|
||||
}
|
||||
|
||||
static u64 int_stat_get(struct spu *spu, int class)
|
||||
{
|
||||
return in_be64(&spu_get_pdata(spu)->priv1->int_stat_RW[class]);
|
||||
return in_be64(&spu->priv1->int_stat_RW[class]);
|
||||
}
|
||||
|
||||
static void cpu_affinity_set(struct spu *spu, int cpu)
|
||||
{
|
||||
u64 target = iic_get_target_id(cpu);
|
||||
u64 route = target << 48 | target << 32 | target << 16;
|
||||
out_be64(&spu_get_pdata(spu)->priv1->int_route_RW, route);
|
||||
out_be64(&spu->priv1->int_route_RW, route);
|
||||
}
|
||||
|
||||
static u64 mfc_dar_get(struct spu *spu)
|
||||
{
|
||||
return in_be64(&spu_get_pdata(spu)->priv1->mfc_dar_RW);
|
||||
return in_be64(&spu->priv1->mfc_dar_RW);
|
||||
}
|
||||
|
||||
static u64 mfc_dsisr_get(struct spu *spu)
|
||||
{
|
||||
return in_be64(&spu_get_pdata(spu)->priv1->mfc_dsisr_RW);
|
||||
return in_be64(&spu->priv1->mfc_dsisr_RW);
|
||||
}
|
||||
|
||||
static void mfc_dsisr_set(struct spu *spu, u64 dsisr)
|
||||
{
|
||||
out_be64(&spu_get_pdata(spu)->priv1->mfc_dsisr_RW, dsisr);
|
||||
out_be64(&spu->priv1->mfc_dsisr_RW, dsisr);
|
||||
}
|
||||
|
||||
static void mfc_sdr_setup(struct spu *spu)
|
||||
{
|
||||
out_be64(&spu_get_pdata(spu)->priv1->mfc_sdr_RW, mfspr(SPRN_SDR1));
|
||||
out_be64(&spu->priv1->mfc_sdr_RW, mfspr(SPRN_SDR1));
|
||||
}
|
||||
|
||||
static void mfc_sr1_set(struct spu *spu, u64 sr1)
|
||||
{
|
||||
out_be64(&spu_get_pdata(spu)->priv1->mfc_sr1_RW, sr1);
|
||||
out_be64(&spu->priv1->mfc_sr1_RW, sr1);
|
||||
}
|
||||
|
||||
static u64 mfc_sr1_get(struct spu *spu)
|
||||
{
|
||||
return in_be64(&spu_get_pdata(spu)->priv1->mfc_sr1_RW);
|
||||
return in_be64(&spu->priv1->mfc_sr1_RW);
|
||||
}
|
||||
|
||||
static void mfc_tclass_id_set(struct spu *spu, u64 tclass_id)
|
||||
{
|
||||
out_be64(&spu_get_pdata(spu)->priv1->mfc_tclass_id_RW, tclass_id);
|
||||
out_be64(&spu->priv1->mfc_tclass_id_RW, tclass_id);
|
||||
}
|
||||
|
||||
static u64 mfc_tclass_id_get(struct spu *spu)
|
||||
{
|
||||
return in_be64(&spu_get_pdata(spu)->priv1->mfc_tclass_id_RW);
|
||||
return in_be64(&spu->priv1->mfc_tclass_id_RW);
|
||||
}
|
||||
|
||||
static void tlb_invalidate(struct spu *spu)
|
||||
{
|
||||
out_be64(&spu_get_pdata(spu)->priv1->tlb_invalidate_entry_W, 0ul);
|
||||
out_be64(&spu->priv1->tlb_invalidate_entry_W, 0ul);
|
||||
}
|
||||
|
||||
static void resource_allocation_groupID_set(struct spu *spu, u64 id)
|
||||
{
|
||||
out_be64(&spu_get_pdata(spu)->priv1->resource_allocation_groupID_RW,
|
||||
id);
|
||||
out_be64(&spu->priv1->resource_allocation_groupID_RW, id);
|
||||
}
|
||||
|
||||
static u64 resource_allocation_groupID_get(struct spu *spu)
|
||||
{
|
||||
return in_be64(
|
||||
&spu_get_pdata(spu)->priv1->resource_allocation_groupID_RW);
|
||||
return in_be64(&spu->priv1->resource_allocation_groupID_RW);
|
||||
}
|
||||
|
||||
static void resource_allocation_enable_set(struct spu *spu, u64 enable)
|
||||
{
|
||||
out_be64(&spu_get_pdata(spu)->priv1->resource_allocation_enable_RW,
|
||||
enable);
|
||||
out_be64(&spu->priv1->resource_allocation_enable_RW, enable);
|
||||
}
|
||||
|
||||
static u64 resource_allocation_enable_get(struct spu *spu)
|
||||
{
|
||||
return in_be64(
|
||||
&spu_get_pdata(spu)->priv1->resource_allocation_enable_RW);
|
||||
return in_be64(&spu->priv1->resource_allocation_enable_RW);
|
||||
}
|
||||
|
||||
const struct spu_priv1_ops spu_priv1_mmio_ops =
|
||||
|
|
|
|||
|
|
@ -0,0 +1,9 @@
|
|||
obj-y += interrupt.o iommu.o setup.o \
|
||||
htab.o beat.o pci.o \
|
||||
scc_epci.o hvCall.o
|
||||
|
||||
obj-$(CONFIG_SMP) += smp.o
|
||||
obj-$(CONFIG_PPC_UDBG_BEAT) += udbg_beat.o
|
||||
obj-$(CONFIG_USB) += scc_uhc.o
|
||||
obj-$(CONFIG_HAS_TXX9_SERIAL) += scc_sio.o
|
||||
obj-$(CONFIG_SPU_BASE) += spu_priv1.o
|
||||
|
|
@ -0,0 +1,163 @@
|
|||
/*
|
||||
* Simple routines for Celleb/Beat
|
||||
*
|
||||
* (C) Copyright 2006-2007 TOSHIBA CORPORATION
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/rtc.h>
|
||||
|
||||
#include <asm/hvconsole.h>
|
||||
#include <asm/time.h>
|
||||
|
||||
#include "beat_wrapper.h"
|
||||
#include "beat.h"
|
||||
|
||||
void beat_restart(char *cmd)
|
||||
{
|
||||
beat_shutdown_logical_partition(1);
|
||||
}
|
||||
|
||||
void beat_power_off(void)
|
||||
{
|
||||
beat_shutdown_logical_partition(0);
|
||||
}
|
||||
|
||||
u64 beat_halt_code = 0x1000000000000000UL;
|
||||
|
||||
void beat_halt(void)
|
||||
{
|
||||
beat_shutdown_logical_partition(beat_halt_code);
|
||||
}
|
||||
|
||||
int beat_set_rtc_time(struct rtc_time *rtc_time)
|
||||
{
|
||||
u64 tim;
|
||||
tim = mktime(rtc_time->tm_year+1900,
|
||||
rtc_time->tm_mon+1, rtc_time->tm_mday,
|
||||
rtc_time->tm_hour, rtc_time->tm_min, rtc_time->tm_sec);
|
||||
if (beat_rtc_write(tim))
|
||||
return -1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
void beat_get_rtc_time(struct rtc_time *rtc_time)
|
||||
{
|
||||
u64 tim;
|
||||
|
||||
if (beat_rtc_read(&tim))
|
||||
tim = 0;
|
||||
to_tm(tim, rtc_time);
|
||||
rtc_time->tm_year -= 1900;
|
||||
rtc_time->tm_mon -= 1;
|
||||
}
|
||||
|
||||
#define BEAT_NVRAM_SIZE 4096
|
||||
|
||||
ssize_t beat_nvram_read(char *buf, size_t count, loff_t *index)
|
||||
{
|
||||
unsigned int i;
|
||||
unsigned long len;
|
||||
char *p = buf;
|
||||
|
||||
if (*index >= BEAT_NVRAM_SIZE)
|
||||
return -ENODEV;
|
||||
i = *index;
|
||||
if (i + count > BEAT_NVRAM_SIZE)
|
||||
count = BEAT_NVRAM_SIZE - i;
|
||||
|
||||
for (; count != 0; count -= len) {
|
||||
len = count;
|
||||
if (len > BEAT_NVRW_CNT)
|
||||
len = BEAT_NVRW_CNT;
|
||||
if (beat_eeprom_read(i, len, p)) {
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
p += len;
|
||||
i += len;
|
||||
}
|
||||
*index = i;
|
||||
return p - buf;
|
||||
}
|
||||
|
||||
ssize_t beat_nvram_write(char *buf, size_t count, loff_t *index)
|
||||
{
|
||||
unsigned int i;
|
||||
unsigned long len;
|
||||
char *p = buf;
|
||||
|
||||
if (*index >= BEAT_NVRAM_SIZE)
|
||||
return -ENODEV;
|
||||
i = *index;
|
||||
if (i + count > BEAT_NVRAM_SIZE)
|
||||
count = BEAT_NVRAM_SIZE - i;
|
||||
|
||||
for (; count != 0; count -= len) {
|
||||
len = count;
|
||||
if (len > BEAT_NVRW_CNT)
|
||||
len = BEAT_NVRW_CNT;
|
||||
if (beat_eeprom_write(i, len, p)) {
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
p += len;
|
||||
i += len;
|
||||
}
|
||||
*index = i;
|
||||
return p - buf;
|
||||
}
|
||||
|
||||
ssize_t beat_nvram_get_size(void)
|
||||
{
|
||||
return BEAT_NVRAM_SIZE;
|
||||
}
|
||||
|
||||
int beat_set_xdabr(unsigned long dabr)
|
||||
{
|
||||
if (beat_set_dabr(dabr, DABRX_KERNEL | DABRX_USER))
|
||||
return -1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int64_t beat_get_term_char(u64 vterm, u64 *len, u64 *t1, u64 *t2)
|
||||
{
|
||||
u64 db[2];
|
||||
s64 ret;
|
||||
|
||||
ret = beat_get_characters_from_console(vterm, len, (u8*)db);
|
||||
if (ret == 0) {
|
||||
*t1 = db[0];
|
||||
*t2 = db[1];
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
int64_t beat_put_term_char(u64 vterm, u64 len, u64 t1, u64 t2)
|
||||
{
|
||||
u64 db[2];
|
||||
|
||||
db[0] = t1;
|
||||
db[1] = t2;
|
||||
return beat_put_characters_to_console(vterm, len, (u8*)db);
|
||||
}
|
||||
|
||||
EXPORT_SYMBOL(beat_get_term_char);
|
||||
EXPORT_SYMBOL(beat_put_term_char);
|
||||
EXPORT_SYMBOL(beat_halt_code);
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
/*
|
||||
* Guest OS Interfaces.
|
||||
*
|
||||
* (C) Copyright 2006 TOSHIBA CORPORATION
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*/
|
||||
|
||||
#ifndef _CELLEB_BEAT_H
|
||||
#define _CELLEB_BEAT_H
|
||||
|
||||
#define DABRX_KERNEL (1UL<<1)
|
||||
#define DABRX_USER (1UL<<0)
|
||||
|
||||
int64_t beat_get_term_char(uint64_t,uint64_t*,uint64_t*,uint64_t*);
|
||||
int64_t beat_put_term_char(uint64_t,uint64_t,uint64_t,uint64_t);
|
||||
int64_t beat_repository_encode(int, const char *, uint64_t[4]);
|
||||
void beat_restart(char *);
|
||||
void beat_power_off(void);
|
||||
void beat_halt(void);
|
||||
int beat_set_rtc_time(struct rtc_time *);
|
||||
void beat_get_rtc_time(struct rtc_time *);
|
||||
ssize_t beat_nvram_get_size(void);
|
||||
ssize_t beat_nvram_read(char *, size_t, loff_t *);
|
||||
ssize_t beat_nvram_write(char *, size_t, loff_t *);
|
||||
int beat_set_xdabr(unsigned long);
|
||||
|
||||
#endif /* _CELLEB_BEAT_H */
|
||||
|
|
@ -0,0 +1,160 @@
|
|||
/*
|
||||
* Beat hypervisor call numbers
|
||||
*
|
||||
* (C) Copyright 2004-2007 TOSHIBA CORPORATION
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*/
|
||||
|
||||
#ifndef BEAT_BEAT_syscall_H
|
||||
#define BEAT_BEAT_syscall_H
|
||||
|
||||
#ifdef __ASSEMBLY__
|
||||
#define __BEAT_ADD_VENDOR_ID(__x, __v) ((__v)<<60|(__x))
|
||||
#else
|
||||
#define __BEAT_ADD_VENDOR_ID(__x, __v) ((u64)(__v)<<60|(__x))
|
||||
#endif
|
||||
#define HV_allocate_memory __BEAT_ADD_VENDOR_ID(0, 0)
|
||||
#define HV_construct_virtual_address_space __BEAT_ADD_VENDOR_ID(2, 0)
|
||||
#define HV_destruct_virtual_address_space __BEAT_ADD_VENDOR_ID(10, 0)
|
||||
#define HV_get_virtual_address_space_id_of_ppe __BEAT_ADD_VENDOR_ID(4, 0)
|
||||
#define HV_query_logical_partition_address_region_info \
|
||||
__BEAT_ADD_VENDOR_ID(6, 0)
|
||||
#define HV_release_memory __BEAT_ADD_VENDOR_ID(13, 0)
|
||||
#define HV_select_virtual_address_space __BEAT_ADD_VENDOR_ID(7, 0)
|
||||
#define HV_load_range_registers __BEAT_ADD_VENDOR_ID(68, 0)
|
||||
#define HV_set_ppe_l2cache_rmt_entry __BEAT_ADD_VENDOR_ID(70, 0)
|
||||
#define HV_set_ppe_tlb_rmt_entry __BEAT_ADD_VENDOR_ID(71, 0)
|
||||
#define HV_set_spe_tlb_rmt_entry __BEAT_ADD_VENDOR_ID(72, 0)
|
||||
#define HV_get_io_address_translation_fault_info __BEAT_ADD_VENDOR_ID(14, 0)
|
||||
#define HV_get_iopte __BEAT_ADD_VENDOR_ID(16, 0)
|
||||
#define HV_preload_iopt_cache __BEAT_ADD_VENDOR_ID(17, 0)
|
||||
#define HV_put_iopte __BEAT_ADD_VENDOR_ID(15, 0)
|
||||
#define HV_connect_event_ports __BEAT_ADD_VENDOR_ID(21, 0)
|
||||
#define HV_construct_event_receive_port __BEAT_ADD_VENDOR_ID(18, 0)
|
||||
#define HV_destruct_event_receive_port __BEAT_ADD_VENDOR_ID(19, 0)
|
||||
#define HV_destruct_event_send_port __BEAT_ADD_VENDOR_ID(22, 0)
|
||||
#define HV_get_state_of_event_send_port __BEAT_ADD_VENDOR_ID(25, 0)
|
||||
#define HV_request_to_connect_event_ports __BEAT_ADD_VENDOR_ID(20, 0)
|
||||
#define HV_send_event_externally __BEAT_ADD_VENDOR_ID(23, 0)
|
||||
#define HV_send_event_locally __BEAT_ADD_VENDOR_ID(24, 0)
|
||||
#define HV_construct_and_connect_irq_plug __BEAT_ADD_VENDOR_ID(28, 0)
|
||||
#define HV_destruct_irq_plug __BEAT_ADD_VENDOR_ID(29, 0)
|
||||
#define HV_detect_pending_interrupts __BEAT_ADD_VENDOR_ID(26, 0)
|
||||
#define HV_end_of_interrupt __BEAT_ADD_VENDOR_ID(27, 0)
|
||||
#define HV_assign_control_signal_notification_port __BEAT_ADD_VENDOR_ID(45, 0)
|
||||
#define HV_end_of_control_signal_processing __BEAT_ADD_VENDOR_ID(48, 0)
|
||||
#define HV_get_control_signal __BEAT_ADD_VENDOR_ID(46, 0)
|
||||
#define HV_set_irq_mask_for_spe __BEAT_ADD_VENDOR_ID(61, 0)
|
||||
#define HV_shutdown_logical_partition __BEAT_ADD_VENDOR_ID(44, 0)
|
||||
#define HV_connect_message_ports __BEAT_ADD_VENDOR_ID(35, 0)
|
||||
#define HV_destruct_message_port __BEAT_ADD_VENDOR_ID(36, 0)
|
||||
#define HV_receive_message __BEAT_ADD_VENDOR_ID(37, 0)
|
||||
#define HV_get_message_port_info __BEAT_ADD_VENDOR_ID(34, 0)
|
||||
#define HV_request_to_connect_message_ports __BEAT_ADD_VENDOR_ID(33, 0)
|
||||
#define HV_send_message __BEAT_ADD_VENDOR_ID(32, 0)
|
||||
#define HV_get_logical_ppe_id __BEAT_ADD_VENDOR_ID(69, 0)
|
||||
#define HV_pause __BEAT_ADD_VENDOR_ID(9, 0)
|
||||
#define HV_destruct_shared_memory_handle __BEAT_ADD_VENDOR_ID(51, 0)
|
||||
#define HV_get_shared_memory_info __BEAT_ADD_VENDOR_ID(52, 0)
|
||||
#define HV_permit_sharing_memory __BEAT_ADD_VENDOR_ID(50, 0)
|
||||
#define HV_request_to_attach_shared_memory __BEAT_ADD_VENDOR_ID(49, 0)
|
||||
#define HV_enable_logical_spe_execution __BEAT_ADD_VENDOR_ID(55, 0)
|
||||
#define HV_construct_logical_spe __BEAT_ADD_VENDOR_ID(53, 0)
|
||||
#define HV_disable_logical_spe_execution __BEAT_ADD_VENDOR_ID(56, 0)
|
||||
#define HV_destruct_logical_spe __BEAT_ADD_VENDOR_ID(54, 0)
|
||||
#define HV_sense_spe_execution_status __BEAT_ADD_VENDOR_ID(58, 0)
|
||||
#define HV_insert_htab_entry __BEAT_ADD_VENDOR_ID(101, 0)
|
||||
#define HV_read_htab_entries __BEAT_ADD_VENDOR_ID(95, 0)
|
||||
#define HV_write_htab_entry __BEAT_ADD_VENDOR_ID(94, 0)
|
||||
#define HV_assign_io_address_translation_fault_port \
|
||||
__BEAT_ADD_VENDOR_ID(100, 0)
|
||||
#define HV_set_interrupt_mask __BEAT_ADD_VENDOR_ID(73, 0)
|
||||
#define HV_get_logical_partition_id __BEAT_ADD_VENDOR_ID(74, 0)
|
||||
#define HV_create_repository_node2 __BEAT_ADD_VENDOR_ID(90, 0)
|
||||
#define HV_create_repository_node __BEAT_ADD_VENDOR_ID(90, 0) /* alias */
|
||||
#define HV_get_repository_node_value2 __BEAT_ADD_VENDOR_ID(91, 0)
|
||||
#define HV_get_repository_node_value __BEAT_ADD_VENDOR_ID(91, 0) /* alias */
|
||||
#define HV_modify_repository_node_value2 __BEAT_ADD_VENDOR_ID(92, 0)
|
||||
#define HV_modify_repository_node_value __BEAT_ADD_VENDOR_ID(92, 0) /* alias */
|
||||
#define HV_remove_repository_node2 __BEAT_ADD_VENDOR_ID(93, 0)
|
||||
#define HV_remove_repository_node __BEAT_ADD_VENDOR_ID(93, 0) /* alias */
|
||||
#define HV_cancel_shared_memory __BEAT_ADD_VENDOR_ID(104, 0)
|
||||
#define HV_clear_interrupt_status_of_spe __BEAT_ADD_VENDOR_ID(206, 0)
|
||||
#define HV_construct_spe_irq_outlet __BEAT_ADD_VENDOR_ID(80, 0)
|
||||
#define HV_destruct_spe_irq_outlet __BEAT_ADD_VENDOR_ID(81, 0)
|
||||
#define HV_disconnect_ipspc_service __BEAT_ADD_VENDOR_ID(88, 0)
|
||||
#define HV_execute_ipspc_command __BEAT_ADD_VENDOR_ID(86, 0)
|
||||
#define HV_get_interrupt_status_of_spe __BEAT_ADD_VENDOR_ID(205, 0)
|
||||
#define HV_get_spe_privileged_state_1_registers __BEAT_ADD_VENDOR_ID(208, 0)
|
||||
#define HV_permit_use_of_ipspc_service __BEAT_ADD_VENDOR_ID(85, 0)
|
||||
#define HV_reinitialize_logical_spe __BEAT_ADD_VENDOR_ID(82, 0)
|
||||
#define HV_request_ipspc_service __BEAT_ADD_VENDOR_ID(84, 0)
|
||||
#define HV_stop_ipspc_command __BEAT_ADD_VENDOR_ID(87, 0)
|
||||
#define HV_set_spe_privileged_state_1_registers __BEAT_ADD_VENDOR_ID(204, 0)
|
||||
#define HV_get_status_of_ipspc_service __BEAT_ADD_VENDOR_ID(203, 0)
|
||||
#define HV_put_characters_to_console __BEAT_ADD_VENDOR_ID(0x101, 1)
|
||||
#define HV_get_characters_from_console __BEAT_ADD_VENDOR_ID(0x102, 1)
|
||||
#define HV_get_base_clock __BEAT_ADD_VENDOR_ID(0x111, 1)
|
||||
#define HV_set_base_clock __BEAT_ADD_VENDOR_ID(0x112, 1)
|
||||
#define HV_get_frame_cycle __BEAT_ADD_VENDOR_ID(0x114, 1)
|
||||
#define HV_disable_console __BEAT_ADD_VENDOR_ID(0x115, 1)
|
||||
#define HV_disable_all_console __BEAT_ADD_VENDOR_ID(0x116, 1)
|
||||
#define HV_oneshot_timer __BEAT_ADD_VENDOR_ID(0x117, 1)
|
||||
#define HV_set_dabr __BEAT_ADD_VENDOR_ID(0x118, 1)
|
||||
#define HV_get_dabr __BEAT_ADD_VENDOR_ID(0x119, 1)
|
||||
#define HV_start_hv_stats __BEAT_ADD_VENDOR_ID(0x21c, 1)
|
||||
#define HV_stop_hv_stats __BEAT_ADD_VENDOR_ID(0x21d, 1)
|
||||
#define HV_get_hv_stats __BEAT_ADD_VENDOR_ID(0x21e, 1)
|
||||
#define HV_get_hv_error_stats __BEAT_ADD_VENDOR_ID(0x221, 1)
|
||||
#define HV_get_stats __BEAT_ADD_VENDOR_ID(0x224, 1)
|
||||
#define HV_get_heap_stats __BEAT_ADD_VENDOR_ID(0x225, 1)
|
||||
#define HV_get_memory_stats __BEAT_ADD_VENDOR_ID(0x227, 1)
|
||||
#define HV_get_memory_detail __BEAT_ADD_VENDOR_ID(0x228, 1)
|
||||
#define HV_set_priority_of_irq_outlet __BEAT_ADD_VENDOR_ID(0x122, 1)
|
||||
#define HV_get_physical_spe_by_reservation_id __BEAT_ADD_VENDOR_ID(0x128, 1)
|
||||
#define HV_get_spe_context __BEAT_ADD_VENDOR_ID(0x129, 1)
|
||||
#define HV_set_spe_context __BEAT_ADD_VENDOR_ID(0x12a, 1)
|
||||
#define HV_downcount_of_interrupt __BEAT_ADD_VENDOR_ID(0x12e, 1)
|
||||
#define HV_peek_spe_context __BEAT_ADD_VENDOR_ID(0x12f, 1)
|
||||
#define HV_read_bpa_register __BEAT_ADD_VENDOR_ID(0x131, 1)
|
||||
#define HV_write_bpa_register __BEAT_ADD_VENDOR_ID(0x132, 1)
|
||||
#define HV_map_context_table_of_spe __BEAT_ADD_VENDOR_ID(0x137, 1)
|
||||
#define HV_get_slb_for_logical_spe __BEAT_ADD_VENDOR_ID(0x138, 1)
|
||||
#define HV_set_slb_for_logical_spe __BEAT_ADD_VENDOR_ID(0x139, 1)
|
||||
#define HV_init_pm __BEAT_ADD_VENDOR_ID(0x150, 1)
|
||||
#define HV_set_pm_signal __BEAT_ADD_VENDOR_ID(0x151, 1)
|
||||
#define HV_get_pm_signal __BEAT_ADD_VENDOR_ID(0x152, 1)
|
||||
#define HV_set_pm_config __BEAT_ADD_VENDOR_ID(0x153, 1)
|
||||
#define HV_get_pm_config __BEAT_ADD_VENDOR_ID(0x154, 1)
|
||||
#define HV_get_inner_trace_data __BEAT_ADD_VENDOR_ID(0x155, 1)
|
||||
#define HV_set_ext_trace_buffer __BEAT_ADD_VENDOR_ID(0x156, 1)
|
||||
#define HV_get_ext_trace_buffer __BEAT_ADD_VENDOR_ID(0x157, 1)
|
||||
#define HV_set_pm_interrupt __BEAT_ADD_VENDOR_ID(0x158, 1)
|
||||
#define HV_get_pm_interrupt __BEAT_ADD_VENDOR_ID(0x159, 1)
|
||||
#define HV_kick_pm __BEAT_ADD_VENDOR_ID(0x160, 1)
|
||||
#define HV_construct_pm_context __BEAT_ADD_VENDOR_ID(0x164, 1)
|
||||
#define HV_destruct_pm_context __BEAT_ADD_VENDOR_ID(0x165, 1)
|
||||
#define HV_be_slow __BEAT_ADD_VENDOR_ID(0x170, 1)
|
||||
#define HV_assign_ipspc_server_connection_status_notification_port \
|
||||
__BEAT_ADD_VENDOR_ID(0x173, 1)
|
||||
#define HV_get_raid_of_physical_spe __BEAT_ADD_VENDOR_ID(0x174, 1)
|
||||
#define HV_set_physical_spe_to_rag __BEAT_ADD_VENDOR_ID(0x175, 1)
|
||||
#define HV_release_physical_spe_from_rag __BEAT_ADD_VENDOR_ID(0x176, 1)
|
||||
#define HV_rtc_read __BEAT_ADD_VENDOR_ID(0x190, 1)
|
||||
#define HV_rtc_write __BEAT_ADD_VENDOR_ID(0x191, 1)
|
||||
#define HV_eeprom_read __BEAT_ADD_VENDOR_ID(0x192, 1)
|
||||
#define HV_eeprom_write __BEAT_ADD_VENDOR_ID(0x193, 1)
|
||||
#endif
|
||||
|
|
@ -0,0 +1,220 @@
|
|||
/*
|
||||
* Beat hypervisor call I/F
|
||||
*
|
||||
* (C) Copyright 2007 TOSHIBA CORPORATION
|
||||
*
|
||||
* This code is based on arch/powerpc/platforms/pseries/plpar_wrapper.h.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*/
|
||||
#ifndef BEAT_HCALL
|
||||
#include "beat_syscall.h"
|
||||
|
||||
/* defined in hvCall.S */
|
||||
extern s64 beat_hcall_norets(u64 opcode, ...);
|
||||
extern s64 beat_hcall_norets8(u64 opcode, u64 arg1, u64 arg2, u64 arg3,
|
||||
u64 arg4, u64 arg5, u64 arg6, u64 arg7, u64 arg8);
|
||||
extern s64 beat_hcall1(u64 opcode, u64 retbuf[1], ...);
|
||||
extern s64 beat_hcall2(u64 opcode, u64 retbuf[2], ...);
|
||||
extern s64 beat_hcall3(u64 opcode, u64 retbuf[3], ...);
|
||||
extern s64 beat_hcall4(u64 opcode, u64 retbuf[4], ...);
|
||||
extern s64 beat_hcall5(u64 opcode, u64 retbuf[5], ...);
|
||||
extern s64 beat_hcall6(u64 opcode, u64 retbuf[6], ...);
|
||||
|
||||
static inline s64 beat_downcount_of_interrupt(u64 plug_id)
|
||||
{
|
||||
return beat_hcall_norets(HV_downcount_of_interrupt, plug_id);
|
||||
}
|
||||
|
||||
static inline s64 beat_set_interrupt_mask(u64 index,
|
||||
u64 val0, u64 val1, u64 val2, u64 val3)
|
||||
{
|
||||
return beat_hcall_norets(HV_set_interrupt_mask, index,
|
||||
val0, val1, val2, val3);
|
||||
}
|
||||
|
||||
static inline s64 beat_destruct_irq_plug(u64 plug_id)
|
||||
{
|
||||
return beat_hcall_norets(HV_destruct_irq_plug, plug_id);
|
||||
}
|
||||
|
||||
static inline s64 beat_construct_and_connect_irq_plug(u64 plug_id,
|
||||
u64 outlet_id)
|
||||
{
|
||||
return beat_hcall_norets(HV_construct_and_connect_irq_plug, plug_id,
|
||||
outlet_id);
|
||||
}
|
||||
|
||||
static inline s64 beat_detect_pending_interrupts(u64 index, u64 *retbuf)
|
||||
{
|
||||
return beat_hcall4(HV_detect_pending_interrupts, retbuf, index);
|
||||
}
|
||||
|
||||
static inline s64 beat_pause(u64 style)
|
||||
{
|
||||
return beat_hcall_norets(HV_pause, style);
|
||||
}
|
||||
|
||||
static inline s64 beat_read_htab_entries(u64 htab_id, u64 index, u64 *retbuf)
|
||||
{
|
||||
return beat_hcall5(HV_read_htab_entries, retbuf, htab_id, index);
|
||||
}
|
||||
|
||||
static inline s64 beat_insert_htab_entry(u64 htab_id, u64 group,
|
||||
u64 bitmask, u64 hpte_v, u64 hpte_r, u64 *slot)
|
||||
{
|
||||
u64 dummy[3];
|
||||
s64 ret;
|
||||
|
||||
ret = beat_hcall3(HV_insert_htab_entry, dummy, htab_id, group,
|
||||
bitmask, hpte_v, hpte_r);
|
||||
*slot = dummy[0];
|
||||
return ret;
|
||||
}
|
||||
|
||||
static inline s64 beat_write_htab_entry(u64 htab_id, u64 slot,
|
||||
u64 hpte_v, u64 hpte_r, u64 mask_v, u64 mask_r,
|
||||
u64 *ret_v, u64 *ret_r)
|
||||
{
|
||||
u64 dummy[2];
|
||||
s64 ret;
|
||||
|
||||
ret = beat_hcall2(HV_write_htab_entry, dummy, htab_id, slot,
|
||||
hpte_v, hpte_r, mask_v, mask_r);
|
||||
*ret_v = dummy[0];
|
||||
*ret_r = dummy[1];
|
||||
return ret;
|
||||
}
|
||||
|
||||
static inline void beat_shutdown_logical_partition(u64 code)
|
||||
{
|
||||
(void)beat_hcall_norets(HV_shutdown_logical_partition, code);
|
||||
}
|
||||
|
||||
static inline s64 beat_rtc_write(u64 time_from_epoch)
|
||||
{
|
||||
return beat_hcall_norets(HV_rtc_write, time_from_epoch);
|
||||
}
|
||||
|
||||
static inline s64 beat_rtc_read(u64 *time_from_epoch)
|
||||
{
|
||||
u64 dummy[1];
|
||||
s64 ret;
|
||||
|
||||
ret = beat_hcall1(HV_rtc_read, dummy);
|
||||
*time_from_epoch = dummy[0];
|
||||
return ret;
|
||||
}
|
||||
|
||||
#define BEAT_NVRW_CNT (sizeof(u64) * 6)
|
||||
|
||||
static inline s64 beat_eeprom_write(u64 index, u64 length, u8 *buffer)
|
||||
{
|
||||
u64 b[6];
|
||||
|
||||
if (length > BEAT_NVRW_CNT)
|
||||
return -1;
|
||||
memcpy(b, buffer, sizeof(b));
|
||||
return beat_hcall_norets8(HV_eeprom_write, index, length,
|
||||
b[0], b[1], b[2], b[3], b[4], b[5]);
|
||||
}
|
||||
|
||||
static inline s64 beat_eeprom_read(u64 index, u64 length, u8 *buffer)
|
||||
{
|
||||
u64 b[6];
|
||||
s64 ret;
|
||||
|
||||
if (length > BEAT_NVRW_CNT)
|
||||
return -1;
|
||||
ret = beat_hcall6(HV_eeprom_read, b, index, length);
|
||||
memcpy(buffer, b, length);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static inline s64 beat_set_dabr(u64 value, u64 style)
|
||||
{
|
||||
return beat_hcall_norets(HV_set_dabr, value, style);
|
||||
}
|
||||
|
||||
static inline s64 beat_get_characters_from_console(u64 termno, u64 *len,
|
||||
u8 *buffer)
|
||||
{
|
||||
u64 dummy[3];
|
||||
s64 ret;
|
||||
|
||||
ret = beat_hcall3(HV_get_characters_from_console, dummy, termno, len);
|
||||
*len = dummy[0];
|
||||
memcpy(buffer, dummy + 1, *len);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static inline s64 beat_put_characters_to_console(u64 termno, u64 len,
|
||||
u8 *buffer)
|
||||
{
|
||||
u64 b[2];
|
||||
|
||||
memcpy(b, buffer, len);
|
||||
return beat_hcall_norets(HV_put_characters_to_console, termno, len, b[0], b[1]);
|
||||
}
|
||||
|
||||
static inline s64 beat_get_spe_privileged_state_1_registers(
|
||||
u64 id, u64 offsetof, u64 *value)
|
||||
{
|
||||
u64 dummy[1];
|
||||
s64 ret;
|
||||
|
||||
ret = beat_hcall1(HV_get_spe_privileged_state_1_registers, dummy, id,
|
||||
offsetof);
|
||||
*value = dummy[0];
|
||||
return ret;
|
||||
}
|
||||
|
||||
static inline s64 beat_set_irq_mask_for_spe(u64 id, u64 class, u64 mask)
|
||||
{
|
||||
return beat_hcall_norets(HV_set_irq_mask_for_spe, id, class, mask);
|
||||
}
|
||||
|
||||
static inline s64 beat_clear_interrupt_status_of_spe(u64 id, u64 class,
|
||||
u64 mask)
|
||||
{
|
||||
return beat_hcall_norets(HV_clear_interrupt_status_of_spe,
|
||||
id, class, mask);
|
||||
}
|
||||
|
||||
static inline s64 beat_set_spe_privileged_state_1_registers(
|
||||
u64 id, u64 offsetof, u64 value)
|
||||
{
|
||||
return beat_hcall_norets(HV_set_spe_privileged_state_1_registers,
|
||||
id, offsetof, value);
|
||||
}
|
||||
|
||||
static inline s64 beat_get_interrupt_status_of_spe(u64 id, u64 class, u64 *val)
|
||||
{
|
||||
u64 dummy[1];
|
||||
s64 ret;
|
||||
|
||||
ret = beat_hcall1(HV_get_interrupt_status_of_spe, dummy, id, class);
|
||||
*val = dummy[0];
|
||||
return ret;
|
||||
}
|
||||
|
||||
static inline s64 beat_put_iopte(u64 ioas_id, u64 io_addr, u64 real_addr,
|
||||
u64 ioid, u64 flags)
|
||||
{
|
||||
return beat_hcall_norets(HV_put_iopte, ioas_id, io_addr, real_addr,
|
||||
ioid, flags);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,311 @@
|
|||
/*
|
||||
* "Cell Reference Set" HTAB support.
|
||||
*
|
||||
* (C) Copyright 2006-2007 TOSHIBA CORPORATION
|
||||
*
|
||||
* This code is based on arch/powerpc/platforms/pseries/lpar.c:
|
||||
* Copyright (C) 2001 Todd Inglett, IBM Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*/
|
||||
|
||||
#undef DEBUG_LOW
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
#include <asm/mmu.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/machdep.h>
|
||||
#include <asm/udbg.h>
|
||||
|
||||
#include "beat_wrapper.h"
|
||||
|
||||
#ifdef DEBUG_LOW
|
||||
#define DBG_LOW(fmt...) do { udbg_printf(fmt); } while(0)
|
||||
#else
|
||||
#define DBG_LOW(fmt...) do { } while(0)
|
||||
#endif
|
||||
|
||||
static DEFINE_SPINLOCK(beat_htab_lock);
|
||||
|
||||
static inline unsigned int beat_read_mask(unsigned hpte_group)
|
||||
{
|
||||
unsigned long hpte_v[5];
|
||||
unsigned long rmask = 0;
|
||||
|
||||
beat_read_htab_entries(0, hpte_group + 0, hpte_v);
|
||||
if (!(hpte_v[0] & HPTE_V_BOLTED))
|
||||
rmask |= 0x8000;
|
||||
if (!(hpte_v[1] & HPTE_V_BOLTED))
|
||||
rmask |= 0x4000;
|
||||
if (!(hpte_v[2] & HPTE_V_BOLTED))
|
||||
rmask |= 0x2000;
|
||||
if (!(hpte_v[3] & HPTE_V_BOLTED))
|
||||
rmask |= 0x1000;
|
||||
beat_read_htab_entries(0, hpte_group + 4, hpte_v);
|
||||
if (!(hpte_v[0] & HPTE_V_BOLTED))
|
||||
rmask |= 0x0800;
|
||||
if (!(hpte_v[1] & HPTE_V_BOLTED))
|
||||
rmask |= 0x0400;
|
||||
if (!(hpte_v[2] & HPTE_V_BOLTED))
|
||||
rmask |= 0x0200;
|
||||
if (!(hpte_v[3] & HPTE_V_BOLTED))
|
||||
rmask |= 0x0100;
|
||||
hpte_group = ~hpte_group & (htab_hash_mask * HPTES_PER_GROUP);
|
||||
beat_read_htab_entries(0, hpte_group + 0, hpte_v);
|
||||
if (!(hpte_v[0] & HPTE_V_BOLTED))
|
||||
rmask |= 0x80;
|
||||
if (!(hpte_v[1] & HPTE_V_BOLTED))
|
||||
rmask |= 0x40;
|
||||
if (!(hpte_v[2] & HPTE_V_BOLTED))
|
||||
rmask |= 0x20;
|
||||
if (!(hpte_v[3] & HPTE_V_BOLTED))
|
||||
rmask |= 0x10;
|
||||
beat_read_htab_entries(0, hpte_group + 4, hpte_v);
|
||||
if (!(hpte_v[0] & HPTE_V_BOLTED))
|
||||
rmask |= 0x08;
|
||||
if (!(hpte_v[1] & HPTE_V_BOLTED))
|
||||
rmask |= 0x04;
|
||||
if (!(hpte_v[2] & HPTE_V_BOLTED))
|
||||
rmask |= 0x02;
|
||||
if (!(hpte_v[3] & HPTE_V_BOLTED))
|
||||
rmask |= 0x01;
|
||||
return rmask;
|
||||
}
|
||||
|
||||
static long beat_lpar_hpte_insert(unsigned long hpte_group,
|
||||
unsigned long va, unsigned long pa,
|
||||
unsigned long rflags, unsigned long vflags,
|
||||
int psize)
|
||||
{
|
||||
unsigned long lpar_rc;
|
||||
unsigned long slot;
|
||||
unsigned long hpte_v, hpte_r;
|
||||
unsigned long flags;
|
||||
|
||||
/* same as iseries */
|
||||
if (vflags & HPTE_V_SECONDARY)
|
||||
return -1;
|
||||
|
||||
if (!(vflags & HPTE_V_BOLTED))
|
||||
DBG_LOW("hpte_insert(group=%lx, va=%016lx, pa=%016lx, "
|
||||
"rflags=%lx, vflags=%lx, psize=%d)\n",
|
||||
hpte_group, va, pa, rflags, vflags, psize);
|
||||
|
||||
hpte_v = hpte_encode_v(va, psize) | vflags | HPTE_V_VALID;
|
||||
hpte_r = hpte_encode_r(pa, psize) | rflags;
|
||||
|
||||
if (!(vflags & HPTE_V_BOLTED))
|
||||
DBG_LOW(" hpte_v=%016lx, hpte_r=%016lx\n", hpte_v, hpte_r);
|
||||
|
||||
if (rflags & (_PAGE_GUARDED|_PAGE_NO_CACHE))
|
||||
hpte_r &= ~_PAGE_COHERENT;
|
||||
|
||||
spin_lock_irqsave(&beat_htab_lock, flags);
|
||||
if ((lpar_rc = beat_read_mask(hpte_group)) == 0) {
|
||||
if (!(vflags & HPTE_V_BOLTED))
|
||||
DBG_LOW(" full\n");
|
||||
spin_unlock_irqrestore(&beat_htab_lock, flags);
|
||||
return -1;
|
||||
}
|
||||
|
||||
lpar_rc = beat_insert_htab_entry(0, hpte_group, lpar_rc << 48,
|
||||
hpte_v, hpte_r, &slot);
|
||||
spin_unlock_irqrestore(&beat_htab_lock, flags);
|
||||
|
||||
/*
|
||||
* Since we try and ioremap PHBs we don't own, the pte insert
|
||||
* will fail. However we must catch the failure in hash_page
|
||||
* or we will loop forever, so return -2 in this case.
|
||||
*/
|
||||
if (unlikely(lpar_rc != 0)) {
|
||||
if (!(vflags & HPTE_V_BOLTED))
|
||||
DBG_LOW(" lpar err %lx\n", lpar_rc);
|
||||
return -2;
|
||||
}
|
||||
if (!(vflags & HPTE_V_BOLTED))
|
||||
DBG_LOW(" -> slot: %lx\n", slot);
|
||||
|
||||
/* We have to pass down the secondary bucket bit here as well */
|
||||
return (slot ^ hpte_group) & 15;
|
||||
}
|
||||
|
||||
static long beat_lpar_hpte_remove(unsigned long hpte_group)
|
||||
{
|
||||
DBG_LOW("hpte_remove(group=%lx)\n", hpte_group);
|
||||
return -1;
|
||||
}
|
||||
|
||||
static unsigned long beat_lpar_hpte_getword0(unsigned long slot)
|
||||
{
|
||||
unsigned long dword0, dword[5];
|
||||
unsigned long lpar_rc;
|
||||
|
||||
lpar_rc = beat_read_htab_entries(0, slot & ~3UL, dword);
|
||||
|
||||
dword0 = dword[slot&3];
|
||||
|
||||
BUG_ON(lpar_rc != 0);
|
||||
|
||||
return dword0;
|
||||
}
|
||||
|
||||
static void beat_lpar_hptab_clear(void)
|
||||
{
|
||||
unsigned long size_bytes = 1UL << ppc64_pft_size;
|
||||
unsigned long hpte_count = size_bytes >> 4;
|
||||
int i;
|
||||
unsigned long dummy0, dummy1;
|
||||
|
||||
/* TODO: Use bulk call */
|
||||
for (i = 0; i < hpte_count; i++)
|
||||
beat_write_htab_entry(0, i, 0, 0, -1UL, -1UL, &dummy0, &dummy1);
|
||||
}
|
||||
|
||||
/*
|
||||
* NOTE: for updatepp ops we are fortunate that the linux "newpp" bits and
|
||||
* the low 3 bits of flags happen to line up. So no transform is needed.
|
||||
* We can probably optimize here and assume the high bits of newpp are
|
||||
* already zero. For now I am paranoid.
|
||||
*/
|
||||
static long beat_lpar_hpte_updatepp(unsigned long slot,
|
||||
unsigned long newpp,
|
||||
unsigned long va,
|
||||
int psize, int local)
|
||||
{
|
||||
unsigned long lpar_rc;
|
||||
unsigned long dummy0, dummy1, want_v;
|
||||
unsigned long flags;
|
||||
|
||||
want_v = hpte_encode_v(va, psize);
|
||||
|
||||
DBG_LOW(" update: "
|
||||
"avpnv=%016lx, slot=%016lx, psize: %d, newpp %016lx ... ",
|
||||
want_v & HPTE_V_AVPN, slot, psize, newpp);
|
||||
|
||||
spin_lock_irqsave(&beat_htab_lock, flags);
|
||||
dummy0 = beat_lpar_hpte_getword0(slot);
|
||||
if ((dummy0 & ~0x7FUL) != (want_v & ~0x7FUL)) {
|
||||
DBG_LOW("not found !\n");
|
||||
spin_unlock_irqrestore(&beat_htab_lock, flags);
|
||||
return -1;
|
||||
}
|
||||
|
||||
lpar_rc = beat_write_htab_entry(0, slot, 0, newpp, 0, 7, &dummy0,
|
||||
&dummy1);
|
||||
spin_unlock_irqrestore(&beat_htab_lock, flags);
|
||||
if (lpar_rc != 0 || dummy0 == 0) {
|
||||
DBG_LOW("not found !\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
DBG_LOW("ok %lx %lx\n", dummy0, dummy1);
|
||||
|
||||
BUG_ON(lpar_rc != 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static long beat_lpar_hpte_find(unsigned long va, int psize)
|
||||
{
|
||||
unsigned long hash;
|
||||
unsigned long i, j;
|
||||
long slot;
|
||||
unsigned long want_v, hpte_v;
|
||||
|
||||
hash = hpt_hash(va, mmu_psize_defs[psize].shift);
|
||||
want_v = hpte_encode_v(va, psize);
|
||||
|
||||
for (j = 0; j < 2; j++) {
|
||||
slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
|
||||
for (i = 0; i < HPTES_PER_GROUP; i++) {
|
||||
hpte_v = beat_lpar_hpte_getword0(slot);
|
||||
|
||||
if (HPTE_V_COMPARE(hpte_v, want_v)
|
||||
&& (hpte_v & HPTE_V_VALID)
|
||||
&& (!!(hpte_v & HPTE_V_SECONDARY) == j)) {
|
||||
/* HPTE matches */
|
||||
if (j)
|
||||
slot = -slot;
|
||||
return slot;
|
||||
}
|
||||
++slot;
|
||||
}
|
||||
hash = ~hash;
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
static void beat_lpar_hpte_updateboltedpp(unsigned long newpp,
|
||||
unsigned long ea,
|
||||
int psize)
|
||||
{
|
||||
unsigned long lpar_rc, slot, vsid, va, dummy0, dummy1;
|
||||
unsigned long flags;
|
||||
|
||||
vsid = get_kernel_vsid(ea);
|
||||
va = (vsid << 28) | (ea & 0x0fffffff);
|
||||
|
||||
spin_lock_irqsave(&beat_htab_lock, flags);
|
||||
slot = beat_lpar_hpte_find(va, psize);
|
||||
BUG_ON(slot == -1);
|
||||
|
||||
lpar_rc = beat_write_htab_entry(0, slot, 0, newpp, 0, 7,
|
||||
&dummy0, &dummy1);
|
||||
spin_unlock_irqrestore(&beat_htab_lock, flags);
|
||||
|
||||
BUG_ON(lpar_rc != 0);
|
||||
}
|
||||
|
||||
static void beat_lpar_hpte_invalidate(unsigned long slot, unsigned long va,
|
||||
int psize, int local)
|
||||
{
|
||||
unsigned long want_v;
|
||||
unsigned long lpar_rc;
|
||||
unsigned long dummy1, dummy2;
|
||||
unsigned long flags;
|
||||
|
||||
DBG_LOW(" inval : slot=%lx, va=%016lx, psize: %d, local: %d\n",
|
||||
slot, va, psize, local);
|
||||
want_v = hpte_encode_v(va, psize);
|
||||
|
||||
spin_lock_irqsave(&beat_htab_lock, flags);
|
||||
dummy1 = beat_lpar_hpte_getword0(slot);
|
||||
|
||||
if ((dummy1 & ~0x7FUL) != (want_v & ~0x7FUL)) {
|
||||
DBG_LOW("not found !\n");
|
||||
spin_unlock_irqrestore(&beat_htab_lock, flags);
|
||||
return;
|
||||
}
|
||||
|
||||
lpar_rc = beat_write_htab_entry(0, slot, 0, 0, HPTE_V_VALID, 0,
|
||||
&dummy1, &dummy2);
|
||||
spin_unlock_irqrestore(&beat_htab_lock, flags);
|
||||
|
||||
BUG_ON(lpar_rc != 0);
|
||||
}
|
||||
|
||||
void __init hpte_init_beat(void)
|
||||
{
|
||||
ppc_md.hpte_invalidate = beat_lpar_hpte_invalidate;
|
||||
ppc_md.hpte_updatepp = beat_lpar_hpte_updatepp;
|
||||
ppc_md.hpte_updateboltedpp = beat_lpar_hpte_updateboltedpp;
|
||||
ppc_md.hpte_insert = beat_lpar_hpte_insert;
|
||||
ppc_md.hpte_remove = beat_lpar_hpte_remove;
|
||||
ppc_md.hpte_clear_all = beat_lpar_hptab_clear;
|
||||
}
|
||||
|
|
@ -0,0 +1,287 @@
|
|||
/*
|
||||
* Beat hypervisor call I/F
|
||||
*
|
||||
* (C) Copyright 2007 TOSHIBA CORPORATION
|
||||
*
|
||||
* This code is based on arch/powerpc/platforms/pseries/hvCall.S.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*/
|
||||
|
||||
#include <asm/ppc_asm.h>
|
||||
|
||||
#define STK_PARM(i) (48 + ((i)-3)*8)
|
||||
|
||||
/* Not implemented on Beat, now */
|
||||
#define HCALL_INST_PRECALL
|
||||
#define HCALL_INST_POSTCALL
|
||||
|
||||
.text
|
||||
|
||||
#define HVSC .long 0x44000022
|
||||
|
||||
/* Note: takes only 7 input parameters at maximum */
|
||||
_GLOBAL(beat_hcall_norets)
|
||||
HMT_MEDIUM
|
||||
|
||||
mfcr r0
|
||||
stw r0,8(r1)
|
||||
|
||||
HCALL_INST_PRECALL
|
||||
|
||||
mr r11,r3
|
||||
mr r3,r4
|
||||
mr r4,r5
|
||||
mr r5,r6
|
||||
mr r6,r7
|
||||
mr r7,r8
|
||||
mr r8,r9
|
||||
|
||||
HVSC /* invoke the hypervisor */
|
||||
|
||||
HCALL_INST_POSTCALL
|
||||
|
||||
lwz r0,8(r1)
|
||||
mtcrf 0xff,r0
|
||||
|
||||
blr /* return r3 = status */
|
||||
|
||||
/* Note: takes 8 input parameters at maximum */
|
||||
_GLOBAL(beat_hcall_norets8)
|
||||
HMT_MEDIUM
|
||||
|
||||
mfcr r0
|
||||
stw r0,8(r1)
|
||||
|
||||
HCALL_INST_PRECALL
|
||||
|
||||
mr r11,r3
|
||||
mr r3,r4
|
||||
mr r4,r5
|
||||
mr r5,r6
|
||||
mr r6,r7
|
||||
mr r7,r8
|
||||
mr r8,r9
|
||||
ld r10,STK_PARM(r10)(r1)
|
||||
|
||||
HVSC /* invoke the hypervisor */
|
||||
|
||||
HCALL_INST_POSTCALL
|
||||
|
||||
lwz r0,8(r1)
|
||||
mtcrf 0xff,r0
|
||||
|
||||
blr /* return r3 = status */
|
||||
|
||||
/* Note: takes only 6 input parameters, 1 output parameters at maximum */
|
||||
_GLOBAL(beat_hcall1)
|
||||
HMT_MEDIUM
|
||||
|
||||
mfcr r0
|
||||
stw r0,8(r1)
|
||||
|
||||
HCALL_INST_PRECALL
|
||||
|
||||
std r4,STK_PARM(r4)(r1) /* save ret buffer */
|
||||
|
||||
mr r11,r3
|
||||
mr r3,r5
|
||||
mr r4,r6
|
||||
mr r5,r7
|
||||
mr r6,r8
|
||||
mr r7,r9
|
||||
mr r8,r10
|
||||
|
||||
HVSC /* invoke the hypervisor */
|
||||
|
||||
HCALL_INST_POSTCALL
|
||||
|
||||
ld r12,STK_PARM(r4)(r1)
|
||||
std r4, 0(r12)
|
||||
|
||||
lwz r0,8(r1)
|
||||
mtcrf 0xff,r0
|
||||
|
||||
blr /* return r3 = status */
|
||||
|
||||
/* Note: takes only 6 input parameters, 2 output parameters at maximum */
|
||||
_GLOBAL(beat_hcall2)
|
||||
HMT_MEDIUM
|
||||
|
||||
mfcr r0
|
||||
stw r0,8(r1)
|
||||
|
||||
HCALL_INST_PRECALL
|
||||
|
||||
std r4,STK_PARM(r4)(r1) /* save ret buffer */
|
||||
|
||||
mr r11,r3
|
||||
mr r3,r5
|
||||
mr r4,r6
|
||||
mr r5,r7
|
||||
mr r6,r8
|
||||
mr r7,r9
|
||||
mr r8,r10
|
||||
|
||||
HVSC /* invoke the hypervisor */
|
||||
|
||||
HCALL_INST_POSTCALL
|
||||
|
||||
ld r12,STK_PARM(r4)(r1)
|
||||
std r4, 0(r12)
|
||||
std r5, 8(r12)
|
||||
|
||||
lwz r0,8(r1)
|
||||
mtcrf 0xff,r0
|
||||
|
||||
blr /* return r3 = status */
|
||||
|
||||
/* Note: takes only 6 input parameters, 3 output parameters at maximum */
|
||||
_GLOBAL(beat_hcall3)
|
||||
HMT_MEDIUM
|
||||
|
||||
mfcr r0
|
||||
stw r0,8(r1)
|
||||
|
||||
HCALL_INST_PRECALL
|
||||
|
||||
std r4,STK_PARM(r4)(r1) /* save ret buffer */
|
||||
|
||||
mr r11,r3
|
||||
mr r3,r5
|
||||
mr r4,r6
|
||||
mr r5,r7
|
||||
mr r6,r8
|
||||
mr r7,r9
|
||||
mr r8,r10
|
||||
|
||||
HVSC /* invoke the hypervisor */
|
||||
|
||||
HCALL_INST_POSTCALL
|
||||
|
||||
ld r12,STK_PARM(r4)(r1)
|
||||
std r4, 0(r12)
|
||||
std r5, 8(r12)
|
||||
std r6, 16(r12)
|
||||
|
||||
lwz r0,8(r1)
|
||||
mtcrf 0xff,r0
|
||||
|
||||
blr /* return r3 = status */
|
||||
|
||||
/* Note: takes only 6 input parameters, 4 output parameters at maximum */
|
||||
_GLOBAL(beat_hcall4)
|
||||
HMT_MEDIUM
|
||||
|
||||
mfcr r0
|
||||
stw r0,8(r1)
|
||||
|
||||
HCALL_INST_PRECALL
|
||||
|
||||
std r4,STK_PARM(r4)(r1) /* save ret buffer */
|
||||
|
||||
mr r11,r3
|
||||
mr r3,r5
|
||||
mr r4,r6
|
||||
mr r5,r7
|
||||
mr r6,r8
|
||||
mr r7,r9
|
||||
mr r8,r10
|
||||
|
||||
HVSC /* invoke the hypervisor */
|
||||
|
||||
HCALL_INST_POSTCALL
|
||||
|
||||
ld r12,STK_PARM(r4)(r1)
|
||||
std r4, 0(r12)
|
||||
std r5, 8(r12)
|
||||
std r6, 16(r12)
|
||||
std r7, 24(r12)
|
||||
|
||||
lwz r0,8(r1)
|
||||
mtcrf 0xff,r0
|
||||
|
||||
blr /* return r3 = status */
|
||||
|
||||
/* Note: takes only 6 input parameters, 5 output parameters at maximum */
|
||||
_GLOBAL(beat_hcall5)
|
||||
HMT_MEDIUM
|
||||
|
||||
mfcr r0
|
||||
stw r0,8(r1)
|
||||
|
||||
HCALL_INST_PRECALL
|
||||
|
||||
std r4,STK_PARM(r4)(r1) /* save ret buffer */
|
||||
|
||||
mr r11,r3
|
||||
mr r3,r5
|
||||
mr r4,r6
|
||||
mr r5,r7
|
||||
mr r6,r8
|
||||
mr r7,r9
|
||||
mr r8,r10
|
||||
|
||||
HVSC /* invoke the hypervisor */
|
||||
|
||||
HCALL_INST_POSTCALL
|
||||
|
||||
ld r12,STK_PARM(r4)(r1)
|
||||
std r4, 0(r12)
|
||||
std r5, 8(r12)
|
||||
std r6, 16(r12)
|
||||
std r7, 24(r12)
|
||||
std r8, 32(r12)
|
||||
|
||||
lwz r0,8(r1)
|
||||
mtcrf 0xff,r0
|
||||
|
||||
blr /* return r3 = status */
|
||||
|
||||
/* Note: takes only 6 input parameters, 6 output parameters at maximum */
|
||||
_GLOBAL(beat_hcall6)
|
||||
HMT_MEDIUM
|
||||
|
||||
mfcr r0
|
||||
stw r0,8(r1)
|
||||
|
||||
HCALL_INST_PRECALL
|
||||
|
||||
std r4,STK_PARM(r4)(r1) /* save ret buffer */
|
||||
|
||||
mr r11,r3
|
||||
mr r3,r5
|
||||
mr r4,r6
|
||||
mr r5,r7
|
||||
mr r6,r8
|
||||
mr r7,r9
|
||||
mr r8,r10
|
||||
|
||||
HVSC /* invoke the hypervisor */
|
||||
|
||||
HCALL_INST_POSTCALL
|
||||
|
||||
ld r12,STK_PARM(r4)(r1)
|
||||
std r4, 0(r12)
|
||||
std r5, 8(r12)
|
||||
std r6, 16(r12)
|
||||
std r7, 24(r12)
|
||||
std r8, 32(r12)
|
||||
std r9, 40(r12)
|
||||
|
||||
lwz r0,8(r1)
|
||||
mtcrf 0xff,r0
|
||||
|
||||
blr /* return r3 = status */
|
||||
|
|
@ -0,0 +1,274 @@
|
|||
/*
|
||||
* Celleb/Beat Interrupt controller
|
||||
*
|
||||
* (C) Copyright 2006-2007 TOSHIBA CORPORATION
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/percpu.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#include <asm/machdep.h>
|
||||
|
||||
#include "interrupt.h"
|
||||
#include "beat_wrapper.h"
|
||||
|
||||
#define MAX_IRQS NR_IRQS
|
||||
static DEFINE_SPINLOCK(beatic_irq_mask_lock);
|
||||
static uint64_t beatic_irq_mask_enable[(MAX_IRQS+255)/64];
|
||||
static uint64_t beatic_irq_mask_ack[(MAX_IRQS+255)/64];
|
||||
|
||||
static struct irq_host *beatic_host = NULL;
|
||||
|
||||
/*
|
||||
* In this implementation, "virq" == "IRQ plug number",
|
||||
* "(irq_hw_number_t)hwirq" == "IRQ outlet number".
|
||||
*/
|
||||
|
||||
/* assumption: locked */
|
||||
static inline void beatic_update_irq_mask(unsigned int irq_plug)
|
||||
{
|
||||
int off;
|
||||
unsigned long masks[4];
|
||||
|
||||
off = (irq_plug / 256) * 4;
|
||||
masks[0] = beatic_irq_mask_enable[off + 0]
|
||||
& beatic_irq_mask_ack[off + 0];
|
||||
masks[1] = beatic_irq_mask_enable[off + 1]
|
||||
& beatic_irq_mask_ack[off + 1];
|
||||
masks[2] = beatic_irq_mask_enable[off + 2]
|
||||
& beatic_irq_mask_ack[off + 2];
|
||||
masks[3] = beatic_irq_mask_enable[off + 3]
|
||||
& beatic_irq_mask_ack[off + 3];
|
||||
if (beat_set_interrupt_mask(irq_plug&~255UL,
|
||||
masks[0], masks[1], masks[2], masks[3]) != 0)
|
||||
panic("Failed to set mask IRQ!");
|
||||
}
|
||||
|
||||
static void beatic_mask_irq(unsigned int irq_plug)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&beatic_irq_mask_lock, flags);
|
||||
beatic_irq_mask_enable[irq_plug/64] &= ~(1UL << (63 - (irq_plug%64)));
|
||||
beatic_update_irq_mask(irq_plug);
|
||||
spin_unlock_irqrestore(&beatic_irq_mask_lock, flags);
|
||||
}
|
||||
|
||||
static void beatic_unmask_irq(unsigned int irq_plug)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&beatic_irq_mask_lock, flags);
|
||||
beatic_irq_mask_enable[irq_plug/64] |= 1UL << (63 - (irq_plug%64));
|
||||
beatic_update_irq_mask(irq_plug);
|
||||
spin_unlock_irqrestore(&beatic_irq_mask_lock, flags);
|
||||
}
|
||||
|
||||
static void beatic_ack_irq(unsigned int irq_plug)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&beatic_irq_mask_lock, flags);
|
||||
beatic_irq_mask_ack[irq_plug/64] &= ~(1UL << (63 - (irq_plug%64)));
|
||||
beatic_update_irq_mask(irq_plug);
|
||||
spin_unlock_irqrestore(&beatic_irq_mask_lock, flags);
|
||||
}
|
||||
|
||||
static void beatic_end_irq(unsigned int irq_plug)
|
||||
{
|
||||
s64 err;
|
||||
unsigned long flags;
|
||||
|
||||
if ((err = beat_downcount_of_interrupt(irq_plug)) != 0) {
|
||||
if ((err & 0xFFFFFFFF) != 0xFFFFFFF5) /* -11: wrong state */
|
||||
panic("Failed to downcount IRQ! Error = %16lx", err);
|
||||
|
||||
printk(KERN_ERR "IRQ over-downcounted, plug %d\n", irq_plug);
|
||||
}
|
||||
spin_lock_irqsave(&beatic_irq_mask_lock, flags);
|
||||
beatic_irq_mask_ack[irq_plug/64] |= 1UL << (63 - (irq_plug%64));
|
||||
beatic_update_irq_mask(irq_plug);
|
||||
spin_unlock_irqrestore(&beatic_irq_mask_lock, flags);
|
||||
}
|
||||
|
||||
static struct irq_chip beatic_pic = {
|
||||
.typename = " CELL-BEAT ",
|
||||
.unmask = beatic_unmask_irq,
|
||||
.mask = beatic_mask_irq,
|
||||
.eoi = beatic_end_irq,
|
||||
};
|
||||
|
||||
/*
|
||||
* Dispose binding hardware IRQ number (hw) and Virtuql IRQ number (virq),
|
||||
* update flags.
|
||||
*
|
||||
* Note that the number (virq) is already assigned at upper layer.
|
||||
*/
|
||||
static void beatic_pic_host_unmap(struct irq_host *h, unsigned int virq)
|
||||
{
|
||||
beat_destruct_irq_plug(virq);
|
||||
}
|
||||
|
||||
/*
|
||||
* Create or update binding hardware IRQ number (hw) and Virtuql
|
||||
* IRQ number (virq). This is called only once for a given mapping.
|
||||
*
|
||||
* Note that the number (virq) is already assigned at upper layer.
|
||||
*/
|
||||
static int beatic_pic_host_map(struct irq_host *h, unsigned int virq,
|
||||
irq_hw_number_t hw)
|
||||
{
|
||||
struct irq_desc *desc = get_irq_desc(virq);
|
||||
int64_t err;
|
||||
|
||||
if ((err = beat_construct_and_connect_irq_plug(virq, hw)) < 0)
|
||||
return -EIO;
|
||||
|
||||
desc->status |= IRQ_LEVEL;
|
||||
set_irq_chip_and_handler(virq, &beatic_pic, handle_fasteoi_irq);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Update binding hardware IRQ number (hw) and Virtuql
|
||||
* IRQ number (virq). This is called only once for a given mapping.
|
||||
*/
|
||||
static void beatic_pic_host_remap(struct irq_host *h, unsigned int virq,
|
||||
irq_hw_number_t hw)
|
||||
{
|
||||
beat_construct_and_connect_irq_plug(virq, hw);
|
||||
}
|
||||
|
||||
/*
|
||||
* Translate device-tree interrupt spec to irq_hw_number_t style (ulong),
|
||||
* to pass away to irq_create_mapping().
|
||||
*
|
||||
* Called from irq_create_of_mapping() only.
|
||||
* Note: We have only 1 entry to translate.
|
||||
*/
|
||||
static int beatic_pic_host_xlate(struct irq_host *h, struct device_node *ct,
|
||||
u32 *intspec, unsigned int intsize,
|
||||
irq_hw_number_t *out_hwirq,
|
||||
unsigned int *out_flags)
|
||||
{
|
||||
u64 *intspec2 = (u64 *)intspec;
|
||||
|
||||
*out_hwirq = *intspec2;
|
||||
*out_flags |= IRQ_TYPE_LEVEL_LOW;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct irq_host_ops beatic_pic_host_ops = {
|
||||
.map = beatic_pic_host_map,
|
||||
.remap = beatic_pic_host_remap,
|
||||
.unmap = beatic_pic_host_unmap,
|
||||
.xlate = beatic_pic_host_xlate,
|
||||
};
|
||||
|
||||
/*
|
||||
* Get an IRQ number
|
||||
* Note: returns VIRQ
|
||||
*/
|
||||
static inline unsigned int beatic_get_irq_plug(void)
|
||||
{
|
||||
int i;
|
||||
uint64_t pending[4], ub;
|
||||
|
||||
for (i = 0; i < MAX_IRQS; i += 256) {
|
||||
beat_detect_pending_interrupts(i, pending);
|
||||
__asm__ ("cntlzd %0,%1":"=r"(ub):
|
||||
"r"(pending[0] & beatic_irq_mask_enable[i/64+0]
|
||||
& beatic_irq_mask_ack[i/64+0]));
|
||||
if (ub != 64)
|
||||
return i + ub + 0;
|
||||
__asm__ ("cntlzd %0,%1":"=r"(ub):
|
||||
"r"(pending[1] & beatic_irq_mask_enable[i/64+1]
|
||||
& beatic_irq_mask_ack[i/64+1]));
|
||||
if (ub != 64)
|
||||
return i + ub + 64;
|
||||
__asm__ ("cntlzd %0,%1":"=r"(ub):
|
||||
"r"(pending[2] & beatic_irq_mask_enable[i/64+2]
|
||||
& beatic_irq_mask_ack[i/64+2]));
|
||||
if (ub != 64)
|
||||
return i + ub + 128;
|
||||
__asm__ ("cntlzd %0,%1":"=r"(ub):
|
||||
"r"(pending[3] & beatic_irq_mask_enable[i/64+3]
|
||||
& beatic_irq_mask_ack[i/64+3]));
|
||||
if (ub != 64)
|
||||
return i + ub + 192;
|
||||
}
|
||||
|
||||
return NO_IRQ;
|
||||
}
|
||||
unsigned int beatic_get_irq(void)
|
||||
{
|
||||
unsigned int ret;
|
||||
|
||||
ret = beatic_get_irq_plug();
|
||||
if (ret != NO_IRQ)
|
||||
beatic_ack_irq(ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
*/
|
||||
void __init beatic_init_IRQ(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
memset(beatic_irq_mask_enable, 0, sizeof(beatic_irq_mask_enable));
|
||||
memset(beatic_irq_mask_ack, 255, sizeof(beatic_irq_mask_ack));
|
||||
for (i = 0; i < MAX_IRQS; i += 256)
|
||||
beat_set_interrupt_mask(i, 0L, 0L, 0L, 0L);
|
||||
|
||||
/* Set out get_irq function */
|
||||
ppc_md.get_irq = beatic_get_irq;
|
||||
|
||||
/* Allocate an irq host */
|
||||
beatic_host = irq_alloc_host(IRQ_HOST_MAP_NOMAP, 0,
|
||||
&beatic_pic_host_ops,
|
||||
0);
|
||||
BUG_ON(beatic_host == NULL);
|
||||
irq_set_default_host(beatic_host);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
|
||||
/* Nullified to compile with SMP mode */
|
||||
void beatic_setup_cpu(int cpu)
|
||||
{
|
||||
}
|
||||
|
||||
void beatic_cause_IPI(int cpu, int mesg)
|
||||
{
|
||||
}
|
||||
|
||||
void beatic_request_IPIs(void)
|
||||
{
|
||||
}
|
||||
#endif /* CONFIG_SMP */
|
||||
|
||||
void beatic_deinit_IRQ(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 1; i < NR_IRQS; i++)
|
||||
beat_destruct_irq_plug(i);
|
||||
}
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
/*
|
||||
* Celleb/Beat Interrupt controller
|
||||
*
|
||||
* (C) Copyright 2006 TOSHIBA CORPORATION
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*/
|
||||
|
||||
#ifndef ASM_BEAT_PIC_H
|
||||
#define ASM_BEAT_PIC_H
|
||||
#ifdef __KERNEL__
|
||||
|
||||
extern void beatic_init_IRQ(void);
|
||||
extern unsigned int beatic_get_irq(void);
|
||||
extern void beatic_cause_IPI(int cpu, int mesg);
|
||||
extern void beatic_request_IPIs(void);
|
||||
extern void beatic_setup_cpu(int);
|
||||
extern void beatic_deinit_IRQ(void);
|
||||
|
||||
#endif
|
||||
#endif /* ASM_BEAT_PIC_H */
|
||||
|
|
@ -0,0 +1,104 @@
|
|||
/*
|
||||
* Support for IOMMU on Celleb platform.
|
||||
*
|
||||
* (C) Copyright 2006-2007 TOSHIBA CORPORATION
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/pci.h>
|
||||
|
||||
#include <asm/of_platform.h>
|
||||
|
||||
#include "beat_wrapper.h"
|
||||
|
||||
#define DMA_FLAGS 0xf800000000000000UL /* r/w permitted, coherency required,
|
||||
strongest order */
|
||||
|
||||
static int __init find_dma_window(u64 *io_space_id, u64 *ioid,
|
||||
u64 *base, u64 *size, u64 *io_page_size)
|
||||
{
|
||||
struct device_node *dn;
|
||||
const unsigned long *dma_window;
|
||||
|
||||
for_each_node_by_type(dn, "ioif") {
|
||||
dma_window = get_property(dn, "toshiba,dma-window", NULL);
|
||||
if (dma_window) {
|
||||
*io_space_id = (dma_window[0] >> 32) & 0xffffffffUL;
|
||||
*ioid = dma_window[0] & 0x7ffUL;
|
||||
*base = dma_window[1];
|
||||
*size = dma_window[2];
|
||||
*io_page_size = 1 << dma_window[3];
|
||||
of_node_put(dn);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __init celleb_init_direct_mapping(void)
|
||||
{
|
||||
u64 lpar_addr, io_addr;
|
||||
u64 io_space_id, ioid, dma_base, dma_size, io_page_size;
|
||||
|
||||
if (!find_dma_window(&io_space_id, &ioid, &dma_base, &dma_size,
|
||||
&io_page_size)) {
|
||||
pr_info("No dma window found !\n");
|
||||
return;
|
||||
}
|
||||
|
||||
for (lpar_addr = 0; lpar_addr < dma_size; lpar_addr += io_page_size) {
|
||||
io_addr = lpar_addr + dma_base;
|
||||
(void)beat_put_iopte(io_space_id, io_addr, lpar_addr,
|
||||
ioid, DMA_FLAGS);
|
||||
}
|
||||
|
||||
dma_direct_offset = dma_base;
|
||||
}
|
||||
|
||||
static int celleb_of_bus_notify(struct notifier_block *nb,
|
||||
unsigned long action, void *data)
|
||||
{
|
||||
struct device *dev = data;
|
||||
|
||||
/* We are only intereted in device addition */
|
||||
if (action != BUS_NOTIFY_ADD_DEVICE)
|
||||
return 0;
|
||||
|
||||
dev->archdata.dma_ops = pci_dma_ops;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct notifier_block celleb_of_bus_notifier = {
|
||||
.notifier_call = celleb_of_bus_notify
|
||||
};
|
||||
|
||||
static int __init celleb_init_iommu(void)
|
||||
{
|
||||
if (!machine_is(celleb))
|
||||
return -ENODEV;
|
||||
|
||||
celleb_init_direct_mapping();
|
||||
pci_dma_ops = &dma_direct_ops;
|
||||
bus_register_notifier(&of_platform_bus_type, &celleb_of_bus_notifier);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
arch_initcall(celleb_init_iommu);
|
||||
|
|
@ -0,0 +1,481 @@
|
|||
/*
|
||||
* Support for PCI on Celleb platform.
|
||||
*
|
||||
* (C) Copyright 2006-2007 TOSHIBA CORPORATION
|
||||
*
|
||||
* This code is based on arch/powerpc/kernel/rtas_pci.c:
|
||||
* Copyright (C) 2001 Dave Engebretsen, IBM Corporation
|
||||
* Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*/
|
||||
|
||||
#undef DEBUG
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/threads.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/bootmem.h>
|
||||
#include <linux/pci_regs.h>
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/prom.h>
|
||||
#include <asm/machdep.h>
|
||||
#include <asm/pci-bridge.h>
|
||||
#include <asm/ppc-pci.h>
|
||||
|
||||
#include "pci.h"
|
||||
#include "interrupt.h"
|
||||
|
||||
#define MAX_PCI_DEVICES 32
|
||||
#define MAX_PCI_FUNCTIONS 8
|
||||
#define MAX_PCI_BASE_ADDRS 3 /* use 64 bit address */
|
||||
|
||||
/* definition for fake pci configuration area for GbE, .... ,and etc. */
|
||||
|
||||
struct celleb_pci_resource {
|
||||
struct resource r[MAX_PCI_BASE_ADDRS];
|
||||
};
|
||||
|
||||
struct celleb_pci_private {
|
||||
unsigned char *fake_config[MAX_PCI_DEVICES][MAX_PCI_FUNCTIONS];
|
||||
struct celleb_pci_resource *res[MAX_PCI_DEVICES][MAX_PCI_FUNCTIONS];
|
||||
};
|
||||
|
||||
static inline u8 celleb_fake_config_readb(void *addr)
|
||||
{
|
||||
u8 *p = addr;
|
||||
return *p;
|
||||
}
|
||||
|
||||
static inline u16 celleb_fake_config_readw(void *addr)
|
||||
{
|
||||
u16 *p = addr;
|
||||
return le16_to_cpu(*p);
|
||||
}
|
||||
|
||||
static inline u32 celleb_fake_config_readl(void *addr)
|
||||
{
|
||||
u32 *p = addr;
|
||||
return le32_to_cpu(*p);
|
||||
}
|
||||
|
||||
static inline void celleb_fake_config_writeb(u32 val, void *addr)
|
||||
{
|
||||
u8 *p = addr;
|
||||
*p = val;
|
||||
}
|
||||
|
||||
static inline void celleb_fake_config_writew(u32 val, void *addr)
|
||||
{
|
||||
u16 val16;
|
||||
u16 *p = addr;
|
||||
val16 = cpu_to_le16(val);
|
||||
*p = val16;
|
||||
}
|
||||
|
||||
static inline void celleb_fake_config_writel(u32 val, void *addr)
|
||||
{
|
||||
u32 val32;
|
||||
u32 *p = addr;
|
||||
val32 = cpu_to_le32(val);
|
||||
*p = val32;
|
||||
}
|
||||
|
||||
static unsigned char *get_fake_config_start(struct pci_controller *hose,
|
||||
int devno, int fn)
|
||||
{
|
||||
struct celleb_pci_private *private = hose->private_data;
|
||||
|
||||
if (private == NULL)
|
||||
return NULL;
|
||||
|
||||
return private->fake_config[devno][fn];
|
||||
}
|
||||
|
||||
static struct celleb_pci_resource *get_resource_start(
|
||||
struct pci_controller *hose,
|
||||
int devno, int fn)
|
||||
{
|
||||
struct celleb_pci_private *private = hose->private_data;
|
||||
|
||||
if (private == NULL)
|
||||
return NULL;
|
||||
|
||||
return private->res[devno][fn];
|
||||
}
|
||||
|
||||
|
||||
static void celleb_config_read_fake(unsigned char *config, int where,
|
||||
int size, u32 *val)
|
||||
{
|
||||
char *p = config + where;
|
||||
|
||||
switch (size) {
|
||||
case 1:
|
||||
*val = celleb_fake_config_readb(p);
|
||||
break;
|
||||
case 2:
|
||||
*val = celleb_fake_config_readw(p);
|
||||
break;
|
||||
case 4:
|
||||
*val = celleb_fake_config_readl(p);
|
||||
break;
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static void celleb_config_write_fake(unsigned char *config, int where,
|
||||
int size, u32 val)
|
||||
{
|
||||
char *p = config + where;
|
||||
|
||||
switch (size) {
|
||||
case 1:
|
||||
celleb_fake_config_writeb(val, p);
|
||||
break;
|
||||
case 2:
|
||||
celleb_fake_config_writew(val, p);
|
||||
break;
|
||||
case 4:
|
||||
celleb_fake_config_writel(val, p);
|
||||
break;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
static int celleb_fake_pci_read_config(struct pci_bus *bus,
|
||||
unsigned int devfn, int where, int size, u32 *val)
|
||||
{
|
||||
char *config;
|
||||
struct device_node *node;
|
||||
struct pci_controller *hose;
|
||||
unsigned int devno = devfn >> 3;
|
||||
unsigned int fn = devfn & 0x7;
|
||||
|
||||
/* allignment check */
|
||||
BUG_ON(where % size);
|
||||
|
||||
pr_debug(" fake read: bus=0x%x, ", bus->number);
|
||||
node = (struct device_node *)bus->sysdata;
|
||||
hose = pci_find_hose_for_OF_device(node);
|
||||
config = get_fake_config_start(hose, devno, fn);
|
||||
|
||||
pr_debug("devno=0x%x, where=0x%x, size=0x%x, ", devno, where, size);
|
||||
if (!config) {
|
||||
pr_debug("failed\n");
|
||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
}
|
||||
|
||||
celleb_config_read_fake(config, where, size, val);
|
||||
pr_debug("val=0x%x\n", *val);
|
||||
|
||||
return PCIBIOS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
|
||||
static int celleb_fake_pci_write_config(struct pci_bus *bus,
|
||||
unsigned int devfn, int where, int size, u32 val)
|
||||
{
|
||||
char *config;
|
||||
struct device_node *node;
|
||||
struct pci_controller *hose;
|
||||
struct celleb_pci_resource *res;
|
||||
unsigned int devno = devfn >> 3;
|
||||
unsigned int fn = devfn & 0x7;
|
||||
|
||||
/* allignment check */
|
||||
BUG_ON(where % size);
|
||||
|
||||
node = (struct device_node *)bus->sysdata;
|
||||
hose = pci_find_hose_for_OF_device(node);
|
||||
config = get_fake_config_start(hose, devno, fn);
|
||||
|
||||
if (!config)
|
||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
|
||||
if (val == ~0) {
|
||||
int i = (where - PCI_BASE_ADDRESS_0) >> 3;
|
||||
|
||||
switch (where) {
|
||||
case PCI_BASE_ADDRESS_0:
|
||||
case PCI_BASE_ADDRESS_2:
|
||||
if (size != 4)
|
||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
res = get_resource_start(hose, devno, fn);
|
||||
if (!res)
|
||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
celleb_config_write_fake(config, where, size,
|
||||
(res->r[i].end - res->r[i].start));
|
||||
return PCIBIOS_SUCCESSFUL;
|
||||
case PCI_BASE_ADDRESS_1:
|
||||
case PCI_BASE_ADDRESS_3:
|
||||
case PCI_BASE_ADDRESS_4:
|
||||
case PCI_BASE_ADDRESS_5:
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
celleb_config_write_fake(config, where, size, val);
|
||||
pr_debug(" fake write: where=%x, size=%d, val=%x\n",
|
||||
where, size, val);
|
||||
|
||||
return PCIBIOS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
static struct pci_ops celleb_fake_pci_ops = {
|
||||
celleb_fake_pci_read_config,
|
||||
celleb_fake_pci_write_config
|
||||
};
|
||||
|
||||
static inline void celleb_setup_pci_base_addrs(struct pci_controller *hose,
|
||||
unsigned int devno, unsigned int fn,
|
||||
unsigned int num_base_addr)
|
||||
{
|
||||
u32 val;
|
||||
unsigned char *config;
|
||||
struct celleb_pci_resource *res;
|
||||
|
||||
config = get_fake_config_start(hose, devno, fn);
|
||||
res = get_resource_start(hose, devno, fn);
|
||||
|
||||
if (!config || !res)
|
||||
return;
|
||||
|
||||
switch (num_base_addr) {
|
||||
case 3:
|
||||
val = (res->r[2].start & 0xfffffff0)
|
||||
| PCI_BASE_ADDRESS_MEM_TYPE_64;
|
||||
celleb_config_write_fake(config, PCI_BASE_ADDRESS_4, 4, val);
|
||||
val = res->r[2].start >> 32;
|
||||
celleb_config_write_fake(config, PCI_BASE_ADDRESS_5, 4, val);
|
||||
/* FALLTHROUGH */
|
||||
case 2:
|
||||
val = (res->r[1].start & 0xfffffff0)
|
||||
| PCI_BASE_ADDRESS_MEM_TYPE_64;
|
||||
celleb_config_write_fake(config, PCI_BASE_ADDRESS_2, 4, val);
|
||||
val = res->r[1].start >> 32;
|
||||
celleb_config_write_fake(config, PCI_BASE_ADDRESS_3, 4, val);
|
||||
/* FALLTHROUGH */
|
||||
case 1:
|
||||
val = (res->r[0].start & 0xfffffff0)
|
||||
| PCI_BASE_ADDRESS_MEM_TYPE_64;
|
||||
celleb_config_write_fake(config, PCI_BASE_ADDRESS_0, 4, val);
|
||||
val = res->r[0].start >> 32;
|
||||
celleb_config_write_fake(config, PCI_BASE_ADDRESS_1, 4, val);
|
||||
break;
|
||||
}
|
||||
|
||||
val = PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
|
||||
celleb_config_write_fake(config, PCI_COMMAND, 2, val);
|
||||
}
|
||||
|
||||
static int __devinit celleb_setup_fake_pci_device(struct device_node *node,
|
||||
struct pci_controller *hose)
|
||||
{
|
||||
unsigned int rlen;
|
||||
int num_base_addr = 0;
|
||||
u32 val;
|
||||
const u32 *wi0, *wi1, *wi2, *wi3, *wi4;
|
||||
unsigned int devno, fn;
|
||||
struct celleb_pci_private *private = hose->private_data;
|
||||
unsigned char **config = NULL;
|
||||
struct celleb_pci_resource **res = NULL;
|
||||
const char *name;
|
||||
const unsigned long *li;
|
||||
int size, result;
|
||||
|
||||
if (private == NULL) {
|
||||
printk(KERN_ERR "PCI: "
|
||||
"memory space for pci controller is not assigned\n");
|
||||
goto error;
|
||||
}
|
||||
|
||||
name = get_property(node, "model", &rlen);
|
||||
if (!name) {
|
||||
printk(KERN_ERR "PCI: model property not found.\n");
|
||||
goto error;
|
||||
}
|
||||
|
||||
wi4 = get_property(node, "reg", &rlen);
|
||||
if (wi4 == NULL)
|
||||
goto error;
|
||||
|
||||
devno = ((wi4[0] >> 8) & 0xff) >> 3;
|
||||
fn = (wi4[0] >> 8) & 0x7;
|
||||
|
||||
pr_debug("PCI: celleb_setup_fake_pci() %s devno=%x fn=%x\n", name,
|
||||
devno, fn);
|
||||
|
||||
size = 256;
|
||||
config = &private->fake_config[devno][fn];
|
||||
if (mem_init_done)
|
||||
*config = kzalloc(size, GFP_KERNEL);
|
||||
else
|
||||
*config = alloc_bootmem(size);
|
||||
if (*config == NULL) {
|
||||
printk(KERN_ERR "PCI: "
|
||||
"not enough memory for fake configuration space\n");
|
||||
goto error;
|
||||
}
|
||||
pr_debug("PCI: fake config area assigned 0x%016lx\n",
|
||||
(unsigned long)*config);
|
||||
|
||||
size = sizeof(struct celleb_pci_resource);
|
||||
res = &private->res[devno][fn];
|
||||
if (mem_init_done)
|
||||
*res = kzalloc(size, GFP_KERNEL);
|
||||
else
|
||||
*res = alloc_bootmem(size);
|
||||
if (*res == NULL) {
|
||||
printk(KERN_ERR
|
||||
"PCI: not enough memory for resource data space\n");
|
||||
goto error;
|
||||
}
|
||||
pr_debug("PCI: res assigned 0x%016lx\n", (unsigned long)*res);
|
||||
|
||||
wi0 = get_property(node, "device-id", NULL);
|
||||
wi1 = get_property(node, "vendor-id", NULL);
|
||||
wi2 = get_property(node, "class-code", NULL);
|
||||
wi3 = get_property(node, "revision-id", NULL);
|
||||
|
||||
celleb_config_write_fake(*config, PCI_DEVICE_ID, 2, wi0[0] & 0xffff);
|
||||
celleb_config_write_fake(*config, PCI_VENDOR_ID, 2, wi1[0] & 0xffff);
|
||||
pr_debug("class-code = 0x%08x\n", wi2[0]);
|
||||
|
||||
celleb_config_write_fake(*config, PCI_CLASS_PROG, 1, wi2[0] & 0xff);
|
||||
celleb_config_write_fake(*config, PCI_CLASS_DEVICE, 2,
|
||||
(wi2[0] >> 8) & 0xffff);
|
||||
celleb_config_write_fake(*config, PCI_REVISION_ID, 1, wi3[0]);
|
||||
|
||||
while (num_base_addr < MAX_PCI_BASE_ADDRS) {
|
||||
result = of_address_to_resource(node,
|
||||
num_base_addr, &(*res)->r[num_base_addr]);
|
||||
if (result)
|
||||
break;
|
||||
num_base_addr++;
|
||||
}
|
||||
|
||||
celleb_setup_pci_base_addrs(hose, devno, fn, num_base_addr);
|
||||
|
||||
li = get_property(node, "interrupts", &rlen);
|
||||
val = li[0];
|
||||
celleb_config_write_fake(*config, PCI_INTERRUPT_PIN, 1, 1);
|
||||
celleb_config_write_fake(*config, PCI_INTERRUPT_LINE, 1, val);
|
||||
|
||||
#ifdef DEBUG
|
||||
pr_debug("PCI: %s irq=%ld\n", name, li[0]);
|
||||
for (i = 0; i < 6; i++) {
|
||||
celleb_config_read_fake(*config,
|
||||
PCI_BASE_ADDRESS_0 + 0x4 * i, 4,
|
||||
&val);
|
||||
pr_debug("PCI: %s fn=%d base_address_%d=0x%x\n",
|
||||
name, fn, i, val);
|
||||
}
|
||||
#endif
|
||||
|
||||
celleb_config_write_fake(*config, PCI_HEADER_TYPE, 1,
|
||||
PCI_HEADER_TYPE_NORMAL);
|
||||
|
||||
return 0;
|
||||
|
||||
error:
|
||||
if (mem_init_done) {
|
||||
if (config && *config)
|
||||
kfree(*config);
|
||||
if (res && *res)
|
||||
kfree(*res);
|
||||
|
||||
} else {
|
||||
if (config && *config) {
|
||||
size = 256;
|
||||
free_bootmem((unsigned long)(*config), size);
|
||||
}
|
||||
if (res && *res) {
|
||||
size = sizeof(struct celleb_pci_resource);
|
||||
free_bootmem((unsigned long)(*res), size);
|
||||
}
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int __devinit phb_set_bus_ranges(struct device_node *dev,
|
||||
struct pci_controller *phb)
|
||||
{
|
||||
const int *bus_range;
|
||||
unsigned int len;
|
||||
|
||||
bus_range = get_property(dev, "bus-range", &len);
|
||||
if (bus_range == NULL || len < 2 * sizeof(int))
|
||||
return 1;
|
||||
|
||||
phb->first_busno = bus_range[0];
|
||||
phb->last_busno = bus_range[1];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __devinit celleb_alloc_private_mem(struct pci_controller *hose)
|
||||
{
|
||||
if (mem_init_done)
|
||||
hose->private_data =
|
||||
kzalloc(sizeof(struct celleb_pci_private), GFP_KERNEL);
|
||||
else
|
||||
hose->private_data =
|
||||
alloc_bootmem(sizeof(struct celleb_pci_private));
|
||||
}
|
||||
|
||||
int __devinit celleb_setup_phb(struct pci_controller *phb)
|
||||
{
|
||||
const char *name;
|
||||
struct device_node *dev = phb->arch_data;
|
||||
struct device_node *node;
|
||||
unsigned int rlen;
|
||||
|
||||
name = get_property(dev, "name", &rlen);
|
||||
if (!name)
|
||||
return 1;
|
||||
|
||||
pr_debug("PCI: celleb_setup_phb() %s\n", name);
|
||||
phb_set_bus_ranges(dev, phb);
|
||||
|
||||
if (strcmp(name, "epci") == 0) {
|
||||
phb->ops = &celleb_epci_ops;
|
||||
return celleb_setup_epci(dev, phb);
|
||||
|
||||
} else if (strcmp(name, "pci-pseudo") == 0) {
|
||||
phb->ops = &celleb_fake_pci_ops;
|
||||
celleb_alloc_private_mem(phb);
|
||||
for (node = of_get_next_child(dev, NULL);
|
||||
node != NULL; node = of_get_next_child(dev, node))
|
||||
celleb_setup_fake_pci_device(node, phb);
|
||||
|
||||
} else
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int celleb_pci_probe_mode(struct pci_bus *bus)
|
||||
{
|
||||
return PCI_PROBE_DEVTREE;
|
||||
}
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
/*
|
||||
* pci prototypes for Celleb platform
|
||||
*
|
||||
* (C) Copyright 2006-2007 TOSHIBA CORPORATION
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*/
|
||||
|
||||
#ifndef _CELLEB_PCI_H
|
||||
#define _CELLEB_PCI_H
|
||||
|
||||
#include <linux/pci.h>
|
||||
|
||||
#include <asm/pci-bridge.h>
|
||||
#include <asm/prom.h>
|
||||
|
||||
extern int celleb_setup_phb(struct pci_controller *);
|
||||
extern int celleb_pci_probe_mode(struct pci_bus *);
|
||||
|
||||
extern struct pci_ops celleb_epci_ops;
|
||||
extern int celleb_setup_epci(struct device_node *, struct pci_controller *);
|
||||
|
||||
#endif /* _CELLEB_PCI_H */
|
||||
|
|
@ -0,0 +1,145 @@
|
|||
/*
|
||||
* SCC (Super Companion Chip) definitions
|
||||
*
|
||||
* (C) Copyright 2004-2006 TOSHIBA CORPORATION
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*/
|
||||
|
||||
#ifndef _CELLEB_SCC_H
|
||||
#define _CELLEB_SCC_H
|
||||
|
||||
#define PCI_VENDOR_ID_TOSHIBA_2 0x102f
|
||||
#define PCI_DEVICE_ID_TOSHIBA_SCC_PCIEXC_BRIDGE 0x01b0
|
||||
#define PCI_DEVICE_ID_TOSHIBA_SCC_EPCI_BRIDGE 0x01b1
|
||||
#define PCI_DEVICE_ID_TOSHIBA_SCC_BRIDGE 0x01b2
|
||||
#define PCI_DEVICE_ID_TOSHIBA_SCC_GBE 0x01b3
|
||||
#define PCI_DEVICE_ID_TOSHIBA_SCC_ATA 0x01b4
|
||||
#define PCI_DEVICE_ID_TOSHIBA_SCC_USB2 0x01b5
|
||||
#define PCI_DEVICE_ID_TOSHIBA_SCC_USB 0x01b6
|
||||
#define PCI_DEVICE_ID_TOSHIBA_SCC_ENCDEC 0x01b7
|
||||
|
||||
#define SCC_EPCI_REG 0x0000d000
|
||||
|
||||
/* EPCI registers */
|
||||
#define SCC_EPCI_CNF10_REG 0x010
|
||||
#define SCC_EPCI_CNF14_REG 0x014
|
||||
#define SCC_EPCI_CNF18_REG 0x018
|
||||
#define SCC_EPCI_PVBAT 0x100
|
||||
#define SCC_EPCI_VPMBAT 0x104
|
||||
#define SCC_EPCI_VPIBAT 0x108
|
||||
#define SCC_EPCI_VCSR 0x110
|
||||
#define SCC_EPCI_VIENAB 0x114
|
||||
#define SCC_EPCI_VISTAT 0x118
|
||||
#define SCC_EPCI_VRDCOUNT 0x124
|
||||
#define SCC_EPCI_BAM0 0x12c
|
||||
#define SCC_EPCI_BAM1 0x134
|
||||
#define SCC_EPCI_BAM2 0x13c
|
||||
#define SCC_EPCI_IADR 0x164
|
||||
#define SCC_EPCI_CLKRST 0x800
|
||||
#define SCC_EPCI_INTSET 0x804
|
||||
#define SCC_EPCI_STATUS 0x808
|
||||
#define SCC_EPCI_ABTSET 0x80c
|
||||
#define SCC_EPCI_WATRP 0x810
|
||||
#define SCC_EPCI_DUMMYRADR 0x814
|
||||
#define SCC_EPCI_SWRESP 0x818
|
||||
#define SCC_EPCI_CNTOPT 0x81c
|
||||
#define SCC_EPCI_ECMODE 0xf00
|
||||
#define SCC_EPCI_IOM_AC_NUM 5
|
||||
#define SCC_EPCI_IOM_ACTE(n) (0xf10 + (n) * 4)
|
||||
#define SCC_EPCI_IOT_AC_NUM 4
|
||||
#define SCC_EPCI_IOT_ACTE(n) (0xf30 + (n) * 4)
|
||||
#define SCC_EPCI_MAEA 0xf50
|
||||
#define SCC_EPCI_MAEC 0xf54
|
||||
#define SCC_EPCI_CKCTRL 0xff0
|
||||
|
||||
/* bits for SCC_EPCI_VCSR */
|
||||
#define SCC_EPCI_VCSR_FRE 0x00020000
|
||||
#define SCC_EPCI_VCSR_FWE 0x00010000
|
||||
#define SCC_EPCI_VCSR_DR 0x00000400
|
||||
#define SCC_EPCI_VCSR_SR 0x00000008
|
||||
#define SCC_EPCI_VCSR_AT 0x00000004
|
||||
|
||||
/* bits for SCC_EPCI_VIENAB/SCC_EPCI_VISTAT */
|
||||
#define SCC_EPCI_VISTAT_PMPE 0x00000008
|
||||
#define SCC_EPCI_VISTAT_PMFE 0x00000004
|
||||
#define SCC_EPCI_VISTAT_PRA 0x00000002
|
||||
#define SCC_EPCI_VISTAT_PRD 0x00000001
|
||||
#define SCC_EPCI_VISTAT_ALL 0x0000000f
|
||||
|
||||
#define SCC_EPCI_VIENAB_PMPEE 0x00000008
|
||||
#define SCC_EPCI_VIENAB_PMFEE 0x00000004
|
||||
#define SCC_EPCI_VIENAB_PRA 0x00000002
|
||||
#define SCC_EPCI_VIENAB_PRD 0x00000001
|
||||
#define SCC_EPCI_VIENAB_ALL 0x0000000f
|
||||
|
||||
/* bits for SCC_EPCI_CLKRST */
|
||||
#define SCC_EPCI_CLKRST_CKS_MASK 0x00030000
|
||||
#define SCC_EPCI_CLKRST_CKS_2 0x00000000
|
||||
#define SCC_EPCI_CLKRST_CKS_4 0x00010000
|
||||
#define SCC_EPCI_CLKRST_CKS_8 0x00020000
|
||||
#define SCC_EPCI_CLKRST_PCICRST 0x00000400
|
||||
#define SCC_EPCI_CLKRST_BC 0x00000200
|
||||
#define SCC_EPCI_CLKRST_PCIRST 0x00000100
|
||||
#define SCC_EPCI_CLKRST_PCKEN 0x00000001
|
||||
|
||||
/* bits for SCC_EPCI_INTSET/SCC_EPCI_STATUS */
|
||||
#define SCC_EPCI_INT_2M 0x01000000
|
||||
#define SCC_EPCI_INT_RERR 0x00200000
|
||||
#define SCC_EPCI_INT_SERR 0x00100000
|
||||
#define SCC_EPCI_INT_PRTER 0x00080000
|
||||
#define SCC_EPCI_INT_SER 0x00040000
|
||||
#define SCC_EPCI_INT_PER 0x00020000
|
||||
#define SCC_EPCI_INT_PAI 0x00010000
|
||||
#define SCC_EPCI_INT_1M 0x00000100
|
||||
#define SCC_EPCI_INT_PME 0x00000010
|
||||
#define SCC_EPCI_INT_INTD 0x00000008
|
||||
#define SCC_EPCI_INT_INTC 0x00000004
|
||||
#define SCC_EPCI_INT_INTB 0x00000002
|
||||
#define SCC_EPCI_INT_INTA 0x00000001
|
||||
#define SCC_EPCI_INT_DEVINT 0x0000000f
|
||||
#define SCC_EPCI_INT_ALL 0x003f001f
|
||||
#define SCC_EPCI_INT_ALLERR 0x003f0000
|
||||
|
||||
/* bits for SCC_EPCI_CKCTRL */
|
||||
#define SCC_EPCI_CKCTRL_CRST0 0x00010000
|
||||
#define SCC_EPCI_CKCTRL_CRST1 0x00020000
|
||||
#define SCC_EPCI_CKCTRL_OCLKEN 0x00000100
|
||||
#define SCC_EPCI_CKCTRL_LCLKEN 0x00000001
|
||||
|
||||
#define SCC_EPCI_IDSEL_AD_TO_SLOT(ad) ((ad) - 10)
|
||||
#define SCC_EPCI_MAX_DEVNU SCC_EPCI_IDSEL_AD_TO_SLOT(32)
|
||||
|
||||
/* bits for SCC_EPCI_CNTOPT */
|
||||
#define SCC_EPCI_CNTOPT_O2PMB 0x00000002
|
||||
|
||||
/* UHC registers */
|
||||
#define SCC_UHC_CKRCTRL 0xff0
|
||||
#define SCC_UHC_ECMODE 0xf00
|
||||
|
||||
/* bits for SCC_UHC_CKRCTRL */
|
||||
#define SCC_UHC_F48MCKLEN 0x00000001
|
||||
#define SCC_UHC_P_SUSPEND 0x00000002
|
||||
#define SCC_UHC_PHY_SUSPEND_SEL 0x00000004
|
||||
#define SCC_UHC_HCLKEN 0x00000100
|
||||
#define SCC_UHC_USBEN 0x00010000
|
||||
#define SCC_UHC_USBCEN 0x00020000
|
||||
#define SCC_UHC_PHYEN 0x00040000
|
||||
|
||||
/* bits for SCC_UHC_ECMODE */
|
||||
#define SCC_UHC_ECMODE_BY_BYTE 0x00000555
|
||||
#define SCC_UHC_ECMODE_BY_WORD 0x00000aaa
|
||||
|
||||
#endif /* _CELLEB_SCC_H */
|
||||
|
|
@ -0,0 +1,409 @@
|
|||
/*
|
||||
* Support for SCC external PCI
|
||||
*
|
||||
* (C) Copyright 2004-2007 TOSHIBA CORPORATION
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*/
|
||||
|
||||
#undef DEBUG
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/threads.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/pci_regs.h>
|
||||
#include <linux/bootmem.h>
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/prom.h>
|
||||
#include <asm/machdep.h>
|
||||
#include <asm/pci-bridge.h>
|
||||
#include <asm/ppc-pci.h>
|
||||
|
||||
#include "scc.h"
|
||||
#include "pci.h"
|
||||
#include "interrupt.h"
|
||||
|
||||
#define MAX_PCI_DEVICES 32
|
||||
#define MAX_PCI_FUNCTIONS 8
|
||||
|
||||
#define iob() __asm__ __volatile__("eieio; sync":::"memory")
|
||||
|
||||
|
||||
#if 0 /* test code for epci dummy read */
|
||||
static void celleb_epci_dummy_read(struct pci_dev *dev)
|
||||
{
|
||||
void *epci_base;
|
||||
struct device_node *node;
|
||||
struct pci_controller *hose;
|
||||
u32 val;
|
||||
|
||||
node = (struct device_node *)dev->bus->sysdata;
|
||||
hose = pci_find_hose_for_OF_device(node);
|
||||
|
||||
if (!hose)
|
||||
return;
|
||||
|
||||
epci_base = (void *)hose->cfg_addr;
|
||||
|
||||
val = in_be32(epci_base + SCC_EPCI_WATRP);
|
||||
iosync();
|
||||
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
static inline void clear_and_disable_master_abort_interrupt(
|
||||
struct pci_controller *hose)
|
||||
{
|
||||
void __iomem *addr;
|
||||
addr = (void *)hose->cfg_addr + PCI_COMMAND;
|
||||
out_be32(addr, in_be32(addr) | (PCI_STATUS_REC_MASTER_ABORT << 16));
|
||||
}
|
||||
|
||||
static int celleb_epci_check_abort(struct pci_controller *hose,
|
||||
unsigned long addr)
|
||||
{
|
||||
void __iomem *reg, *epci_base;
|
||||
u32 val;
|
||||
|
||||
iob();
|
||||
epci_base = (void *)hose->cfg_addr;
|
||||
|
||||
reg = epci_base + PCI_COMMAND;
|
||||
val = in_be32(reg);
|
||||
|
||||
if (val & (PCI_STATUS_REC_MASTER_ABORT << 16)) {
|
||||
out_be32(reg,
|
||||
(val & 0xffff) | (PCI_STATUS_REC_MASTER_ABORT << 16));
|
||||
|
||||
/* clear PCI Controller error, FRE, PMFE */
|
||||
reg = epci_base + SCC_EPCI_STATUS;
|
||||
out_be32(reg, SCC_EPCI_INT_PAI);
|
||||
|
||||
reg = epci_base + SCC_EPCI_VCSR;
|
||||
val = in_be32(reg) & 0xffff;
|
||||
val |= SCC_EPCI_VCSR_FRE;
|
||||
out_be32(reg, val);
|
||||
|
||||
reg = epci_base + SCC_EPCI_VISTAT;
|
||||
out_be32(reg, SCC_EPCI_VISTAT_PMFE);
|
||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
}
|
||||
|
||||
return PCIBIOS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
static unsigned long celleb_epci_make_config_addr(struct pci_controller *hose,
|
||||
unsigned int devfn, int where)
|
||||
{
|
||||
unsigned long addr;
|
||||
struct pci_bus *bus = hose->bus;
|
||||
|
||||
if (bus->self)
|
||||
addr = (unsigned long)hose->cfg_data +
|
||||
(((bus->number & 0xff) << 16)
|
||||
| ((devfn & 0xff) << 8)
|
||||
| (where & 0xff)
|
||||
| 0x01000000);
|
||||
else
|
||||
addr = (unsigned long)hose->cfg_data +
|
||||
(((devfn & 0xff) << 8) | (where & 0xff));
|
||||
|
||||
pr_debug("EPCI: config_addr = 0x%016lx\n", addr);
|
||||
|
||||
return addr;
|
||||
}
|
||||
|
||||
static int celleb_epci_read_config(struct pci_bus *bus,
|
||||
unsigned int devfn, int where, int size, u32 * val)
|
||||
{
|
||||
unsigned long addr;
|
||||
struct device_node *node;
|
||||
struct pci_controller *hose;
|
||||
|
||||
/* allignment check */
|
||||
BUG_ON(where % size);
|
||||
|
||||
node = (struct device_node *)bus->sysdata;
|
||||
hose = pci_find_hose_for_OF_device(node);
|
||||
|
||||
if (!hose->cfg_data)
|
||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
|
||||
if (bus->number == hose->first_busno && devfn == 0) {
|
||||
/* EPCI controller self */
|
||||
|
||||
addr = (unsigned long)hose->cfg_addr + where;
|
||||
|
||||
switch (size) {
|
||||
case 1:
|
||||
*val = in_8((u8 *)addr);
|
||||
break;
|
||||
case 2:
|
||||
*val = in_be16((u16 *)addr);
|
||||
break;
|
||||
case 4:
|
||||
*val = in_be32((u32 *)addr);
|
||||
break;
|
||||
default:
|
||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
}
|
||||
|
||||
} else {
|
||||
|
||||
clear_and_disable_master_abort_interrupt(hose);
|
||||
addr = celleb_epci_make_config_addr(hose, devfn, where);
|
||||
|
||||
switch (size) {
|
||||
case 1:
|
||||
*val = in_8((u8 *)addr);
|
||||
break;
|
||||
case 2:
|
||||
*val = in_le16((u16 *)addr);
|
||||
break;
|
||||
case 4:
|
||||
*val = in_le32((u32 *)addr);
|
||||
break;
|
||||
default:
|
||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
}
|
||||
}
|
||||
|
||||
pr_debug("EPCI: "
|
||||
"addr=0x%lx, devfn=0x%x, where=0x%x, size=0x%x, val=0x%x\n",
|
||||
addr, devfn, where, size, *val);
|
||||
|
||||
return celleb_epci_check_abort(hose, 0);
|
||||
}
|
||||
|
||||
static int celleb_epci_write_config(struct pci_bus *bus,
|
||||
unsigned int devfn, int where, int size, u32 val)
|
||||
{
|
||||
unsigned long addr;
|
||||
struct device_node *node;
|
||||
struct pci_controller *hose;
|
||||
|
||||
/* allignment check */
|
||||
BUG_ON(where % size);
|
||||
|
||||
node = (struct device_node *)bus->sysdata;
|
||||
hose = pci_find_hose_for_OF_device(node);
|
||||
|
||||
if (!hose->cfg_data)
|
||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
|
||||
if (bus->number == hose->first_busno && devfn == 0) {
|
||||
/* EPCI controller self */
|
||||
|
||||
addr = (unsigned long)hose->cfg_addr + where;
|
||||
|
||||
switch (size) {
|
||||
case 1:
|
||||
out_8((u8 *)addr, val);
|
||||
break;
|
||||
case 2:
|
||||
out_be16((u16 *)addr, val);
|
||||
break;
|
||||
case 4:
|
||||
out_be32((u32 *)addr, val);
|
||||
break;
|
||||
default:
|
||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
}
|
||||
|
||||
} else {
|
||||
|
||||
clear_and_disable_master_abort_interrupt(hose);
|
||||
addr = celleb_epci_make_config_addr(hose, devfn, where);
|
||||
|
||||
switch (size) {
|
||||
case 1:
|
||||
out_8((u8 *)addr, val);
|
||||
break;
|
||||
case 2:
|
||||
out_le16((u16 *)addr, val);
|
||||
break;
|
||||
case 4:
|
||||
out_le32((u32 *)addr, val);
|
||||
break;
|
||||
default:
|
||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
}
|
||||
}
|
||||
|
||||
return celleb_epci_check_abort(hose, addr);
|
||||
}
|
||||
|
||||
struct pci_ops celleb_epci_ops = {
|
||||
celleb_epci_read_config,
|
||||
celleb_epci_write_config,
|
||||
};
|
||||
|
||||
/* to be moved in FW */
|
||||
static int __devinit celleb_epci_init(struct pci_controller *hose)
|
||||
{
|
||||
u32 val;
|
||||
void __iomem *reg, *epci_base;
|
||||
int hwres = 0;
|
||||
|
||||
epci_base = (void *)hose->cfg_addr;
|
||||
|
||||
/* PCI core reset(Internal bus and PCI clock) */
|
||||
reg = epci_base + SCC_EPCI_CKCTRL;
|
||||
val = in_be32(reg);
|
||||
if (val == 0x00030101)
|
||||
hwres = 1;
|
||||
else {
|
||||
val &= ~(SCC_EPCI_CKCTRL_CRST0 | SCC_EPCI_CKCTRL_CRST1);
|
||||
out_be32(reg, val);
|
||||
|
||||
/* set PCI core clock */
|
||||
val = in_be32(reg);
|
||||
val |= (SCC_EPCI_CKCTRL_OCLKEN | SCC_EPCI_CKCTRL_LCLKEN);
|
||||
out_be32(reg, val);
|
||||
|
||||
/* release PCI core reset (internal bus) */
|
||||
val = in_be32(reg);
|
||||
val |= SCC_EPCI_CKCTRL_CRST0;
|
||||
out_be32(reg, val);
|
||||
|
||||
/* set PCI clock select */
|
||||
reg = epci_base + SCC_EPCI_CLKRST;
|
||||
val = in_be32(reg);
|
||||
val &= ~SCC_EPCI_CLKRST_CKS_MASK;
|
||||
val |= SCC_EPCI_CLKRST_CKS_2;
|
||||
out_be32(reg, val);
|
||||
|
||||
/* set arbiter */
|
||||
reg = epci_base + SCC_EPCI_ABTSET;
|
||||
out_be32(reg, 0x0f1f001f); /* temporary value */
|
||||
|
||||
/* buffer on */
|
||||
reg = epci_base + SCC_EPCI_CLKRST;
|
||||
val = in_be32(reg);
|
||||
val |= SCC_EPCI_CLKRST_BC;
|
||||
out_be32(reg, val);
|
||||
|
||||
/* PCI clock enable */
|
||||
val = in_be32(reg);
|
||||
val |= SCC_EPCI_CLKRST_PCKEN;
|
||||
out_be32(reg, val);
|
||||
|
||||
/* release PCI core reset (all) */
|
||||
reg = epci_base + SCC_EPCI_CKCTRL;
|
||||
val = in_be32(reg);
|
||||
val |= (SCC_EPCI_CKCTRL_CRST0 | SCC_EPCI_CKCTRL_CRST1);
|
||||
out_be32(reg, val);
|
||||
|
||||
/* set base translation registers. (already set by Beat) */
|
||||
|
||||
/* set base address masks. (already set by Beat) */
|
||||
}
|
||||
|
||||
/* release interrupt masks and clear all interrupts */
|
||||
reg = epci_base + SCC_EPCI_INTSET;
|
||||
out_be32(reg, 0x013f011f); /* all interrupts enable */
|
||||
reg = epci_base + SCC_EPCI_VIENAB;
|
||||
val = SCC_EPCI_VIENAB_PMPEE | SCC_EPCI_VIENAB_PMFEE;
|
||||
out_be32(reg, val);
|
||||
reg = epci_base + SCC_EPCI_STATUS;
|
||||
out_be32(reg, 0xffffffff);
|
||||
reg = epci_base + SCC_EPCI_VISTAT;
|
||||
out_be32(reg, 0xffffffff);
|
||||
|
||||
/* disable PCI->IB address translation */
|
||||
reg = epci_base + SCC_EPCI_VCSR;
|
||||
val = in_be32(reg);
|
||||
val &= ~(SCC_EPCI_VCSR_DR | SCC_EPCI_VCSR_AT);
|
||||
out_be32(reg, val);
|
||||
|
||||
/* set base addresses. (no need to set?) */
|
||||
|
||||
/* memory space, bus master enable */
|
||||
reg = epci_base + PCI_COMMAND;
|
||||
val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
|
||||
out_be32(reg, val);
|
||||
|
||||
/* endian mode setup */
|
||||
reg = epci_base + SCC_EPCI_ECMODE;
|
||||
val = 0x00550155;
|
||||
out_be32(reg, val);
|
||||
|
||||
/* set control option */
|
||||
reg = epci_base + SCC_EPCI_CNTOPT;
|
||||
val = in_be32(reg);
|
||||
val |= SCC_EPCI_CNTOPT_O2PMB;
|
||||
out_be32(reg, val);
|
||||
|
||||
/* XXX: temporay: set registers for address conversion setup */
|
||||
reg = epci_base + SCC_EPCI_CNF10_REG;
|
||||
out_be32(reg, 0x80000008);
|
||||
reg = epci_base + SCC_EPCI_CNF14_REG;
|
||||
out_be32(reg, 0x40000008);
|
||||
|
||||
reg = epci_base + SCC_EPCI_BAM0;
|
||||
out_be32(reg, 0x80000000);
|
||||
reg = epci_base + SCC_EPCI_BAM1;
|
||||
out_be32(reg, 0xe0000000);
|
||||
|
||||
reg = epci_base + SCC_EPCI_PVBAT;
|
||||
out_be32(reg, 0x80000000);
|
||||
|
||||
if (!hwres) {
|
||||
/* release external PCI reset */
|
||||
reg = epci_base + SCC_EPCI_CLKRST;
|
||||
val = in_be32(reg);
|
||||
val |= SCC_EPCI_CLKRST_PCIRST;
|
||||
out_be32(reg, val);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int __devinit celleb_setup_epci(struct device_node *node,
|
||||
struct pci_controller *hose)
|
||||
{
|
||||
struct resource r;
|
||||
|
||||
pr_debug("PCI: celleb_setup_epci()\n");
|
||||
|
||||
if (of_address_to_resource(node, 0, &r))
|
||||
goto error;
|
||||
hose->cfg_addr = ioremap(r.start, (r.end - r.start + 1));
|
||||
if (!hose->cfg_addr)
|
||||
goto error;
|
||||
pr_debug("EPCI: cfg_addr map 0x%016lx->0x%016lx + 0x%016lx\n",
|
||||
r.start, (unsigned long)hose->cfg_addr,
|
||||
(r.end - r.start + 1));
|
||||
|
||||
if (of_address_to_resource(node, 2, &r))
|
||||
goto error;
|
||||
hose->cfg_data = ioremap(r.start, (r.end - r.start + 1));
|
||||
if (!hose->cfg_data)
|
||||
goto error;
|
||||
pr_debug("EPCI: cfg_data map 0x%016lx->0x%016lx + 0x%016lx\n",
|
||||
r.start, (unsigned long)hose->cfg_data,
|
||||
(r.end - r.start + 1));
|
||||
|
||||
celleb_epci_init(hose);
|
||||
|
||||
return 0;
|
||||
|
||||
error:
|
||||
return 1;
|
||||
}
|
||||
|
|
@ -0,0 +1,101 @@
|
|||
/*
|
||||
* setup serial port in SCC
|
||||
*
|
||||
* (C) Copyright 2006 TOSHIBA CORPORATION
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*/
|
||||
|
||||
#include <linux/tty.h>
|
||||
#include <linux/serial.h>
|
||||
#include <linux/serial_core.h>
|
||||
#include <linux/console.h>
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <asm/prom.h>
|
||||
|
||||
/* sio irq0=0xb00010022 irq0=0xb00010023 irq2=0xb00010024
|
||||
mmio=0xfff000-0x1000,0xff2000-0x1000 */
|
||||
static int txx9_serial_bitmap = 0;
|
||||
|
||||
static struct {
|
||||
uint32_t offset;
|
||||
uint32_t index;
|
||||
} txx9_scc_tab[3] = {
|
||||
{ 0x300, 0 }, /* 0xFFF300 */
|
||||
{ 0x400, 0 }, /* 0xFFF400 */
|
||||
{ 0x800, 1 } /* 0xFF2800 */
|
||||
};
|
||||
|
||||
static int txx9_serial_init(void)
|
||||
{
|
||||
extern int early_serial_txx9_setup(struct uart_port *port);
|
||||
struct device_node *node;
|
||||
int i;
|
||||
struct uart_port req;
|
||||
struct of_irq irq;
|
||||
struct resource res;
|
||||
|
||||
node = of_find_node_by_path("/ioif1/sio");
|
||||
if (!node)
|
||||
return 0;
|
||||
|
||||
for(i = 0; i < sizeof(txx9_scc_tab)/sizeof(txx9_scc_tab[0]); i++) {
|
||||
if (!(txx9_serial_bitmap & (1<<i)))
|
||||
continue;
|
||||
|
||||
if (of_irq_map_one(node, i, &irq))
|
||||
continue;
|
||||
if (of_address_to_resource(node, txx9_scc_tab[i].index, &res))
|
||||
continue;
|
||||
|
||||
memset(&req, 0, sizeof(req));
|
||||
req.line = i;
|
||||
req.iotype = UPIO_MEM;
|
||||
req.mapbase = res.start + txx9_scc_tab[i].offset;
|
||||
#ifdef CONFIG_SERIAL_TXX9_CONSOLE
|
||||
req.membase = ioremap(req.mapbase, 0x24);
|
||||
#endif
|
||||
req.irq = irq_create_of_mapping(irq.controller,
|
||||
irq.specifier, irq.size);
|
||||
req.flags |= UPF_IOREMAP | UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
|
||||
req.uartclk = 83300000;
|
||||
early_serial_txx9_setup(&req);
|
||||
}
|
||||
|
||||
of_node_put(node);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int txx9_serial_config(char *ptr)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (;;) {
|
||||
switch(get_option(&ptr, &i)) {
|
||||
default:
|
||||
return 0;
|
||||
case 2:
|
||||
txx9_serial_bitmap |= 1 << i;
|
||||
break;
|
||||
case 1:
|
||||
txx9_serial_bitmap |= 1 << i;
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
__setup("txx9_serial=", txx9_serial_config);
|
||||
|
||||
console_initcall(txx9_serial_init);
|
||||
|
|
@ -0,0 +1,94 @@
|
|||
/*
|
||||
* SCC (Super Companion Chip) UHC setup
|
||||
*
|
||||
* (C) Copyright 2006-2007 TOSHIBA CORPORATION
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/pci.h>
|
||||
|
||||
#include <asm/delay.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/machdep.h>
|
||||
|
||||
#include "scc.h"
|
||||
|
||||
#define UHC_RESET_WAIT_MAX 10000
|
||||
|
||||
static inline int uhc_clkctrl_ready(u32 val)
|
||||
{
|
||||
const u32 mask = SCC_UHC_USBCEN | SCC_UHC_USBCEN;
|
||||
return((val & mask) == mask);
|
||||
}
|
||||
|
||||
/*
|
||||
* UHC(usb host controler) enable function.
|
||||
* affect to both of OHCI and EHCI core module.
|
||||
*/
|
||||
static void enable_scc_uhc(struct pci_dev *dev)
|
||||
{
|
||||
void __iomem *uhc_base;
|
||||
u32 __iomem *uhc_clkctrl;
|
||||
u32 __iomem *uhc_ecmode;
|
||||
u32 val = 0;
|
||||
int i;
|
||||
|
||||
if (!machine_is(celleb))
|
||||
return;
|
||||
|
||||
uhc_base = ioremap(pci_resource_start(dev, 0),
|
||||
pci_resource_len(dev, 0));
|
||||
if (!uhc_base) {
|
||||
printk(KERN_ERR "failed to map UHC register base.\n");
|
||||
return;
|
||||
}
|
||||
uhc_clkctrl = uhc_base + SCC_UHC_CKRCTRL;
|
||||
uhc_ecmode = uhc_base + SCC_UHC_ECMODE;
|
||||
|
||||
/* setup for normal mode */
|
||||
val |= SCC_UHC_F48MCKLEN;
|
||||
out_be32(uhc_clkctrl, val);
|
||||
val |= SCC_UHC_PHY_SUSPEND_SEL;
|
||||
out_be32(uhc_clkctrl, val);
|
||||
udelay(10);
|
||||
val |= SCC_UHC_PHYEN;
|
||||
out_be32(uhc_clkctrl, val);
|
||||
udelay(50);
|
||||
|
||||
/* disable reset */
|
||||
val |= SCC_UHC_HCLKEN;
|
||||
out_be32(uhc_clkctrl, val);
|
||||
val |= (SCC_UHC_USBCEN | SCC_UHC_USBEN);
|
||||
out_be32(uhc_clkctrl, val);
|
||||
i = 0;
|
||||
while (!uhc_clkctrl_ready(in_be32(uhc_clkctrl))) {
|
||||
udelay(10);
|
||||
if (i++ > UHC_RESET_WAIT_MAX) {
|
||||
printk(KERN_ERR "Failed to disable UHC reset %x\n",
|
||||
in_be32(uhc_clkctrl));
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Endian Conversion Mode for Master ALL area */
|
||||
out_be32(uhc_ecmode, SCC_UHC_ECMODE_BY_BYTE);
|
||||
|
||||
iounmap(uhc_base);
|
||||
}
|
||||
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
|
||||
PCI_DEVICE_ID_TOSHIBA_SCC_USB, enable_scc_uhc);
|
||||
|
|
@ -0,0 +1,191 @@
|
|||
/*
|
||||
* Celleb setup code
|
||||
*
|
||||
* (C) Copyright 2006-2007 TOSHIBA CORPORATION
|
||||
*
|
||||
* This code is based on arch/powerpc/platforms/cell/setup.c:
|
||||
* Copyright (C) 1995 Linus Torvalds
|
||||
* Adapted from 'alpha' version by Gary Thomas
|
||||
* Modified by Cort Dougan (cort@cs.nmt.edu)
|
||||
* Modified by PPC64 Team, IBM Corp
|
||||
* Modified by Cell Team, IBM Deutschland Entwicklung GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*/
|
||||
|
||||
#undef DEBUG
|
||||
|
||||
#include <linux/cpu.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/stddef.h>
|
||||
#include <linux/unistd.h>
|
||||
#include <linux/reboot.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/seq_file.h>
|
||||
#include <linux/root_dev.h>
|
||||
#include <linux/console.h>
|
||||
|
||||
#include <asm/mmu.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/kexec.h>
|
||||
#include <asm/prom.h>
|
||||
#include <asm/machdep.h>
|
||||
#include <asm/cputable.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/spu_priv1.h>
|
||||
#include <asm/firmware.h>
|
||||
#include <asm/of_platform.h>
|
||||
|
||||
#include "interrupt.h"
|
||||
#include "beat_wrapper.h"
|
||||
#include "beat.h"
|
||||
#include "pci.h"
|
||||
|
||||
static char celleb_machine_type[128] = "Celleb";
|
||||
|
||||
static void celleb_show_cpuinfo(struct seq_file *m)
|
||||
{
|
||||
struct device_node *root;
|
||||
const char *model = "";
|
||||
|
||||
root = of_find_node_by_path("/");
|
||||
if (root)
|
||||
model = get_property(root, "model", NULL);
|
||||
/* using "CHRP" is to trick anaconda into installing FCx into Celleb */
|
||||
seq_printf(m, "machine\t\t: %s %s\n", celleb_machine_type, model);
|
||||
of_node_put(root);
|
||||
}
|
||||
|
||||
static int celleb_machine_type_hack(char *ptr)
|
||||
{
|
||||
strncpy(celleb_machine_type, ptr, sizeof(celleb_machine_type));
|
||||
celleb_machine_type[sizeof(celleb_machine_type)-1] = 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
__setup("celleb_machine_type_hack", celleb_machine_type_hack);
|
||||
|
||||
static void celleb_progress(char *s, unsigned short hex)
|
||||
{
|
||||
printk("*** %04x : %s\n", hex, s ? s : "");
|
||||
}
|
||||
|
||||
static void __init celleb_setup_arch(void)
|
||||
{
|
||||
#ifdef CONFIG_SPU_BASE
|
||||
spu_priv1_ops = &spu_priv1_beat_ops;
|
||||
spu_management_ops = &spu_management_of_ops;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
smp_init_celleb();
|
||||
#endif
|
||||
|
||||
/* init to some ~sane value until calibrate_delay() runs */
|
||||
loops_per_jiffy = 50000000;
|
||||
|
||||
if (ROOT_DEV == 0) {
|
||||
printk("No ramdisk, default root is /dev/hda2\n");
|
||||
ROOT_DEV = Root_HDA2;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DUMMY_CONSOLE
|
||||
conswitchp = &dummy_con;
|
||||
#endif
|
||||
}
|
||||
|
||||
static void beat_power_save(void)
|
||||
{
|
||||
beat_pause(0);
|
||||
}
|
||||
|
||||
static int __init celleb_probe(void)
|
||||
{
|
||||
unsigned long root = of_get_flat_dt_root();
|
||||
|
||||
if (!of_flat_dt_is_compatible(root, "Beat"))
|
||||
return 0;
|
||||
|
||||
powerpc_firmware_features |= FW_FEATURE_CELLEB_POSSIBLE;
|
||||
hpte_init_beat();
|
||||
return 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Cell has no legacy IO; anything calling this function has to
|
||||
* fail or bad things will happen
|
||||
*/
|
||||
static int celleb_check_legacy_ioport(unsigned int baseport)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static void celleb_kexec_cpu_down(int crash, int secondary)
|
||||
{
|
||||
beatic_deinit_IRQ();
|
||||
}
|
||||
|
||||
static struct of_device_id celleb_bus_ids[] = {
|
||||
{ .type = "scc", },
|
||||
{ .type = "ioif", }, /* old style */
|
||||
{},
|
||||
};
|
||||
|
||||
static int __init celleb_publish_devices(void)
|
||||
{
|
||||
if (!machine_is(celleb))
|
||||
return 0;
|
||||
|
||||
/* Publish OF platform devices for southbridge IOs */
|
||||
of_platform_bus_probe(NULL, celleb_bus_ids, NULL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
device_initcall(celleb_publish_devices);
|
||||
|
||||
define_machine(celleb) {
|
||||
.name = "Cell Reference Set",
|
||||
.probe = celleb_probe,
|
||||
.setup_arch = celleb_setup_arch,
|
||||
.show_cpuinfo = celleb_show_cpuinfo,
|
||||
.restart = beat_restart,
|
||||
.power_off = beat_power_off,
|
||||
.halt = beat_halt,
|
||||
.get_rtc_time = beat_get_rtc_time,
|
||||
.set_rtc_time = beat_set_rtc_time,
|
||||
.calibrate_decr = generic_calibrate_decr,
|
||||
.check_legacy_ioport = celleb_check_legacy_ioport,
|
||||
.progress = celleb_progress,
|
||||
.power_save = beat_power_save,
|
||||
.nvram_size = beat_nvram_get_size,
|
||||
.nvram_read = beat_nvram_read,
|
||||
.nvram_write = beat_nvram_write,
|
||||
.set_dabr = beat_set_xdabr,
|
||||
.init_IRQ = beatic_init_IRQ,
|
||||
.get_irq = beatic_get_irq,
|
||||
.pci_probe_mode = celleb_pci_probe_mode,
|
||||
.pci_setup_phb = celleb_setup_phb,
|
||||
#ifdef CONFIG_KEXEC
|
||||
.kexec_cpu_down = celleb_kexec_cpu_down,
|
||||
.machine_kexec = default_machine_kexec,
|
||||
.machine_kexec_prepare = default_machine_kexec_prepare,
|
||||
.machine_crash_shutdown = default_machine_crash_shutdown,
|
||||
#endif
|
||||
};
|
||||
|
|
@ -0,0 +1,124 @@
|
|||
/*
|
||||
* SMP support for Celleb platform. (Incomplete)
|
||||
*
|
||||
* (C) Copyright 2006 TOSHIBA CORPORATION
|
||||
*
|
||||
* This code is based on arch/powerpc/platforms/cell/smp.c:
|
||||
* Dave Engebretsen, Peter Bergner, and
|
||||
* Mike Corrigan {engebret|bergner|mikec}@us.ibm.com
|
||||
* Plus various changes from other IBM teams...
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*/
|
||||
|
||||
#undef DEBUG
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/threads.h>
|
||||
#include <linux/cpu.h>
|
||||
|
||||
#include <asm/irq.h>
|
||||
#include <asm/smp.h>
|
||||
#include <asm/machdep.h>
|
||||
#include <asm/udbg.h>
|
||||
|
||||
#include "interrupt.h"
|
||||
|
||||
#ifdef DEBUG
|
||||
#define DBG(fmt...) udbg_printf(fmt)
|
||||
#else
|
||||
#define DBG(fmt...)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* The primary thread of each non-boot processor is recorded here before
|
||||
* smp init.
|
||||
*/
|
||||
/* static cpumask_t of_spin_map; */
|
||||
|
||||
/**
|
||||
* smp_startup_cpu() - start the given cpu
|
||||
*
|
||||
* At boot time, there is nothing to do for primary threads which were
|
||||
* started from Open Firmware. For anything else, call RTAS with the
|
||||
* appropriate start location.
|
||||
*
|
||||
* Returns:
|
||||
* 0 - failure
|
||||
* 1 - success
|
||||
*/
|
||||
static inline int __devinit smp_startup_cpu(unsigned int lcpu)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void smp_beatic_message_pass(int target, int msg)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
if (target < NR_CPUS) {
|
||||
beatic_cause_IPI(target, msg);
|
||||
} else {
|
||||
for_each_online_cpu(i) {
|
||||
if (target == MSG_ALL_BUT_SELF
|
||||
&& i == smp_processor_id())
|
||||
continue;
|
||||
beatic_cause_IPI(i, msg);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static int __init smp_beatic_probe(void)
|
||||
{
|
||||
return cpus_weight(cpu_possible_map);
|
||||
}
|
||||
|
||||
static void __devinit smp_beatic_setup_cpu(int cpu)
|
||||
{
|
||||
beatic_setup_cpu(cpu);
|
||||
}
|
||||
|
||||
static void __devinit smp_celleb_kick_cpu(int nr)
|
||||
{
|
||||
BUG_ON(nr < 0 || nr >= NR_CPUS);
|
||||
|
||||
if (!smp_startup_cpu(nr))
|
||||
return;
|
||||
}
|
||||
|
||||
static int smp_celleb_cpu_bootable(unsigned int nr)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
static struct smp_ops_t bpa_beatic_smp_ops = {
|
||||
.message_pass = smp_beatic_message_pass,
|
||||
.probe = smp_beatic_probe,
|
||||
.kick_cpu = smp_celleb_kick_cpu,
|
||||
.setup_cpu = smp_beatic_setup_cpu,
|
||||
.cpu_bootable = smp_celleb_cpu_bootable,
|
||||
};
|
||||
|
||||
/* This is called very early */
|
||||
void __init smp_init_celleb(void)
|
||||
{
|
||||
DBG(" -> smp_init_celleb()\n");
|
||||
|
||||
smp_ops = &bpa_beatic_smp_ops;
|
||||
|
||||
DBG(" <- smp_init_celleb()\n");
|
||||
}
|
||||
|
|
@ -0,0 +1,208 @@
|
|||
/*
|
||||
* spu hypervisor abstraction for Beat
|
||||
*
|
||||
* (C) Copyright 2006-2007 TOSHIBA CORPORATION
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
|
||||
#include <asm/types.h>
|
||||
#include <asm/spu.h>
|
||||
#include <asm/spu_priv1.h>
|
||||
|
||||
#include "beat_wrapper.h"
|
||||
|
||||
static inline void _int_mask_set(struct spu *spu, int class, u64 mask)
|
||||
{
|
||||
spu->shadow_int_mask_RW[class] = mask;
|
||||
beat_set_irq_mask_for_spe(spu->spe_id, class, mask);
|
||||
}
|
||||
|
||||
static inline u64 _int_mask_get(struct spu *spu, int class)
|
||||
{
|
||||
return spu->shadow_int_mask_RW[class];
|
||||
}
|
||||
|
||||
static void int_mask_set(struct spu *spu, int class, u64 mask)
|
||||
{
|
||||
_int_mask_set(spu, class, mask);
|
||||
}
|
||||
|
||||
static u64 int_mask_get(struct spu *spu, int class)
|
||||
{
|
||||
return _int_mask_get(spu, class);
|
||||
}
|
||||
|
||||
static void int_mask_and(struct spu *spu, int class, u64 mask)
|
||||
{
|
||||
u64 old_mask;
|
||||
old_mask = _int_mask_get(spu, class);
|
||||
_int_mask_set(spu, class, old_mask & mask);
|
||||
}
|
||||
|
||||
static void int_mask_or(struct spu *spu, int class, u64 mask)
|
||||
{
|
||||
u64 old_mask;
|
||||
old_mask = _int_mask_get(spu, class);
|
||||
_int_mask_set(spu, class, old_mask | mask);
|
||||
}
|
||||
|
||||
static void int_stat_clear(struct spu *spu, int class, u64 stat)
|
||||
{
|
||||
beat_clear_interrupt_status_of_spe(spu->spe_id, class, stat);
|
||||
}
|
||||
|
||||
static u64 int_stat_get(struct spu *spu, int class)
|
||||
{
|
||||
u64 int_stat;
|
||||
beat_get_interrupt_status_of_spe(spu->spe_id, class, &int_stat);
|
||||
return int_stat;
|
||||
}
|
||||
|
||||
static void cpu_affinity_set(struct spu *spu, int cpu)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
static u64 mfc_dar_get(struct spu *spu)
|
||||
{
|
||||
u64 dar;
|
||||
beat_get_spe_privileged_state_1_registers(
|
||||
spu->spe_id,
|
||||
offsetof(struct spu_priv1, mfc_dar_RW), &dar);
|
||||
return dar;
|
||||
}
|
||||
|
||||
static u64 mfc_dsisr_get(struct spu *spu)
|
||||
{
|
||||
u64 dsisr;
|
||||
beat_get_spe_privileged_state_1_registers(
|
||||
spu->spe_id,
|
||||
offsetof(struct spu_priv1, mfc_dsisr_RW), &dsisr);
|
||||
return dsisr;
|
||||
}
|
||||
|
||||
static void mfc_dsisr_set(struct spu *spu, u64 dsisr)
|
||||
{
|
||||
beat_set_spe_privileged_state_1_registers(
|
||||
spu->spe_id,
|
||||
offsetof(struct spu_priv1, mfc_dsisr_RW), dsisr);
|
||||
}
|
||||
|
||||
static void mfc_sdr_setup(struct spu *spu)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
static void mfc_sr1_set(struct spu *spu, u64 sr1)
|
||||
{
|
||||
beat_set_spe_privileged_state_1_registers(
|
||||
spu->spe_id,
|
||||
offsetof(struct spu_priv1, mfc_sr1_RW), sr1);
|
||||
}
|
||||
|
||||
static u64 mfc_sr1_get(struct spu *spu)
|
||||
{
|
||||
u64 sr1;
|
||||
beat_get_spe_privileged_state_1_registers(
|
||||
spu->spe_id,
|
||||
offsetof(struct spu_priv1, mfc_sr1_RW), &sr1);
|
||||
return sr1;
|
||||
}
|
||||
|
||||
static void mfc_tclass_id_set(struct spu *spu, u64 tclass_id)
|
||||
{
|
||||
beat_set_spe_privileged_state_1_registers(
|
||||
spu->spe_id,
|
||||
offsetof(struct spu_priv1, mfc_tclass_id_RW), tclass_id);
|
||||
}
|
||||
|
||||
static u64 mfc_tclass_id_get(struct spu *spu)
|
||||
{
|
||||
u64 tclass_id;
|
||||
beat_get_spe_privileged_state_1_registers(
|
||||
spu->spe_id,
|
||||
offsetof(struct spu_priv1, mfc_tclass_id_RW), &tclass_id);
|
||||
return tclass_id;
|
||||
}
|
||||
|
||||
static void tlb_invalidate(struct spu *spu)
|
||||
{
|
||||
beat_set_spe_privileged_state_1_registers(
|
||||
spu->spe_id,
|
||||
offsetof(struct spu_priv1, tlb_invalidate_entry_W), 0ul);
|
||||
}
|
||||
|
||||
static void resource_allocation_groupID_set(struct spu *spu, u64 id)
|
||||
{
|
||||
beat_set_spe_privileged_state_1_registers(
|
||||
spu->spe_id,
|
||||
offsetof(struct spu_priv1, resource_allocation_groupID_RW),
|
||||
id);
|
||||
}
|
||||
|
||||
static u64 resource_allocation_groupID_get(struct spu *spu)
|
||||
{
|
||||
u64 id;
|
||||
beat_get_spe_privileged_state_1_registers(
|
||||
spu->spe_id,
|
||||
offsetof(struct spu_priv1, resource_allocation_groupID_RW),
|
||||
&id);
|
||||
return id;
|
||||
}
|
||||
|
||||
static void resource_allocation_enable_set(struct spu *spu, u64 enable)
|
||||
{
|
||||
beat_set_spe_privileged_state_1_registers(
|
||||
spu->spe_id,
|
||||
offsetof(struct spu_priv1, resource_allocation_enable_RW),
|
||||
enable);
|
||||
}
|
||||
|
||||
static u64 resource_allocation_enable_get(struct spu *spu)
|
||||
{
|
||||
u64 enable;
|
||||
beat_get_spe_privileged_state_1_registers(
|
||||
spu->spe_id,
|
||||
offsetof(struct spu_priv1, resource_allocation_enable_RW),
|
||||
&enable);
|
||||
return enable;
|
||||
}
|
||||
|
||||
const struct spu_priv1_ops spu_priv1_beat_ops =
|
||||
{
|
||||
.int_mask_and = int_mask_and,
|
||||
.int_mask_or = int_mask_or,
|
||||
.int_mask_set = int_mask_set,
|
||||
.int_mask_get = int_mask_get,
|
||||
.int_stat_clear = int_stat_clear,
|
||||
.int_stat_get = int_stat_get,
|
||||
.cpu_affinity_set = cpu_affinity_set,
|
||||
.mfc_dar_get = mfc_dar_get,
|
||||
.mfc_dsisr_get = mfc_dsisr_get,
|
||||
.mfc_dsisr_set = mfc_dsisr_set,
|
||||
.mfc_sdr_setup = mfc_sdr_setup,
|
||||
.mfc_sr1_set = mfc_sr1_set,
|
||||
.mfc_sr1_get = mfc_sr1_get,
|
||||
.mfc_tclass_id_set = mfc_tclass_id_set,
|
||||
.mfc_tclass_id_get = mfc_tclass_id_get,
|
||||
.tlb_invalidate = tlb_invalidate,
|
||||
.resource_allocation_groupID_set = resource_allocation_groupID_set,
|
||||
.resource_allocation_groupID_get = resource_allocation_groupID_get,
|
||||
.resource_allocation_enable_set = resource_allocation_enable_set,
|
||||
.resource_allocation_enable_get = resource_allocation_enable_get,
|
||||
};
|
||||
|
|
@ -0,0 +1,97 @@
|
|||
/*
|
||||
* udbg function for Beat
|
||||
*
|
||||
* (C) Copyright 2006 TOSHIBA CORPORATION
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/console.h>
|
||||
|
||||
#include <asm/machdep.h>
|
||||
#include <asm/prom.h>
|
||||
#include <asm/udbg.h>
|
||||
|
||||
#include "beat.h"
|
||||
|
||||
#define celleb_vtermno 0
|
||||
|
||||
static void udbg_putc_beat(char c)
|
||||
{
|
||||
unsigned long rc;
|
||||
|
||||
if (c == '\n')
|
||||
udbg_putc_beat('\r');
|
||||
|
||||
rc = beat_put_term_char(celleb_vtermno, 1, (uint64_t)c << 56, 0);
|
||||
}
|
||||
|
||||
/* Buffered chars getc */
|
||||
static long inbuflen;
|
||||
static long inbuf[2]; /* must be 2 longs */
|
||||
|
||||
static int udbg_getc_poll_beat(void)
|
||||
{
|
||||
/* The interface is tricky because it may return up to 16 chars.
|
||||
* We save them statically for future calls to udbg_getc().
|
||||
*/
|
||||
char ch, *buf = (char *)inbuf;
|
||||
int i;
|
||||
long rc;
|
||||
if (inbuflen == 0) {
|
||||
/* get some more chars. */
|
||||
inbuflen = 0;
|
||||
rc = beat_get_term_char(celleb_vtermno, &inbuflen, inbuf+0, inbuf+1);
|
||||
if (rc != 0)
|
||||
inbuflen = 0; /* otherwise inbuflen is garbage */
|
||||
}
|
||||
if (inbuflen <= 0 || inbuflen > 16) {
|
||||
/* Catch error case as well as other oddities (corruption) */
|
||||
inbuflen = 0;
|
||||
return -1;
|
||||
}
|
||||
ch = buf[0];
|
||||
for (i = 1; i < inbuflen; i++) /* shuffle them down. */
|
||||
buf[i-1] = buf[i];
|
||||
inbuflen--;
|
||||
return ch;
|
||||
}
|
||||
|
||||
static int udbg_getc_beat(void)
|
||||
{
|
||||
int ch;
|
||||
for (;;) {
|
||||
ch = udbg_getc_poll_beat();
|
||||
if (ch == -1) {
|
||||
/* This shouldn't be needed...but... */
|
||||
volatile unsigned long delay;
|
||||
for (delay=0; delay < 2000000; delay++)
|
||||
;
|
||||
} else {
|
||||
return ch;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* call this from early_init() for a working debug console on
|
||||
* vterm capable LPAR machines
|
||||
*/
|
||||
void __init udbg_init_debug_beat(void)
|
||||
{
|
||||
udbg_putc = udbg_putc_beat;
|
||||
udbg_getc = udbg_getc_beat;
|
||||
udbg_getc_poll = udbg_getc_poll_beat;
|
||||
}
|
||||
|
|
@ -104,15 +104,6 @@ config RADSTONE_PPC7D
|
|||
config PAL4
|
||||
bool "SBS-Palomar4"
|
||||
|
||||
config GEMINI
|
||||
bool "Synergy-Gemini"
|
||||
select PPC_INDIRECT_PCI
|
||||
depends on BROKEN
|
||||
help
|
||||
Select Gemini if configuring for a Synergy Microsystems' Gemini
|
||||
series Single Board Computer. More information is available at:
|
||||
<http://www.synergymicro.com/PressRel/97_10_15.html>.
|
||||
|
||||
config EST8260
|
||||
bool "EST8260"
|
||||
---help---
|
||||
|
|
|
|||
|
|
@ -425,14 +425,6 @@ static void __init setup_u4_pcie(struct pci_controller* hose)
|
|||
hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
|
||||
hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);
|
||||
|
||||
/* The bus contains a bridge from root -> device, we need to
|
||||
* make it visible on bus 0 so that we pick the right type
|
||||
* of config cycles. If we didn't, we would have to force all
|
||||
* config cycles to be type 1. So we override the "bus-range"
|
||||
* property here
|
||||
*/
|
||||
hose->first_busno = 0x00;
|
||||
hose->last_busno = 0xff;
|
||||
u4_pcie = hose;
|
||||
}
|
||||
|
||||
|
|
@ -560,13 +552,16 @@ void __init maple_pci_init(void)
|
|||
return;
|
||||
}
|
||||
for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) {
|
||||
if (np->name == NULL)
|
||||
if (!np->type)
|
||||
continue;
|
||||
if (!strcmp(np->name, "pci") || !strcmp(np->name, "pcie")) {
|
||||
if (add_bridge(np) == 0)
|
||||
of_node_get(np);
|
||||
}
|
||||
if (strcmp(np->name, "ht") == 0) {
|
||||
if (strcmp(np->type, "pci") && strcmp(np->type, "ht"))
|
||||
continue;
|
||||
if ((device_is_compatible(np, "u4-pcie") ||
|
||||
device_is_compatible(np, "u3-agp")) &&
|
||||
add_bridge(np) == 0)
|
||||
of_node_get(np);
|
||||
|
||||
if (device_is_compatible(np, "u3-ht")) {
|
||||
of_node_get(np);
|
||||
ht = np;
|
||||
}
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
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Reference in New Issue