drm/radeon/dpm: fix displaygap programming on rv6xx
Need to use the driver state rather than the register state since the displays may not be enabled when the power state is programmed. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1182,10 +1182,10 @@ static void rv6xx_program_display_gap(struct radeon_device *rdev)
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u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
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tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
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if (RREG32(AVIVO_D1CRTC_CONTROL) & AVIVO_CRTC_EN) {
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if (rdev->pm.dpm.new_active_crtcs & 1) {
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tmp |= DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK);
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tmp |= DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
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} else if (RREG32(AVIVO_D2CRTC_CONTROL) & AVIVO_CRTC_EN) {
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} else if (rdev->pm.dpm.new_active_crtcs & 2) {
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tmp |= DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
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tmp |= DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK);
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} else {
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