thermal: exynos: simplify HW_TRIP level setting
Simplify HW_TRIP level setting in exynos_tmu_initialize() (don't pretend that the current code is hardware and configuration independent and just do SoC type check explicitly). Then remove no longer needed reg->threshold_[th2,th3_l0_shift] abstractions (only assigned for Exynos5440 in exynos5440_tmu_registers) and EXYNOS_MAX_TRIGGER_PER_REG define. There should be no functional changes caused by this patch. Cc: Amit Daniel Kachhap <amit.daniel@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Eduardo Valentin <edubezval@gmail.com> Cc: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
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@ -252,18 +252,18 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
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(pdata->trigger_type[i] == HW_TRIP)) {
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(pdata->trigger_type[i] == HW_TRIP)) {
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threshold_code = temp_to_code(data,
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threshold_code = temp_to_code(data,
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pdata->trigger_levels[i]);
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pdata->trigger_levels[i]);
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if (i == EXYNOS_MAX_TRIGGER_PER_REG - 1) {
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if (data->soc != SOC_ARCH_EXYNOS5440) {
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/* 1-4 level to be assigned in th0 reg */
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/* 1-4 level to be assigned in th0 reg */
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rising_threshold &= ~(0xff << 8 * i);
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rising_threshold &= ~(0xff << 8 * i);
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rising_threshold |= threshold_code << 8 * i;
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rising_threshold |= threshold_code << 8 * i;
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writel(rising_threshold,
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writel(rising_threshold,
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data->base + reg->threshold_th0);
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data->base + EXYNOS_THD_TEMP_RISE);
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} else if (i == EXYNOS_MAX_TRIGGER_PER_REG) {
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} else {
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/* 5th level to be assigned in th2 reg */
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/* 5th level to be assigned in th2 reg */
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rising_threshold =
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rising_threshold =
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threshold_code << reg->threshold_th3_l0_shift;
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threshold_code << EXYNOS5440_TMU_TH_RISE4_SHIFT;
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writel(rising_threshold,
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writel(rising_threshold,
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data->base + reg->threshold_th2);
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data->base + EXYNOS5440_TMU_S0_7_TH2);
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}
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}
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con = readl(data->base + reg->tmu_ctrl);
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con = readl(data->base + reg->tmu_ctrl);
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con |= (1 << EXYNOS_TMU_THERM_TRIP_EN_SHIFT);
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con |= (1 << EXYNOS_TMU_THERM_TRIP_EN_SHIFT);
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@ -80,8 +80,6 @@ enum soc_type {
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* @tmu_cur_temp: register containing the current temperature of the TMU.
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* @tmu_cur_temp: register containing the current temperature of the TMU.
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* @threshold_th0: Register containing first set of rising levels.
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* @threshold_th0: Register containing first set of rising levels.
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* @threshold_th1: Register containing second set of rising levels.
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* @threshold_th1: Register containing second set of rising levels.
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* @threshold_th2: Register containing third set of rising levels.
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* @threshold_th3_l0_shift: shift bits of level0 threshold temperature.
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* @tmu_inten: register containing the different threshold interrupt
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* @tmu_inten: register containing the different threshold interrupt
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enable bits.
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enable bits.
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* @inten_rise0_shift: shift bits of rising 0 interrupt bits.
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* @inten_rise0_shift: shift bits of rising 0 interrupt bits.
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@ -100,8 +98,6 @@ struct exynos_tmu_registers {
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u32 threshold_th0;
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u32 threshold_th0;
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u32 threshold_th1;
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u32 threshold_th1;
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u32 threshold_th2;
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u32 threshold_th3_l0_shift;
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u32 tmu_inten;
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u32 tmu_inten;
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u32 inten_rise0_shift;
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u32 inten_rise0_shift;
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@ -391,8 +391,6 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
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.tmu_cur_temp = EXYNOS5440_TMU_S0_7_TEMP,
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.tmu_cur_temp = EXYNOS5440_TMU_S0_7_TEMP,
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.threshold_th0 = EXYNOS5440_TMU_S0_7_TH0,
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.threshold_th0 = EXYNOS5440_TMU_S0_7_TH0,
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.threshold_th1 = EXYNOS5440_TMU_S0_7_TH1,
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.threshold_th1 = EXYNOS5440_TMU_S0_7_TH1,
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.threshold_th2 = EXYNOS5440_TMU_S0_7_TH2,
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.threshold_th3_l0_shift = EXYNOS5440_TMU_TH_RISE4_SHIFT,
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.tmu_inten = EXYNOS5440_TMU_S0_7_IRQEN,
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.tmu_inten = EXYNOS5440_TMU_S0_7_IRQEN,
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.inten_rise0_shift = EXYNOS5440_TMU_INTEN_RISE0_SHIFT,
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.inten_rise0_shift = EXYNOS5440_TMU_INTEN_RISE0_SHIFT,
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.inten_rise1_shift = EXYNOS5440_TMU_INTEN_RISE1_SHIFT,
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.inten_rise1_shift = EXYNOS5440_TMU_INTEN_RISE1_SHIFT,
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@ -72,8 +72,6 @@
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#define EXYNOS_EMUL_DATA_MASK 0xFF
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#define EXYNOS_EMUL_DATA_MASK 0xFF
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#define EXYNOS_EMUL_ENABLE 0x1
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#define EXYNOS_EMUL_ENABLE 0x1
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#define EXYNOS_MAX_TRIGGER_PER_REG 4
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/* Exynos5260 specific */
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/* Exynos5260 specific */
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#define EXYNOS5260_TMU_REG_INTEN 0xC0
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#define EXYNOS5260_TMU_REG_INTEN 0xC0
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#define EXYNOS5260_TMU_REG_INTSTAT 0xC4
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#define EXYNOS5260_TMU_REG_INTSTAT 0xC4
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