MXC arch: Simplify architecture's irq sources
Simplify architecture's irq headers and sources, to share these files between MXC3 and MXC2. Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de>
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Juergen Beisert
Robert Schwebel
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9e8a30dce1
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259bcaae9a
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/*
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* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/init.h>
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#include <linux/device.h>
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#include <linux/errno.h>
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#include <asm/hardware.h>
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#include <linux/irq.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/mach/irq.h>
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#include <asm/arch/common.h>
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#define AVIC_BASE IO_ADDRESS(AVIC_BASE_ADDR)
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#define AVIC_INTCNTL (AVIC_BASE + 0x00) /* int control reg */
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#define AVIC_NIMASK (AVIC_BASE + 0x04) /* int mask reg */
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#define AVIC_INTENNUM (AVIC_BASE + 0x08) /* int enable number reg */
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#define AVIC_INTDISNUM (AVIC_BASE + 0x0C) /* int disable number reg */
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#define AVIC_INTENABLEH (AVIC_BASE + 0x10) /* int enable reg high */
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#define AVIC_INTENABLEL (AVIC_BASE + 0x14) /* int enable reg low */
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#define AVIC_INTTYPEH (AVIC_BASE + 0x18) /* int type reg high */
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#define AVIC_INTTYPEL (AVIC_BASE + 0x1C) /* int type reg low */
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#define AVIC_NIPRIORITY7 (AVIC_BASE + 0x20) /* norm int priority lvl7 */
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#define AVIC_NIPRIORITY6 (AVIC_BASE + 0x24) /* norm int priority lvl6 */
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#define AVIC_NIPRIORITY5 (AVIC_BASE + 0x28) /* norm int priority lvl5 */
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#define AVIC_NIPRIORITY4 (AVIC_BASE + 0x2C) /* norm int priority lvl4 */
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#define AVIC_NIPRIORITY3 (AVIC_BASE + 0x30) /* norm int priority lvl3 */
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#define AVIC_NIPRIORITY2 (AVIC_BASE + 0x34) /* norm int priority lvl2 */
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#define AVIC_NIPRIORITY1 (AVIC_BASE + 0x38) /* norm int priority lvl1 */
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#define AVIC_NIPRIORITY0 (AVIC_BASE + 0x3C) /* norm int priority lvl0 */
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#define AVIC_NIVECSR (AVIC_BASE + 0x40) /* norm int vector/status */
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#define AVIC_FIVECSR (AVIC_BASE + 0x44) /* fast int vector/status */
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#define AVIC_INTSRCH (AVIC_BASE + 0x48) /* int source reg high */
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#define AVIC_INTSRCL (AVIC_BASE + 0x4C) /* int source reg low */
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#define AVIC_INTFRCH (AVIC_BASE + 0x50) /* int force reg high */
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#define AVIC_INTFRCL (AVIC_BASE + 0x54) /* int force reg low */
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#define AVIC_NIPNDH (AVIC_BASE + 0x58) /* norm int pending high */
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#define AVIC_NIPNDL (AVIC_BASE + 0x5C) /* norm int pending low */
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#define AVIC_FIPNDH (AVIC_BASE + 0x60) /* fast int pending high */
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#define AVIC_FIPNDL (AVIC_BASE + 0x64) /* fast int pending low */
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#define SYSTEM_PREV_REG IO_ADDRESS(IIM_BASE_ADDR + 0x20)
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#define SYSTEM_SREV_REG IO_ADDRESS(IIM_BASE_ADDR + 0x24)
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#define IIM_PROD_REV_SH 3
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#define IIM_PROD_REV_LEN 5
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/* Disable interrupt number "irq" in the AVIC */
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static void mxc_mask_irq(unsigned int irq)
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{
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@ -32,7 +67,7 @@ static void mxc_unmask_irq(unsigned int irq)
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}
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static struct irq_chip mxc_avic_chip = {
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.mask_ack = mxc_mask_irq,
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.ack = mxc_mask_irq,
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.mask = mxc_mask_irq,
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.unmask = mxc_unmask_irq,
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};
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@ -13,17 +13,4 @@
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#include <asm/hardware.h>
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#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
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#define MXC_IRQ_TO_GPIO(irq) ((irq) - MXC_GPIO_INT_BASE)
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#define MXC_GPIO_TO_IRQ(x) (MXC_GPIO_INT_BASE + x)
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/* Number of normal interrupts */
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#define NR_IRQS (MXC_MAX_INT_LINES + \
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MXC_MAX_GPIO_LINES + \
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MXC_MAX_VIRTUAL_INTS)
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/* Number of fast interrupts */
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#define NR_FIQS MXC_MAX_INTS
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#endif /* __ASM_ARCH_MXC_IRQS_H__ */
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@ -320,6 +320,8 @@
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#define MXC_MAX_GPIO_LINES (GPIO_NUM_PIN * GPIO_PORT_NUM)
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#define MXC_MAX_VIRTUAL_INTS 16
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#define NR_IRQS (MXC_MAX_INT_LINES + MXC_MAX_GPIO_LINES + MXC_MAX_VIRTUAL_INTS)
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/*!
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* Number of GPIO port as defined in the IC Spec
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*/
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@ -29,42 +29,4 @@
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# define cpu_is_mx31() (0)
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#endif
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/*
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*****************************************
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* AVIC Registers *
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*****************************************
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*/
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#define AVIC_BASE IO_ADDRESS(AVIC_BASE_ADDR)
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#define AVIC_INTCNTL (AVIC_BASE + 0x00) /* int control reg */
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#define AVIC_NIMASK (AVIC_BASE + 0x04) /* int mask reg */
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#define AVIC_INTENNUM (AVIC_BASE + 0x08) /* int enable number reg */
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#define AVIC_INTDISNUM (AVIC_BASE + 0x0C) /* int disable number reg */
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#define AVIC_INTENABLEH (AVIC_BASE + 0x10) /* int enable reg high */
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#define AVIC_INTENABLEL (AVIC_BASE + 0x14) /* int enable reg low */
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#define AVIC_INTTYPEH (AVIC_BASE + 0x18) /* int type reg high */
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#define AVIC_INTTYPEL (AVIC_BASE + 0x1C) /* int type reg low */
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#define AVIC_NIPRIORITY7 (AVIC_BASE + 0x20) /* norm int priority lvl7 */
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#define AVIC_NIPRIORITY6 (AVIC_BASE + 0x24) /* norm int priority lvl6 */
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#define AVIC_NIPRIORITY5 (AVIC_BASE + 0x28) /* norm int priority lvl5 */
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#define AVIC_NIPRIORITY4 (AVIC_BASE + 0x2C) /* norm int priority lvl4 */
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#define AVIC_NIPRIORITY3 (AVIC_BASE + 0x30) /* norm int priority lvl3 */
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#define AVIC_NIPRIORITY2 (AVIC_BASE + 0x34) /* norm int priority lvl2 */
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#define AVIC_NIPRIORITY1 (AVIC_BASE + 0x38) /* norm int priority lvl1 */
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#define AVIC_NIPRIORITY0 (AVIC_BASE + 0x3C) /* norm int priority lvl0 */
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#define AVIC_NIVECSR (AVIC_BASE + 0x40) /* norm int vector/status */
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#define AVIC_FIVECSR (AVIC_BASE + 0x44) /* fast int vector/status */
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#define AVIC_INTSRCH (AVIC_BASE + 0x48) /* int source reg high */
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#define AVIC_INTSRCL (AVIC_BASE + 0x4C) /* int source reg low */
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#define AVIC_INTFRCH (AVIC_BASE + 0x50) /* int force reg high */
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#define AVIC_INTFRCL (AVIC_BASE + 0x54) /* int force reg low */
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#define AVIC_NIPNDH (AVIC_BASE + 0x58) /* norm int pending high */
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#define AVIC_NIPNDL (AVIC_BASE + 0x5C) /* norm int pending low */
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#define AVIC_FIPNDH (AVIC_BASE + 0x60) /* fast int pending high */
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#define AVIC_FIPNDL (AVIC_BASE + 0x64) /* fast int pending low */
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#define SYSTEM_PREV_REG IO_ADDRESS(IIM_BASE_ADDR + 0x20)
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#define SYSTEM_SREV_REG IO_ADDRESS(IIM_BASE_ADDR + 0x24)
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#define IIM_PROD_REV_SH 3
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#define IIM_PROD_REV_LEN 5
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#endif /* __ASM_ARCH_MXC_H__ */
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