clk: exynos: prepare for multiplatform
The new common clock drivers for exynos are using compile time constants and soc_is_exynos* macros to provide backwards compatibility for pre-DT systems, which is not possible with multiplatform kernels. This moves all the necessary information back into platform code and removes the mach/* header inclusions. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Mike Turquette <mturquette@linaro.org>
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@ -413,7 +413,7 @@ void __init exynos_init_time(void)
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} else {
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} else {
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/* todo: remove after migrating legacy E4 platforms to dt */
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/* todo: remove after migrating legacy E4 platforms to dt */
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#ifdef CONFIG_ARCH_EXYNOS4
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#ifdef CONFIG_ARCH_EXYNOS4
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exynos4_clk_init(NULL);
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exynos4_clk_init(NULL, !soc_is_exynos4210(), S5P_VA_CMU, readl(S5P_VA_CHIPID + 8) & 1);
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exynos4_clk_register_fixed_ext(xxti_f, xusbxti_f);
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exynos4_clk_register_fixed_ext(xxti_f, xusbxti_f);
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#endif
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#endif
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mct_init();
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mct_init();
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@ -27,7 +27,7 @@ void exynos5_restart(char mode, const char *cmd);
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void exynos_init_late(void);
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void exynos_init_late(void);
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/* ToDo: remove these after migrating legacy exynos4 platforms to dt */
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/* ToDo: remove these after migrating legacy exynos4 platforms to dt */
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void exynos4_clk_init(struct device_node *np);
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void exynos4_clk_init(struct device_node *np, int is_exynos4210, void __iomem *reg_base, unsigned long xom);
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void exynos4_clk_register_fixed_ext(unsigned long, unsigned long);
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void exynos4_clk_register_fixed_ext(unsigned long, unsigned long);
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#ifdef CONFIG_PM_GENERIC_DOMAINS
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#ifdef CONFIG_PM_GENERIC_DOMAINS
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@ -16,7 +16,6 @@
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#include <linux/of.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_address.h>
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#include <plat/cpu.h>
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#include "clk.h"
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#include "clk.h"
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#include "clk-pll.h"
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#include "clk-pll.h"
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@ -910,16 +909,6 @@ struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
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CLK_IGNORE_UNUSED, 0),
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CLK_IGNORE_UNUSED, 0),
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};
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};
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#ifdef CONFIG_OF
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static struct of_device_id exynos4_clk_ids[] __initdata = {
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{ .compatible = "samsung,exynos4210-clock",
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.data = (void *)EXYNOS4210, },
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{ .compatible = "samsung,exynos4412-clock",
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.data = (void *)EXYNOS4X12, },
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{ },
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};
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#endif
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/*
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/*
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* The parent of the fin_pll clock is selected by the XOM[0] bit. This bit
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* The parent of the fin_pll clock is selected by the XOM[0] bit. This bit
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* resides in chipid register space, outside of the clock controller memory
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* resides in chipid register space, outside of the clock controller memory
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@ -927,21 +916,32 @@ static struct of_device_id exynos4_clk_ids[] __initdata = {
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* controller is first remapped and the value of XOM[0] bit is read to
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* controller is first remapped and the value of XOM[0] bit is read to
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* determine the parent clock.
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* determine the parent clock.
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*/
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*/
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static void __init exynos4_clk_register_finpll(void)
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static unsigned long exynos4_get_xom(void)
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{
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{
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struct samsung_fixed_rate_clock fclk;
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unsigned long xom = 0;
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void __iomem *chipid_base;
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struct device_node *np;
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struct device_node *np;
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struct clk *clk;
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void __iomem *chipid_base = S5P_VA_CHIPID;
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unsigned long xom, finpll_f = 24000000;
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char *parent_name;
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np = of_find_compatible_node(NULL, NULL, "samsung,exynos4210-chipid");
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np = of_find_compatible_node(NULL, NULL, "samsung,exynos4210-chipid");
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if (np)
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if (np) {
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chipid_base = of_iomap(np, 0);
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chipid_base = of_iomap(np, 0);
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if (chipid_base) {
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if (chipid_base)
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xom = readl(chipid_base + 8);
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xom = readl(chipid_base + 8);
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iounmap(chipid_base);
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}
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return xom;
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}
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static void __init exynos4_clk_register_finpll(unsigned long xom)
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{
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struct samsung_fixed_rate_clock fclk;
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struct clk *clk;
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unsigned long finpll_f = 24000000;
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char *parent_name;
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parent_name = xom & 1 ? "xusbxti" : "xxti";
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parent_name = xom & 1 ? "xusbxti" : "xxti";
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clk = clk_get(NULL, parent_name);
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clk = clk_get(NULL, parent_name);
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if (IS_ERR(clk)) {
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if (IS_ERR(clk)) {
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@ -951,10 +951,6 @@ static void __init exynos4_clk_register_finpll(void)
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} else {
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} else {
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finpll_f = clk_get_rate(clk);
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finpll_f = clk_get_rate(clk);
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}
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}
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} else {
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pr_err("%s: failed to map chipid registers, assuming "
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"fin_pll clock frequency is 24MHz\n", __func__);
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}
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fclk.id = fin_pll;
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fclk.id = fin_pll;
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fclk.name = "fin_pll";
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fclk.name = "fin_pll";
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@ -963,8 +959,6 @@ static void __init exynos4_clk_register_finpll(void)
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fclk.fixed_rate = finpll_f;
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fclk.fixed_rate = finpll_f;
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samsung_clk_register_fixed_rate(&fclk, 1);
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samsung_clk_register_fixed_rate(&fclk, 1);
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if (np)
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iounmap(chipid_base);
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}
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}
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/*
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/*
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@ -988,28 +982,14 @@ static __initdata struct of_device_id ext_clk_match[] = {
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};
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};
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/* register exynos4 clocks */
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/* register exynos4 clocks */
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void __init exynos4_clk_init(struct device_node *np)
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void __init exynos4_clk_init(struct device_node *np, enum exynos4_soc exynos4_soc, void __iomem *reg_base, unsigned long xom)
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{
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{
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void __iomem *reg_base;
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struct clk *apll, *mpll, *epll, *vpll;
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struct clk *apll, *mpll, *epll, *vpll;
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u32 exynos4_soc;
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if (np) {
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if (np) {
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const struct of_device_id *match;
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match = of_match_node(exynos4_clk_ids, np);
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exynos4_soc = (u32)match->data;
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reg_base = of_iomap(np, 0);
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reg_base = of_iomap(np, 0);
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if (!reg_base)
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if (!reg_base)
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panic("%s: failed to map registers\n", __func__);
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panic("%s: failed to map registers\n", __func__);
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} else {
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reg_base = S5P_VA_CMU;
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if (soc_is_exynos4210())
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exynos4_soc = EXYNOS4210;
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else if (soc_is_exynos4212() || soc_is_exynos4412())
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exynos4_soc = EXYNOS4X12;
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else
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panic("%s: unable to determine soc\n", __func__);
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}
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}
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if (exynos4_soc == EXYNOS4210)
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if (exynos4_soc == EXYNOS4210)
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@ -1026,7 +1006,7 @@ void __init exynos4_clk_init(struct device_node *np)
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ARRAY_SIZE(exynos4_fixed_rate_ext_clks),
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ARRAY_SIZE(exynos4_fixed_rate_ext_clks),
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ext_clk_match);
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ext_clk_match);
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exynos4_clk_register_finpll();
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exynos4_clk_register_finpll(xom);
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if (exynos4_soc == EXYNOS4210) {
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if (exynos4_soc == EXYNOS4210) {
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apll = samsung_clk_register_pll45xx("fout_apll", "fin_pll",
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apll = samsung_clk_register_pll45xx("fout_apll", "fin_pll",
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@ -1087,5 +1067,16 @@ void __init exynos4_clk_init(struct device_node *np)
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_get_rate("sclk_epll"), _get_rate("sclk_vpll"),
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_get_rate("sclk_epll"), _get_rate("sclk_vpll"),
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_get_rate("arm_clk"));
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_get_rate("arm_clk"));
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}
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}
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CLK_OF_DECLARE(exynos4210_clk, "samsung,exynos4210-clock", exynos4_clk_init);
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CLK_OF_DECLARE(exynos4412_clk, "samsung,exynos4412-clock", exynos4_clk_init);
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static void __init exynos4210_clk_init(struct device_node *np)
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{
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exynos4_clk_init(np, EXYNOS4210, NULL, exynos4_get_xom());
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}
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CLK_OF_DECLARE(exynos4210_clk, "samsung,exynos4210-clock", exynos4210_clk_init);
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static void __init exynos4412_clk_init(struct device_node *np)
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{
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exynos4_clk_init(np, EXYNOS4X12, NULL, exynos4_get_xom());
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}
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CLK_OF_DECLARE(exynos4412_clk, "samsung,exynos4412-clock", exynos4412_clk_init);
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@ -16,7 +16,6 @@
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#include <linux/of.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_address.h>
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#include <plat/cpu.h>
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#include "clk.h"
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#include "clk.h"
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#include "clk-pll.h"
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#include "clk-pll.h"
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@ -15,7 +15,6 @@
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#include <linux/of.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_address.h>
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#include <plat/cpu.h>
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#include "clk.h"
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#include "clk.h"
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#include "clk-pll.h"
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#include "clk-pll.h"
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@ -20,8 +20,6 @@
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#include <linux/of.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_address.h>
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#include <mach/map.h>
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/**
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/**
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* struct samsung_clock_alias: information about mux clock
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* struct samsung_clock_alias: information about mux clock
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* @id: platform specific id of the clock.
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* @id: platform specific id of the clock.
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