[POWERPC] cpm2: Add SCCs to cpm2_clk_setup(), and cpm2_smc_clk_setup().
Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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@ -144,7 +144,8 @@ int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode)
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cpmux_t __iomem *im_cpmux;
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u32 __iomem *reg;
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u32 mask = 7;
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u8 clk_map [24][3] = {
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u8 clk_map[][3] = {
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{CPM_CLK_FCC1, CPM_BRG5, 0},
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{CPM_CLK_FCC1, CPM_BRG6, 1},
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{CPM_CLK_FCC1, CPM_BRG7, 2},
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@ -168,8 +169,40 @@ int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode)
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{CPM_CLK_FCC3, CPM_CLK13, 4},
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{CPM_CLK_FCC3, CPM_CLK14, 5},
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{CPM_CLK_FCC3, CPM_CLK15, 6},
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{CPM_CLK_FCC3, CPM_CLK16, 7}
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};
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{CPM_CLK_FCC3, CPM_CLK16, 7},
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{CPM_CLK_SCC1, CPM_BRG1, 0},
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{CPM_CLK_SCC1, CPM_BRG2, 1},
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{CPM_CLK_SCC1, CPM_BRG3, 2},
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{CPM_CLK_SCC1, CPM_BRG4, 3},
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{CPM_CLK_SCC1, CPM_CLK11, 4},
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{CPM_CLK_SCC1, CPM_CLK12, 5},
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{CPM_CLK_SCC1, CPM_CLK3, 6},
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{CPM_CLK_SCC1, CPM_CLK4, 7},
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{CPM_CLK_SCC2, CPM_BRG1, 0},
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{CPM_CLK_SCC2, CPM_BRG2, 1},
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{CPM_CLK_SCC2, CPM_BRG3, 2},
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{CPM_CLK_SCC2, CPM_BRG4, 3},
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{CPM_CLK_SCC2, CPM_CLK11, 4},
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{CPM_CLK_SCC2, CPM_CLK12, 5},
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{CPM_CLK_SCC2, CPM_CLK3, 6},
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{CPM_CLK_SCC2, CPM_CLK4, 7},
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{CPM_CLK_SCC3, CPM_BRG1, 0},
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{CPM_CLK_SCC3, CPM_BRG2, 1},
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{CPM_CLK_SCC3, CPM_BRG3, 2},
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{CPM_CLK_SCC3, CPM_BRG4, 3},
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{CPM_CLK_SCC3, CPM_CLK5, 4},
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{CPM_CLK_SCC3, CPM_CLK6, 5},
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{CPM_CLK_SCC3, CPM_CLK7, 6},
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{CPM_CLK_SCC3, CPM_CLK8, 7},
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{CPM_CLK_SCC4, CPM_BRG1, 0},
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{CPM_CLK_SCC4, CPM_BRG2, 1},
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{CPM_CLK_SCC4, CPM_BRG3, 2},
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{CPM_CLK_SCC4, CPM_BRG4, 3},
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{CPM_CLK_SCC4, CPM_CLK5, 4},
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{CPM_CLK_SCC4, CPM_CLK6, 5},
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{CPM_CLK_SCC4, CPM_CLK7, 6},
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{CPM_CLK_SCC4, CPM_CLK8, 7},
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};
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im_cpmux = cpm2_map(im_cpmux);
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@ -209,23 +242,80 @@ int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode)
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if (mode == CPM_CLK_RX)
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shift += 3;
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for (i=0; i<24; i++) {
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for (i = 0; i < ARRAY_SIZE(clk_map); i++) {
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if (clk_map[i][0] == target && clk_map[i][1] == clock) {
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bits = clk_map[i][2];
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break;
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}
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}
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if (i == sizeof(clk_map)/3)
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if (i == ARRAY_SIZE(clk_map))
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ret = -EINVAL;
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bits <<= shift;
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mask <<= shift;
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out_be32(reg, (in_be32(reg) & ~mask) | bits);
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cpm2_unmap(im_cpmux);
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return ret;
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}
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int cpm2_smc_clk_setup(enum cpm_clk_target target, int clock)
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{
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int ret = 0;
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int shift;
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int i, bits = 0;
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cpmux_t __iomem *im_cpmux;
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u8 __iomem *reg;
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u8 mask = 3;
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u8 clk_map[][3] = {
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{CPM_CLK_SMC1, CPM_BRG1, 0},
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{CPM_CLK_SMC1, CPM_BRG7, 1},
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{CPM_CLK_SMC1, CPM_CLK7, 2},
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{CPM_CLK_SMC1, CPM_CLK9, 3},
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{CPM_CLK_SMC2, CPM_BRG2, 0},
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{CPM_CLK_SMC2, CPM_BRG8, 1},
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{CPM_CLK_SMC2, CPM_CLK4, 2},
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{CPM_CLK_SMC2, CPM_CLK15, 3},
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};
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im_cpmux = cpm2_map(im_cpmux);
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switch (target) {
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case CPM_CLK_SMC1:
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reg = &im_cpmux->cmx_smr;
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mask = 3;
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shift = 4;
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break;
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case CPM_CLK_SMC2:
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reg = &im_cpmux->cmx_smr;
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mask = 3;
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shift = 0;
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break;
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default:
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printk(KERN_ERR "cpm2_smc_clock_setup: invalid clock target\n");
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return -EINVAL;
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}
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for (i = 0; i < ARRAY_SIZE(clk_map); i++) {
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if (clk_map[i][0] == target && clk_map[i][1] == clock) {
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bits = clk_map[i][2];
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break;
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}
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}
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if (i == ARRAY_SIZE(clk_map))
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ret = -EINVAL;
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bits <<= shift;
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mask <<= shift;
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out_8(reg, (in_8(reg) & ~mask) | bits);
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cpm2_unmap(im_cpmux);
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return ret;
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}
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/*
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* dpalloc / dpfree bits.
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*/
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@ -1206,7 +1206,9 @@ enum cpm_clk_target {
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CPM_CLK_SCC4,
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CPM_CLK_FCC1,
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CPM_CLK_FCC2,
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CPM_CLK_FCC3
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CPM_CLK_FCC3,
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CPM_CLK_SMC1,
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CPM_CLK_SMC2,
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};
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enum cpm_clk {
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@ -1243,6 +1245,7 @@ enum cpm_clk {
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};
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extern int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode);
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extern int cpm2_smc_clk_setup(enum cpm_clk_target target, int clock);
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#endif /* __CPM2__ */
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#endif /* __KERNEL__ */
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