x86: change bitwise operations to get a void parameter.
This patch changes the bitwise operations in bitops.h to get a void pointers as a parameter. Before this patch, a lot of warnings can be seen. They're gone after it. Signed-off-by: Glauber de Oliveira Costa <gcosta@redhat.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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@ -43,7 +43,7 @@
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* Note that @nr may be almost arbitrarily large; this function is not
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* Note that @nr may be almost arbitrarily large; this function is not
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* restricted to acting on a single-word quantity.
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* restricted to acting on a single-word quantity.
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*/
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*/
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static inline void set_bit(int nr, volatile unsigned long *addr)
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static inline void set_bit(int nr, volatile void *addr)
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{
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{
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asm volatile(LOCK_PREFIX "bts %1,%0"
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asm volatile(LOCK_PREFIX "bts %1,%0"
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: ADDR
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: ADDR
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@ -59,7 +59,7 @@ static inline void set_bit(int nr, volatile unsigned long *addr)
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* If it's called on the same region of memory simultaneously, the effect
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* If it's called on the same region of memory simultaneously, the effect
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* may be that only one operation succeeds.
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* may be that only one operation succeeds.
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*/
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*/
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static inline void __set_bit(int nr, volatile unsigned long *addr)
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static inline void __set_bit(int nr, volatile void *addr)
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{
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{
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asm volatile("bts %1,%0"
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asm volatile("bts %1,%0"
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: ADDR
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: ADDR
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@ -77,7 +77,7 @@ static inline void __set_bit(int nr, volatile unsigned long *addr)
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* you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
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* you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
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* in order to ensure changes are visible on other processors.
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* in order to ensure changes are visible on other processors.
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*/
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*/
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static inline void clear_bit(int nr, volatile unsigned long *addr)
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static inline void clear_bit(int nr, volatile void *addr)
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{
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{
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asm volatile(LOCK_PREFIX "btr %1,%0"
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asm volatile(LOCK_PREFIX "btr %1,%0"
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: ADDR
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: ADDR
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@ -92,13 +92,13 @@ static inline void clear_bit(int nr, volatile unsigned long *addr)
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* clear_bit() is atomic and implies release semantics before the memory
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* clear_bit() is atomic and implies release semantics before the memory
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* operation. It can be used for an unlock.
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* operation. It can be used for an unlock.
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*/
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*/
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static inline void clear_bit_unlock(unsigned nr, volatile unsigned long *addr)
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static inline void clear_bit_unlock(unsigned nr, volatile void *addr)
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{
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{
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barrier();
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barrier();
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clear_bit(nr, addr);
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clear_bit(nr, addr);
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}
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}
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static inline void __clear_bit(int nr, volatile unsigned long *addr)
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static inline void __clear_bit(int nr, volatile void *addr)
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{
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{
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asm volatile("btr %1,%0" : ADDR : "Ir" (nr));
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asm volatile("btr %1,%0" : ADDR : "Ir" (nr));
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}
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}
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@ -115,7 +115,7 @@ static inline void __clear_bit(int nr, volatile unsigned long *addr)
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* No memory barrier is required here, because x86 cannot reorder stores past
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* No memory barrier is required here, because x86 cannot reorder stores past
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* older loads. Same principle as spin_unlock.
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* older loads. Same principle as spin_unlock.
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*/
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*/
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static inline void __clear_bit_unlock(unsigned nr, volatile unsigned long *addr)
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static inline void __clear_bit_unlock(unsigned nr, volatile void *addr)
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{
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{
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barrier();
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barrier();
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__clear_bit(nr, addr);
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__clear_bit(nr, addr);
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@ -133,7 +133,7 @@ static inline void __clear_bit_unlock(unsigned nr, volatile unsigned long *addr)
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* If it's called on the same region of memory simultaneously, the effect
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* If it's called on the same region of memory simultaneously, the effect
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* may be that only one operation succeeds.
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* may be that only one operation succeeds.
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*/
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*/
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static inline void __change_bit(int nr, volatile unsigned long *addr)
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static inline void __change_bit(int nr, volatile void *addr)
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{
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{
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asm volatile("btc %1,%0" : ADDR : "Ir" (nr));
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asm volatile("btc %1,%0" : ADDR : "Ir" (nr));
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}
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}
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@ -147,7 +147,7 @@ static inline void __change_bit(int nr, volatile unsigned long *addr)
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* Note that @nr may be almost arbitrarily large; this function is not
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* Note that @nr may be almost arbitrarily large; this function is not
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* restricted to acting on a single-word quantity.
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* restricted to acting on a single-word quantity.
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*/
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*/
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static inline void change_bit(int nr, volatile unsigned long *addr)
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static inline void change_bit(int nr, volatile void *addr)
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{
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{
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asm volatile(LOCK_PREFIX "btc %1,%0"
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asm volatile(LOCK_PREFIX "btc %1,%0"
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: ADDR : "Ir" (nr));
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: ADDR : "Ir" (nr));
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@ -161,7 +161,7 @@ static inline void change_bit(int nr, volatile unsigned long *addr)
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* This operation is atomic and cannot be reordered.
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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* It also implies a memory barrier.
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*/
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*/
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static inline int test_and_set_bit(int nr, volatile unsigned long *addr)
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static inline int test_and_set_bit(int nr, volatile void *addr)
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{
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{
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int oldbit;
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int oldbit;
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@ -180,7 +180,7 @@ static inline int test_and_set_bit(int nr, volatile unsigned long *addr)
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*
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*
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* This is the same as test_and_set_bit on x86.
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* This is the same as test_and_set_bit on x86.
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*/
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*/
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static inline int test_and_set_bit_lock(int nr, volatile unsigned long *addr)
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static inline int test_and_set_bit_lock(int nr, volatile void *addr)
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{
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{
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return test_and_set_bit(nr, addr);
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return test_and_set_bit(nr, addr);
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}
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}
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@ -194,7 +194,7 @@ static inline int test_and_set_bit_lock(int nr, volatile unsigned long *addr)
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* If two examples of this operation race, one can appear to succeed
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* If two examples of this operation race, one can appear to succeed
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* but actually fail. You must protect multiple accesses with a lock.
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* but actually fail. You must protect multiple accesses with a lock.
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*/
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*/
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static inline int __test_and_set_bit(int nr, volatile unsigned long *addr)
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static inline int __test_and_set_bit(int nr, volatile void *addr)
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{
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{
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int oldbit;
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int oldbit;
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@ -213,7 +213,7 @@ static inline int __test_and_set_bit(int nr, volatile unsigned long *addr)
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* This operation is atomic and cannot be reordered.
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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* It also implies a memory barrier.
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*/
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*/
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static inline int test_and_clear_bit(int nr, volatile unsigned long *addr)
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static inline int test_and_clear_bit(int nr, volatile void *addr)
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{
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{
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int oldbit;
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int oldbit;
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@ -234,7 +234,7 @@ static inline int test_and_clear_bit(int nr, volatile unsigned long *addr)
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* If two examples of this operation race, one can appear to succeed
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* If two examples of this operation race, one can appear to succeed
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* but actually fail. You must protect multiple accesses with a lock.
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* but actually fail. You must protect multiple accesses with a lock.
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*/
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*/
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static inline int __test_and_clear_bit(int nr, volatile unsigned long *addr)
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static inline int __test_and_clear_bit(int nr, volatile void *addr)
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{
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{
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int oldbit;
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int oldbit;
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@ -246,7 +246,7 @@ static inline int __test_and_clear_bit(int nr, volatile unsigned long *addr)
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}
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}
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/* WARNING: non atomic and it can be reordered! */
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/* WARNING: non atomic and it can be reordered! */
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static inline int __test_and_change_bit(int nr, volatile unsigned long *addr)
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static inline int __test_and_change_bit(int nr, volatile void *addr)
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{
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{
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int oldbit;
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int oldbit;
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@ -266,7 +266,7 @@ static inline int __test_and_change_bit(int nr, volatile unsigned long *addr)
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* This operation is atomic and cannot be reordered.
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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* It also implies a memory barrier.
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*/
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*/
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static inline int test_and_change_bit(int nr, volatile unsigned long *addr)
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static inline int test_and_change_bit(int nr, volatile void *addr)
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{
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{
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int oldbit;
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int oldbit;
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@ -278,19 +278,20 @@ static inline int test_and_change_bit(int nr, volatile unsigned long *addr)
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return oldbit;
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return oldbit;
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}
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}
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static inline int constant_test_bit(int nr, const volatile unsigned long *addr)
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static inline int constant_test_bit(int nr, const volatile void *addr)
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{
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{
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return ((1UL << (nr % BITS_PER_LONG)) & (addr[nr / BITS_PER_LONG])) != 0;
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return ((1UL << (nr % BITS_PER_LONG)) &
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(((unsigned long *)addr)[nr / BITS_PER_LONG])) != 0;
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}
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}
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static inline int variable_test_bit(int nr, volatile const unsigned long *addr)
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static inline int variable_test_bit(int nr, volatile const void *addr)
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{
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{
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int oldbit;
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int oldbit;
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asm volatile("bt %2,%1\n\t"
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asm volatile("bt %2,%1\n\t"
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"sbb %0,%0"
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"sbb %0,%0"
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: "=r" (oldbit)
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: "=r" (oldbit)
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: "m" (*addr), "Ir" (nr));
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: "m" (*(unsigned long *)addr), "Ir" (nr));
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return oldbit;
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return oldbit;
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}
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}
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