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[SERIAL] Add support for more Connect Tech PCI serial boards 

I've also fixed the sort-ordering comments on this naming convention.

Signed-off-by: Stuart MacDonald <stuartm@connecttech.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Gareth Howlett 2006-01-04 17:00:42 +00:00 committed by Russell King
parent 2af7cd68f1
commit 26e92861be
2 changed files with 131 additions and 6 deletions
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112
drivers/serial/8250_pci.c
View File

@ -853,14 +853,15 @@ get_pci_irq(struct pci_dev *dev, struct pciserial_board *board)
* driver_data member. * driver_data member.
* *
* The makeup of these names are: * The makeup of these names are:
* pbn_bn{_bt}_n_baud * pbn_bn{_bt}_n_baud{_offsetinhex}
* *
* bn = PCI BAR number * bn = PCI BAR number
* bt = Index using PCI BARs * bt = Index using PCI BARs
* n = number of serial ports * n = number of serial ports
* baud = baud rate * baud = baud rate
* offsetinhex = offset for each sequential port (in hex)
* *
* This table is sorted by (in order): baud, bt, bn, n. * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
* *
* Please note: in theory if n = 1, _bt infix should make no difference. * Please note: in theory if n = 1, _bt infix should make no difference.
* ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
@ -881,6 +882,13 @@ enum pci_board_num_t {
pbn_b0_4_1152000, pbn_b0_4_1152000,
pbn_b0_2_1843200,
pbn_b0_4_1843200,
pbn_b0_2_1843200_200,
pbn_b0_4_1843200_200,
pbn_b0_8_1843200_200,
pbn_b0_bt_1_115200, pbn_b0_bt_1_115200,
pbn_b0_bt_2_115200, pbn_b0_bt_2_115200,
pbn_b0_bt_8_115200, pbn_b0_bt_8_115200,
@ -904,6 +912,8 @@ enum pci_board_num_t {
pbn_b1_4_921600, pbn_b1_4_921600,
pbn_b1_8_921600, pbn_b1_8_921600,
pbn_b1_2_1250000,
pbn_b1_bt_2_921600, pbn_b1_bt_2_921600,
pbn_b1_1_1382400, pbn_b1_1_1382400,
@ -1029,6 +1039,38 @@ static struct pciserial_board pci_boards[] __devinitdata = {
.uart_offset = 8, .uart_offset = 8,
}, },
[pbn_b0_2_1843200] = {
.flags = FL_BASE0,
.num_ports = 2,
.base_baud = 1843200,
.uart_offset = 8,
},
[pbn_b0_4_1843200] = {
.flags = FL_BASE0,
.num_ports = 4,
.base_baud = 1843200,
.uart_offset = 8,
},
[pbn_b0_2_1843200_200] = {
.flags = FL_BASE0,
.num_ports = 2,
.base_baud = 1843200,
.uart_offset = 0x200,
},
[pbn_b0_4_1843200_200] = {
.flags = FL_BASE0,
.num_ports = 4,
.base_baud = 1843200,
.uart_offset = 0x200,
},
[pbn_b0_8_1843200_200] = {
.flags = FL_BASE0,
.num_ports = 8,
.base_baud = 1843200,
.uart_offset = 0x200,
},
[pbn_b0_bt_1_115200] = { [pbn_b0_bt_1_115200] = {
.flags = FL_BASE0|FL_BASE_BARS, .flags = FL_BASE0|FL_BASE_BARS,
.num_ports = 1, .num_ports = 1,
@ -1141,6 +1183,12 @@ static struct pciserial_board pci_boards[] __devinitdata = {
.base_baud = 921600, .base_baud = 921600,
.uart_offset = 8, .uart_offset = 8,
}, },
[pbn_b1_2_1250000] = {
.flags = FL_BASE1,
.num_ports = 2,
.base_baud = 1250000,
.uart_offset = 8,
},
[pbn_b1_bt_2_921600] = { [pbn_b1_bt_2_921600] = {
.flags = FL_BASE1|FL_BASE_BARS, .flags = FL_BASE1|FL_BASE_BARS,
@ -1801,6 +1849,66 @@ static struct pci_device_id serial_pci_tbl[] = {
PCI_SUBVENDOR_ID_CONNECT_TECH, PCI_SUBVENDOR_ID_CONNECT_TECH,
PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0, PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
pbn_b1_4_921600 }, pbn_b1_4_921600 },
{ PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
PCI_SUBVENDOR_ID_CONNECT_TECH,
PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
pbn_b1_2_1250000 },
{ PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
PCI_SUBVENDOR_ID_CONNECT_TECH,
PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
pbn_b0_2_1843200 },
{ PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
PCI_SUBVENDOR_ID_CONNECT_TECH,
PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
pbn_b0_4_1843200 },
{ PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
PCI_SUBVENDOR_ID_CONNECT_TECH,
PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
pbn_b0_2_1843200_200 },
{ PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
PCI_SUBVENDOR_ID_CONNECT_TECH,
PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
pbn_b0_4_1843200_200 },
{ PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
PCI_SUBVENDOR_ID_CONNECT_TECH,
PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
pbn_b0_8_1843200_200 },
{ PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
PCI_SUBVENDOR_ID_CONNECT_TECH,
PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
pbn_b0_2_1843200_200 },
{ PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
PCI_SUBVENDOR_ID_CONNECT_TECH,
PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
pbn_b0_4_1843200_200 },
{ PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
PCI_SUBVENDOR_ID_CONNECT_TECH,
PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
pbn_b0_8_1843200_200 },
{ PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
PCI_SUBVENDOR_ID_CONNECT_TECH,
PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
pbn_b0_2_1843200_200 },
{ PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
PCI_SUBVENDOR_ID_CONNECT_TECH,
PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
pbn_b0_4_1843200_200 },
{ PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
PCI_SUBVENDOR_ID_CONNECT_TECH,
PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
pbn_b0_8_1843200_200 },
{ PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
PCI_SUBVENDOR_ID_CONNECT_TECH,
PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
pbn_b0_2_1843200_200 },
{ PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
PCI_SUBVENDOR_ID_CONNECT_TECH,
PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
pbn_b0_4_1843200_200 },
{ PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
PCI_SUBVENDOR_ID_CONNECT_TECH,
PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
pbn_b0_8_1843200_200 },
{ PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530, { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ANY_ID, PCI_ANY_ID, 0, 0,

17
include/linux/pci_ids.h
View File

@ -1567,6 +1567,23 @@
#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6 0x0009 #define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6 0x0009
#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1 0x000A #define PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1 0x000A
#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1 0x000B #define PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1 0x000B
#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ 0x000C
#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_PTM 0x000D
#define PCI_SUBDEVICE_ID_CONNECT_TECH_NT960PCI 0x0100
#define PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2 0x0201
#define PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4 0x0202
#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232 0x0300
#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232 0x0301
#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232 0x0302
#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1 0x0310
#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2 0x0311
#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4 0x0312
#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2 0x0320
#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4 0x0321
#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8 0x0322
#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485 0x0330
#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485 0x0331
#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485 0x0332
#define PCI_VENDOR_ID_NVIDIA_SGS 0x12d2 #define PCI_VENDOR_ID_NVIDIA_SGS 0x12d2