[PATCH] sata_sil24: enable 64bit
Enable 64bit. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
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bad28a37f5
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26ec634c31
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@ -485,6 +485,7 @@ static int sil24_softreset(struct ata_port *ap, unsigned int *class)
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prb->fis[1] = 0; /* no PM yet */
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writel((u32)paddr, port + PORT_CMD_ACTIVATE);
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writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4);
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mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
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irq_stat = ata_wait_register(port + PORT_IRQ_STAT, mask, 0x0,
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@ -644,6 +645,8 @@ static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc)
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dma_addr_t paddr = pp->cmd_block_dma + qc->tag * sizeof(*pp->cmd_block);
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writel((u32)paddr, port + PORT_CMD_ACTIVATE);
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writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4);
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return 0;
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}
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@ -980,11 +983,17 @@ static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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/*
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* Configure the device
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*/
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/*
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* FIXME: This device is certainly 64-bit capable. We just
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* don't know how to use it. After fixing 32bit activation in
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* this function, enable 64bit masks here.
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*/
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if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
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rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
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if (rc) {
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rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
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if (rc) {
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dev_printk(KERN_ERR, &pdev->dev,
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"64-bit DMA enable failed\n");
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goto out_free;
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}
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}
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} else {
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rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
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if (rc) {
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dev_printk(KERN_ERR, &pdev->dev,
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@ -997,6 +1006,7 @@ static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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"32-bit consistent DMA enable failed\n");
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goto out_free;
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}
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}
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/* GPIO off */
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writel(0, host_base + HOST_FLASH_CMD);
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@ -1053,9 +1063,8 @@ static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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writel(0x0000, port + PORT_CRC_ERR_CNT);
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writel(0x0000, port + PORT_HSHK_ERR_CNT);
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/* FIXME: 32bit activation? */
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writel(0, port + PORT_ACTIVATE_UPPER_ADDR);
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writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_STAT);
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/* Always use 64bit activation */
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writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
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/* Configure interrupts */
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writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
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