i40e: Use the new rx ctl register helpers. Don't use AQ calls from clear_hw.
Use the new AdminQ functions for safely accessing the Rx control registers that may be affected by heavy small packet traffic. We can't use AdminQ calls in i40e_clear_hw() because the HW is being initialized and the AdminQ is not alive. We recently added an AQ related replacement for reading PFLAN_QALLOC, and this patch puts back the original register read. Change-ID: Ib027168c954a5733299aa3a4ce5f8218c6bb5636 Signed-off-by: Shannon Nelson <shannon.nelson@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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@ -1328,7 +1328,7 @@ void i40e_clear_hw(struct i40e_hw *hw)
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num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
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I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
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val = i40e_read_rx_ctl(hw, I40E_PFLAN_QALLOC);
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val = rd32(hw, I40E_PFLAN_QALLOC);
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base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
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I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
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j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
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@ -2181,8 +2181,8 @@ static int i40e_get_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd,
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static int i40e_set_rss_hash_opt(struct i40e_pf *pf, struct ethtool_rxnfc *nfc)
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{
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struct i40e_hw *hw = &pf->hw;
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u64 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
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((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
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u64 hena = (u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0)) |
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((u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1)) << 32);
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/* RSS does not support anything other than hashing
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* to queues on src and dst IPs and ports
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@ -2291,8 +2291,8 @@ static int i40e_set_rss_hash_opt(struct i40e_pf *pf, struct ethtool_rxnfc *nfc)
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return -EINVAL;
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}
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wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
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wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
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i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (u32)hena);
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i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
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i40e_flush(hw);
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/* Save setting for future output/update */
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@ -295,11 +295,11 @@ void i40e_init_pf_fcoe(struct i40e_pf *pf)
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}
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/* enable FCoE hash filter */
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val = rd32(hw, I40E_PFQF_HENA(1));
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val = i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1));
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val |= BIT(I40E_FILTER_PCTYPE_FCOE_OX - 32);
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val |= BIT(I40E_FILTER_PCTYPE_FCOE_RX - 32);
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val &= I40E_PFQF_HENA_PTYPE_ENA_MASK;
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wr32(hw, I40E_PFQF_HENA(1), val);
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i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), val);
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/* enable flag */
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pf->flags |= I40E_FLAG_FCOE_ENABLED;
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@ -317,11 +317,11 @@ void i40e_init_pf_fcoe(struct i40e_pf *pf)
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pf->filter_settings.fcoe_cntx_num = I40E_DMA_CNTX_SIZE_4K;
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/* Setup max frame with FCoE_MTU plus L2 overheads */
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val = rd32(hw, I40E_GLFCOE_RCTL);
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val = i40e_read_rx_ctl(hw, I40E_GLFCOE_RCTL);
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val &= ~I40E_GLFCOE_RCTL_MAX_SIZE_MASK;
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val |= ((FCOE_MTU + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
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<< I40E_GLFCOE_RCTL_MAX_SIZE_SHIFT);
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wr32(hw, I40E_GLFCOE_RCTL, val);
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i40e_write_rx_ctl(hw, I40E_GLFCOE_RCTL, val);
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dev_info(&pf->pdev->dev, "FCoE is supported.\n");
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}
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@ -8032,7 +8032,7 @@ static int i40e_config_rss_reg(struct i40e_vsi *vsi, const u8 *seed,
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u32 *seed_dw = (u32 *)seed;
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for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
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wr32(hw, I40E_PFQF_HKEY(i), seed_dw[i]);
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i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), seed_dw[i]);
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}
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if (lut) {
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@ -8069,7 +8069,7 @@ static int i40e_get_rss_reg(struct i40e_vsi *vsi, u8 *seed,
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u32 *seed_dw = (u32 *)seed;
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for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
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seed_dw[i] = rd32(hw, I40E_PFQF_HKEY(i));
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seed_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
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}
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if (lut) {
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u32 *lut_dw = (u32 *)lut;
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@ -8152,19 +8152,19 @@ static int i40e_pf_config_rss(struct i40e_pf *pf)
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int ret;
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/* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
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hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
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((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
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hena = (u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0)) |
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((u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1)) << 32);
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hena |= i40e_pf_get_default_rss_hena(pf);
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wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
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wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
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i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (u32)hena);
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i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
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/* Determine the RSS table size based on the hardware capabilities */
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reg_val = rd32(hw, I40E_PFQF_CTL_0);
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reg_val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
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reg_val = (pf->rss_table_size == 512) ?
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(reg_val | I40E_PFQF_CTL_0_HASHLUTSIZE_512) :
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(reg_val & ~I40E_PFQF_CTL_0_HASHLUTSIZE_512);
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wr32(hw, I40E_PFQF_CTL_0, reg_val);
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i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, reg_val);
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/* Determine the RSS size of the VSI */
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if (!vsi->rss_size)
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@ -11211,8 +11211,8 @@ static void i40e_remove(struct pci_dev *pdev)
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i40e_ptp_stop(pf);
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/* Disable RSS in hw */
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wr32(hw, I40E_PFQF_HENA(0), 0);
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wr32(hw, I40E_PFQF_HENA(1), 0);
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i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
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i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
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/* no more scheduling of any task */
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set_bit(__I40E_DOWN, &pf->state);
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@ -602,8 +602,8 @@ static void i40e_enable_vf_mappings(struct i40e_vf *vf)
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* that VF queues be mapped using this method, even when they are
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* contiguous in real life
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*/
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wr32(hw, I40E_VSILAN_QBASE(vf->lan_vsi_id),
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I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK);
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i40e_write_rx_ctl(hw, I40E_VSILAN_QBASE(vf->lan_vsi_id),
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I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK);
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/* enable VF vplan_qtable mappings */
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reg = I40E_VPLAN_MAPENA_TXRX_ENA_MASK;
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@ -630,7 +630,8 @@ static void i40e_enable_vf_mappings(struct i40e_vf *vf)
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(j * 2) + 1);
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reg |= qid << 16;
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}
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wr32(hw, I40E_VSILAN_QTABLE(j, vf->lan_vsi_id), reg);
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i40e_write_rx_ctl(hw, I40E_VSILAN_QTABLE(j, vf->lan_vsi_id),
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reg);
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}
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i40e_flush(hw);
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