ARM: 5644/1: add bcmring core.c, clock.c, clock.h
add core.c, clock.c, and clock.h in mach-bcmring implement timer init, clocksource init, amba device init implement clock set/get enable/disable API add dummy clkdev.h Signed-off-by: Leo Chen <leochen@broadcom.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Leo Chen
Russell King
parent
4663712cc7
commit
278a6752e8
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/*****************************************************************************
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* Copyright 2001 - 2009 Broadcom Corporation. All rights reserved.
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2, available at
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* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
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*
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* Notwithstanding the above, under no circumstances may you combine this
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* software in any way with any other Broadcom software provided under a
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* license other than the GPL, without Broadcom's express prior written
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* consent.
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*****************************************************************************/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/device.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/string.h>
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#include <linux/clk.h>
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#include <linux/spinlock.h>
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#include <mach/csp/hw_cfg.h>
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#include <mach/csp/chipcHw_def.h>
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#include <mach/csp/chipcHw_reg.h>
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#include <mach/csp/chipcHw_inline.h>
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#include <asm/clkdev.h>
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#include "clock.h"
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#define clk_is_primary(x) ((x)->type & CLK_TYPE_PRIMARY)
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#define clk_is_pll1(x) ((x)->type & CLK_TYPE_PLL1)
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#define clk_is_pll2(x) ((x)->type & CLK_TYPE_PLL2)
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#define clk_is_programmable(x) ((x)->type & CLK_TYPE_PROGRAMMABLE)
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#define clk_is_bypassable(x) ((x)->type & CLK_TYPE_BYPASSABLE)
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#define clk_is_using_xtal(x) ((x)->mode & CLK_MODE_XTAL)
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static DEFINE_SPINLOCK(clk_lock);
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static void __clk_enable(struct clk *clk)
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{
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if (!clk)
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return;
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/* enable parent clock first */
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if (clk->parent)
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__clk_enable(clk->parent);
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if (clk->use_cnt++ == 0) {
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if (clk_is_pll1(clk)) { /* PLL1 */
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chipcHw_pll1Enable(clk->rate_hz, 0);
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} else if (clk_is_pll2(clk)) { /* PLL2 */
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chipcHw_pll2Enable(clk->rate_hz);
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} else if (clk_is_using_xtal(clk)) { /* source is crystal */
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if (!clk_is_primary(clk))
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chipcHw_bypassClockEnable(clk->csp_id);
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} else { /* source is PLL */
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chipcHw_setClockEnable(clk->csp_id);
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}
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}
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}
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int clk_enable(struct clk *clk)
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{
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unsigned long flags;
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if (!clk)
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return -EINVAL;
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spin_lock_irqsave(&clk_lock, flags);
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__clk_enable(clk);
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spin_unlock_irqrestore(&clk_lock, flags);
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return 0;
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}
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EXPORT_SYMBOL(clk_enable);
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static void __clk_disable(struct clk *clk)
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{
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if (!clk)
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return;
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BUG_ON(clk->use_cnt == 0);
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if (--clk->use_cnt == 0) {
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if (clk_is_pll1(clk)) { /* PLL1 */
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chipcHw_pll1Disable();
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} else if (clk_is_pll2(clk)) { /* PLL2 */
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chipcHw_pll2Disable();
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} else if (clk_is_using_xtal(clk)) { /* source is crystal */
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if (!clk_is_primary(clk))
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chipcHw_bypassClockDisable(clk->csp_id);
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} else { /* source is PLL */
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chipcHw_setClockDisable(clk->csp_id);
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}
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}
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if (clk->parent)
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__clk_disable(clk->parent);
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}
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void clk_disable(struct clk *clk)
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{
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unsigned long flags;
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if (!clk)
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return;
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spin_lock_irqsave(&clk_lock, flags);
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__clk_disable(clk);
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spin_unlock_irqrestore(&clk_lock, flags);
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}
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EXPORT_SYMBOL(clk_disable);
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unsigned long clk_get_rate(struct clk *clk)
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{
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if (!clk)
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return 0;
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return clk->rate_hz;
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}
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EXPORT_SYMBOL(clk_get_rate);
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long clk_round_rate(struct clk *clk, unsigned long rate)
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{
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unsigned long flags;
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unsigned long actual;
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unsigned long rate_hz;
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if (!clk)
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return -EINVAL;
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if (!clk_is_programmable(clk))
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return -EINVAL;
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if (clk->use_cnt)
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return -EBUSY;
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spin_lock_irqsave(&clk_lock, flags);
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actual = clk->parent->rate_hz;
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rate_hz = min(actual, rate);
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spin_unlock_irqrestore(&clk_lock, flags);
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return rate_hz;
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}
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EXPORT_SYMBOL(clk_round_rate);
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int clk_set_rate(struct clk *clk, unsigned long rate)
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{
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unsigned long flags;
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unsigned long actual;
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unsigned long rate_hz;
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if (!clk)
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return -EINVAL;
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if (!clk_is_programmable(clk))
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return -EINVAL;
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if (clk->use_cnt)
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return -EBUSY;
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spin_lock_irqsave(&clk_lock, flags);
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actual = clk->parent->rate_hz;
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rate_hz = min(actual, rate);
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rate_hz = chipcHw_setClockFrequency(clk->csp_id, rate_hz);
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clk->rate_hz = rate_hz;
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spin_unlock_irqrestore(&clk_lock, flags);
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return 0;
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}
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EXPORT_SYMBOL(clk_set_rate);
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struct clk *clk_get_parent(struct clk *clk)
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{
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if (!clk)
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return NULL;
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return clk->parent;
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}
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EXPORT_SYMBOL(clk_get_parent);
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int clk_set_parent(struct clk *clk, struct clk *parent)
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{
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unsigned long flags;
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struct clk *old_parent;
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if (!clk || !parent)
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return -EINVAL;
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if (!clk_is_primary(parent) || !clk_is_bypassable(clk))
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return -EINVAL;
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/* if more than one user, parent is not allowed */
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if (clk->use_cnt > 1)
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return -EBUSY;
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if (clk->parent == parent)
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return 0;
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spin_lock_irqsave(&clk_lock, flags);
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old_parent = clk->parent;
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clk->parent = parent;
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if (clk_is_using_xtal(parent))
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clk->mode |= CLK_MODE_XTAL;
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else
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clk->mode &= (~CLK_MODE_XTAL);
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/* if clock is active */
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if (clk->use_cnt != 0) {
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clk->use_cnt--;
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/* enable clock with the new parent */
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__clk_enable(clk);
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/* disable the old parent */
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__clk_disable(old_parent);
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}
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spin_unlock_irqrestore(&clk_lock, flags);
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return 0;
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}
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EXPORT_SYMBOL(clk_set_parent);
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@ -0,0 +1,33 @@
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/*****************************************************************************
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* Copyright 2001 - 2009 Broadcom Corporation. All rights reserved.
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2, available at
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* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
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*
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* Notwithstanding the above, under no circumstances may you combine this
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* software in any way with any other Broadcom software provided under a
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* license other than the GPL, without Broadcom's express prior written
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* consent.
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*****************************************************************************/
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#include <mach/csp/chipcHw_def.h>
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#define CLK_TYPE_PRIMARY 1 /* primary clock must NOT have a parent */
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#define CLK_TYPE_PLL1 2 /* PPL1 */
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#define CLK_TYPE_PLL2 4 /* PPL2 */
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#define CLK_TYPE_PROGRAMMABLE 8 /* programmable clock rate */
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#define CLK_TYPE_BYPASSABLE 16 /* parent can be changed */
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#define CLK_MODE_XTAL 1 /* clock source is from crystal */
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struct clk {
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const char *name; /* clock name */
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unsigned int type; /* clock type */
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unsigned int mode; /* current mode */
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volatile int use_bypass; /* indicate if it's in bypass mode */
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chipcHw_CLOCK_e csp_id; /* clock ID for CSP CHIPC */
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unsigned long rate_hz; /* clock rate in Hz */
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unsigned int use_cnt; /* usage count */
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struct clk *parent; /* parent clock */
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};
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@ -0,0 +1,367 @@
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/*
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* derived from linux/arch/arm/mach-versatile/core.c
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* linux/arch/arm/mach-bcmring/core.c
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*
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* Copyright (C) 1999 - 2003 ARM Limited
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* Copyright (C) 2000 Deep Blue Solutions Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/* Portions copyright Broadcom 2008 */
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#include <linux/init.h>
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/platform_device.h>
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#include <linux/sysdev.h>
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#include <linux/interrupt.h>
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#include <linux/amba/bus.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/amba/bus.h>
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#include <mach/csp/mm_addr.h>
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#include <mach/hardware.h>
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#include <asm/clkdev.h>
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#include <linux/io.h>
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#include <asm/irq.h>
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#include <asm/hardware/arm_timer.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/flash.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/time.h>
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#include <asm/mach/map.h>
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#include <asm/mach/mmc.h>
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#include <cfg_global.h>
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#include "clock.h"
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#include <csp/secHw.h>
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#include <mach/csp/secHw_def.h>
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#include <mach/csp/chipcHw_inline.h>
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#include <mach/csp/tmrHw_reg.h>
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#define AMBA_DEVICE(name, initname, base, plat, size) \
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static struct amba_device name##_device = { \
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.dev = { \
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.coherent_dma_mask = ~0, \
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.init_name = initname, \
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.platform_data = plat \
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}, \
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.res = { \
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.start = MM_ADDR_IO_##base, \
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.end = MM_ADDR_IO_##base + (size) - 1, \
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.flags = IORESOURCE_MEM \
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}, \
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.dma_mask = ~0, \
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.irq = { \
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IRQ_##base \
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} \
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}
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AMBA_DEVICE(uartA, "uarta", UARTA, NULL, SZ_4K);
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AMBA_DEVICE(uartB, "uartb", UARTB, NULL, SZ_4K);
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static struct clk pll1_clk = {
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.name = "PLL1",
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.type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL1,
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.rate_hz = 2000000000,
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.use_cnt = 7,
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};
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static struct clk uart_clk = {
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.name = "UART",
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.type = CLK_TYPE_PROGRAMMABLE,
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.csp_id = chipcHw_CLOCK_UART,
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.rate_hz = HW_CFG_UART_CLK_HZ,
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.parent = &pll1_clk,
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};
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static struct clk_lookup lookups[] = {
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{ /* UART0 */
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.dev_id = "uarta",
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.clk = &uart_clk,
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}, { /* UART1 */
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.dev_id = "uartb",
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.clk = &uart_clk,
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}
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};
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static struct amba_device *amba_devs[] __initdata = {
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&uartA_device,
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&uartB_device,
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};
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void __init bcmring_amba_init(void)
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{
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int i;
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u32 bus_clock;
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/* Linux is run initially in non-secure mode. Secure peripherals */
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/* generate FIQ, and must be handled in secure mode. Until we have */
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/* a linux security monitor implementation, keep everything in */
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/* non-secure mode. */
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chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_SPU);
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secHw_setUnsecure(secHw_BLK_MASK_CHIP_CONTROL |
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secHw_BLK_MASK_KEY_SCAN |
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secHw_BLK_MASK_TOUCH_SCREEN |
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secHw_BLK_MASK_UART0 |
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secHw_BLK_MASK_UART1 |
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secHw_BLK_MASK_WATCHDOG |
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secHw_BLK_MASK_SPUM |
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secHw_BLK_MASK_DDR2 |
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secHw_BLK_MASK_SPU |
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secHw_BLK_MASK_PKA |
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secHw_BLK_MASK_RNG |
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secHw_BLK_MASK_RTC |
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secHw_BLK_MASK_OTP |
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secHw_BLK_MASK_BOOT |
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secHw_BLK_MASK_MPU |
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secHw_BLK_MASK_TZCTRL | secHw_BLK_MASK_INTR);
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/* Only the devices attached to the AMBA bus are enabled just before the bus is */
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/* scanned and the drivers are loaded. The clocks need to be on for the AMBA bus */
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/* driver to access these blocks. The bus is probed, and the drivers are loaded. */
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/* FIXME Need to remove enable of PIF once CLCD clock enable used properly in FPGA. */
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bus_clock = chipcHw_REG_BUS_CLOCK_GE
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| chipcHw_REG_BUS_CLOCK_SDIO0 | chipcHw_REG_BUS_CLOCK_SDIO1;
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chipcHw_busInterfaceClockEnable(bus_clock);
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for (i = 0; i < ARRAY_SIZE(lookups); i++)
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clkdev_add(&lookups[i]);
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for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
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struct amba_device *d = amba_devs[i];
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amba_device_register(d, &iomem_resource);
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}
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}
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/*
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* Where is the timer (VA)?
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*/
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#define TIMER0_VA_BASE MM_IO_BASE_TMR
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#define TIMER1_VA_BASE (MM_IO_BASE_TMR + 0x20)
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#define TIMER2_VA_BASE (MM_IO_BASE_TMR + 0x40)
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#define TIMER3_VA_BASE (MM_IO_BASE_TMR + 0x60)
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/* Timer 0 - 25 MHz, Timer3 at bus clock rate, typically 150-166 MHz */
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#if defined(CONFIG_ARCH_FPGA11107)
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/* fpga cpu/bus are currently 30 times slower so scale frequency as well to */
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/* slow down Linux's sense of time */
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#define TIMER0_FREQUENCY_MHZ (tmrHw_LOW_FREQUENCY_MHZ * 30)
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#define TIMER1_FREQUENCY_MHZ (tmrHw_LOW_FREQUENCY_MHZ * 30)
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#define TIMER3_FREQUENCY_MHZ (tmrHw_HIGH_FREQUENCY_MHZ * 30)
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#define TIMER3_FREQUENCY_KHZ (tmrHw_HIGH_FREQUENCY_HZ / 1000 * 30)
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#else
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#define TIMER0_FREQUENCY_MHZ tmrHw_LOW_FREQUENCY_MHZ
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#define TIMER1_FREQUENCY_MHZ tmrHw_LOW_FREQUENCY_MHZ
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#define TIMER3_FREQUENCY_MHZ tmrHw_HIGH_FREQUENCY_MHZ
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#define TIMER3_FREQUENCY_KHZ (tmrHw_HIGH_FREQUENCY_HZ / 1000)
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#endif
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#define TICKS_PER_uSEC TIMER0_FREQUENCY_MHZ
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/*
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* These are useconds NOT ticks.
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*
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*/
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#define mSEC_1 1000
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#define mSEC_5 (mSEC_1 * 5)
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#define mSEC_10 (mSEC_1 * 10)
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#define mSEC_25 (mSEC_1 * 25)
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#define SEC_1 (mSEC_1 * 1000)
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/*
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* How long is the timer interval?
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*/
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#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
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#if TIMER_INTERVAL >= 0x100000
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#define TIMER_RELOAD (TIMER_INTERVAL >> 8)
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#define TIMER_DIVISOR (TIMER_CTRL_DIV256)
|
||||
#define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
|
||||
#elif TIMER_INTERVAL >= 0x10000
|
||||
#define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */
|
||||
#define TIMER_DIVISOR (TIMER_CTRL_DIV16)
|
||||
#define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
|
||||
#else
|
||||
#define TIMER_RELOAD (TIMER_INTERVAL)
|
||||
#define TIMER_DIVISOR (TIMER_CTRL_DIV1)
|
||||
#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
|
||||
#endif
|
||||
|
||||
static void timer_set_mode(enum clock_event_mode mode,
|
||||
struct clock_event_device *clk)
|
||||
{
|
||||
unsigned long ctrl;
|
||||
|
||||
switch (mode) {
|
||||
case CLOCK_EVT_MODE_PERIODIC:
|
||||
writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
|
||||
|
||||
ctrl = TIMER_CTRL_PERIODIC;
|
||||
ctrl |=
|
||||
TIMER_DIVISOR | TIMER_CTRL_32BIT | TIMER_CTRL_IE |
|
||||
TIMER_CTRL_ENABLE;
|
||||
break;
|
||||
case CLOCK_EVT_MODE_ONESHOT:
|
||||
/* period set, and timer enabled in 'next_event' hook */
|
||||
ctrl = TIMER_CTRL_ONESHOT;
|
||||
ctrl |= TIMER_DIVISOR | TIMER_CTRL_32BIT | TIMER_CTRL_IE;
|
||||
break;
|
||||
case CLOCK_EVT_MODE_UNUSED:
|
||||
case CLOCK_EVT_MODE_SHUTDOWN:
|
||||
default:
|
||||
ctrl = 0;
|
||||
}
|
||||
|
||||
writel(ctrl, TIMER0_VA_BASE + TIMER_CTRL);
|
||||
}
|
||||
|
||||
static int timer_set_next_event(unsigned long evt,
|
||||
struct clock_event_device *unused)
|
||||
{
|
||||
unsigned long ctrl = readl(TIMER0_VA_BASE + TIMER_CTRL);
|
||||
|
||||
writel(evt, TIMER0_VA_BASE + TIMER_LOAD);
|
||||
writel(ctrl | TIMER_CTRL_ENABLE, TIMER0_VA_BASE + TIMER_CTRL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct clock_event_device timer0_clockevent = {
|
||||
.name = "timer0",
|
||||
.shift = 32,
|
||||
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
|
||||
.set_mode = timer_set_mode,
|
||||
.set_next_event = timer_set_next_event,
|
||||
};
|
||||
|
||||
/*
|
||||
* IRQ handler for the timer
|
||||
*/
|
||||
static irqreturn_t bcmring_timer_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
struct clock_event_device *evt = &timer0_clockevent;
|
||||
|
||||
writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
|
||||
|
||||
evt->event_handler(evt);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static struct irqaction bcmring_timer_irq = {
|
||||
.name = "bcmring Timer Tick",
|
||||
.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
|
||||
.handler = bcmring_timer_interrupt,
|
||||
};
|
||||
|
||||
static cycle_t bcmring_get_cycles_timer1(void)
|
||||
{
|
||||
return ~readl(TIMER1_VA_BASE + TIMER_VALUE);
|
||||
}
|
||||
|
||||
static cycle_t bcmring_get_cycles_timer3(void)
|
||||
{
|
||||
return ~readl(TIMER3_VA_BASE + TIMER_VALUE);
|
||||
}
|
||||
|
||||
static struct clocksource clocksource_bcmring_timer1 = {
|
||||
.name = "timer1",
|
||||
.rating = 200,
|
||||
.read = bcmring_get_cycles_timer1,
|
||||
.mask = CLOCKSOURCE_MASK(32),
|
||||
.shift = 20,
|
||||
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
|
||||
};
|
||||
|
||||
static struct clocksource clocksource_bcmring_timer3 = {
|
||||
.name = "timer3",
|
||||
.rating = 100,
|
||||
.read = bcmring_get_cycles_timer3,
|
||||
.mask = CLOCKSOURCE_MASK(32),
|
||||
.shift = 20,
|
||||
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
|
||||
};
|
||||
|
||||
static int __init bcmring_clocksource_init(void)
|
||||
{
|
||||
/* setup timer1 as free-running clocksource */
|
||||
writel(0, TIMER1_VA_BASE + TIMER_CTRL);
|
||||
writel(0xffffffff, TIMER1_VA_BASE + TIMER_LOAD);
|
||||
writel(0xffffffff, TIMER1_VA_BASE + TIMER_VALUE);
|
||||
writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
|
||||
TIMER1_VA_BASE + TIMER_CTRL);
|
||||
|
||||
clocksource_bcmring_timer1.mult =
|
||||
clocksource_khz2mult(TIMER1_FREQUENCY_MHZ * 1000,
|
||||
clocksource_bcmring_timer1.shift);
|
||||
clocksource_register(&clocksource_bcmring_timer1);
|
||||
|
||||
/* setup timer3 as free-running clocksource */
|
||||
writel(0, TIMER3_VA_BASE + TIMER_CTRL);
|
||||
writel(0xffffffff, TIMER3_VA_BASE + TIMER_LOAD);
|
||||
writel(0xffffffff, TIMER3_VA_BASE + TIMER_VALUE);
|
||||
writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
|
||||
TIMER3_VA_BASE + TIMER_CTRL);
|
||||
|
||||
clocksource_bcmring_timer3.mult =
|
||||
clocksource_khz2mult(TIMER3_FREQUENCY_KHZ,
|
||||
clocksource_bcmring_timer3.shift);
|
||||
clocksource_register(&clocksource_bcmring_timer3);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Set up timer interrupt, and return the current time in seconds.
|
||||
*/
|
||||
void __init bcmring_init_timer(void)
|
||||
{
|
||||
printk(KERN_INFO "bcmring_init_timer\n");
|
||||
/*
|
||||
* Initialise to a known state (all timers off)
|
||||
*/
|
||||
writel(0, TIMER0_VA_BASE + TIMER_CTRL);
|
||||
writel(0, TIMER1_VA_BASE + TIMER_CTRL);
|
||||
writel(0, TIMER2_VA_BASE + TIMER_CTRL);
|
||||
writel(0, TIMER3_VA_BASE + TIMER_CTRL);
|
||||
|
||||
/*
|
||||
* Make irqs happen for the system timer
|
||||
*/
|
||||
setup_irq(IRQ_TIMER0, &bcmring_timer_irq);
|
||||
|
||||
bcmring_clocksource_init();
|
||||
|
||||
timer0_clockevent.mult =
|
||||
div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
|
||||
timer0_clockevent.max_delta_ns =
|
||||
clockevent_delta2ns(0xffffffff, &timer0_clockevent);
|
||||
timer0_clockevent.min_delta_ns =
|
||||
clockevent_delta2ns(0xf, &timer0_clockevent);
|
||||
|
||||
timer0_clockevent.cpumask = cpumask_of(0);
|
||||
clockevents_register_device(&timer0_clockevent);
|
||||
}
|
||||
|
||||
struct sys_timer bcmring_timer = {
|
||||
.init = bcmring_init_timer,
|
||||
};
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
#ifndef __ASM_MACH_CLKDEV_H
|
||||
#define __ASM_MACH_CLKDEV_H
|
||||
|
||||
#define __clk_get(clk) ({ 1; })
|
||||
#define __clk_put(clk) do { } while (0)
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue