RDMA/cxgb4: Fix accounting for unsignaled SQ WRs to deal with wrap
When determining how many WRs are completed with a signaled CQE, correctly deal with queue wraps. Signed-off-by: Steve Wise <swise@opengridcomputing.com> Signed-off-by: Vipul Pandya <vipul@chelsio.com> Signed-off-by: Roland Dreier <roland@purestorage.com>
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@ -611,9 +611,12 @@ proc_cqe:
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* to the first unsignaled one, and idx points to the
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* signaled one. So adjust in_use based on this delta.
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* if this is not completing any unsigned wrs, then the
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* delta will be 0.
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* delta will be 0. Handle wrapping also!
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*/
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wq->sq.in_use -= idx - wq->sq.cidx;
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if (idx < wq->sq.cidx)
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wq->sq.in_use -= wq->sq.size + idx - wq->sq.cidx;
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else
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wq->sq.in_use -= idx - wq->sq.cidx;
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BUG_ON(wq->sq.in_use < 0 && wq->sq.in_use < wq->sq.size);
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wq->sq.cidx = (uint16_t)idx;
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