sh: Add support for SH7201 CPU subtype.
This patch adds support for the SH-2A FPU based SH7201 processor subtype. Signed-off-by: Peter Griffin <pgriffin@mpc-data.co.uk> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Peter Griffin
Paul Mundt
parent
135210b378
commit
2825999e8a
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@ -185,6 +185,11 @@ config CPU_SUBTYPE_SH7619
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# SH-2A Processor Support
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config CPU_SUBTYPE_SH7201
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bool "Support SH7201 processor"
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select CPU_SH2A
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select CPU_HAS_FPU
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config CPU_SUBTYPE_SH7203
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bool "Support SH7203 processor"
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select CPU_SH2A
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@ -25,7 +25,7 @@ static void __init check_bugs(void)
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case CPU_SH7619:
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*p++ = '2';
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break;
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case CPU_SH7203 ... CPU_MXG:
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case CPU_SH7201 ... CPU_MXG:
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*p++ = '2';
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*p++ = 'a';
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break;
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@ -18,7 +18,7 @@ enum cpu_type {
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CPU_SH7619,
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/* SH-2A types */
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CPU_SH7203, CPU_SH7206, CPU_SH7263, CPU_MXG,
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CPU_SH7201, CPU_SH7203, CPU_SH7206, CPU_SH7263, CPU_MXG,
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/* SH-3 types */
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CPU_SH7705, CPU_SH7706, CPU_SH7707,
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@ -8,9 +8,10 @@ common-y += ex.o entry.o
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obj-$(CONFIG_SH_FPU) += fpu.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7206) += setup-sh7206.o clock-sh7206.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7201) += setup-sh7201.o clock-sh7201.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7203) += setup-sh7203.o clock-sh7203.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7263) += setup-sh7203.o clock-sh7203.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7206) += setup-sh7206.o clock-sh7206.o
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obj-$(CONFIG_CPU_SUBTYPE_MXG) += setup-mxg.o clock-sh7206.o
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# Pinmux setup
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@ -0,0 +1,85 @@
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/*
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* arch/sh/kernel/cpu/sh2a/clock-sh7201.c
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*
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* SH7201 support for the clock framework
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*
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* Copyright (C) 2008 Peter Griffin <pgriffin@mpc-data.co.uk>
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*
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* Based on clock-sh4.c
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* Copyright (C) 2005 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <asm/clock.h>
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#include <asm/freq.h>
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#include <asm/io.h>
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const static int pll1rate[]={1,2,3,4,6,8};
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const static int pfc_divisors[]={1,2,3,4,6,8,12};
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#define ifc_divisors pfc_divisors
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#if (CONFIG_SH_CLK_MD == 0)
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#define PLL2 (4)
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#elif (CONFIG_SH_CLK_MD == 2)
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#define PLL2 (2)
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#elif (CONFIG_SH_CLK_MD == 3)
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#define PLL2 (1)
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#else
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#error "Illegal Clock Mode!"
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#endif
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static void master_clk_init(struct clk *clk)
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{
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clk->rate = 10000000 * PLL2 * pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0007];
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}
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static struct clk_ops sh7201_master_clk_ops = {
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.init = master_clk_init,
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};
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static void module_clk_recalc(struct clk *clk)
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{
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int idx = (ctrl_inw(FREQCR) & 0x0007);
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clk->rate = clk->parent->rate / pfc_divisors[idx];
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}
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static struct clk_ops sh7201_module_clk_ops = {
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.recalc = module_clk_recalc,
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};
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static void bus_clk_recalc(struct clk *clk)
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{
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int idx = (ctrl_inw(FREQCR) & 0x0007);
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clk->rate = clk->parent->rate / pfc_divisors[idx];
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}
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static struct clk_ops sh7201_bus_clk_ops = {
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.recalc = bus_clk_recalc,
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};
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static void cpu_clk_recalc(struct clk *clk)
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{
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int idx = ((ctrl_inw(FREQCR) >> 4) & 0x0007);
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clk->rate = clk->parent->rate / ifc_divisors[idx];
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}
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static struct clk_ops sh7201_cpu_clk_ops = {
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.recalc = cpu_clk_recalc,
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};
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static struct clk_ops *sh7201_clk_ops[] = {
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&sh7201_master_clk_ops,
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&sh7201_module_clk_ops,
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&sh7201_bus_clk_ops,
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&sh7201_cpu_clk_ops,
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};
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void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
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{
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if (idx < ARRAY_SIZE(sh7201_clk_ops))
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*ops = sh7201_clk_ops[idx];
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}
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@ -18,16 +18,17 @@ int __init detect_cpu_and_cache_system(void)
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/* All SH-2A CPUs have support for 16 and 32-bit opcodes.. */
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boot_cpu_data.flags |= CPU_HAS_OP32;
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#if defined(CONFIG_CPU_SUBTYPE_SH7203)
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#if defined(CONFIG_CPU_SUBTYPE_SH7201)
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boot_cpu_data.type = CPU_SH7201;
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boot_cpu_data.flags |= CPU_HAS_FPU;
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#elif defined(CONFIG_CPU_SUBTYPE_SH7203)
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boot_cpu_data.type = CPU_SH7203;
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/* SH7203 has an FPU.. */
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boot_cpu_data.flags |= CPU_HAS_FPU;
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#elif defined(CONFIG_CPU_SUBTYPE_SH7263)
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boot_cpu_data.type = CPU_SH7263;
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boot_cpu_data.flags |= CPU_HAS_FPU;
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#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
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boot_cpu_data.type = CPU_SH7206;
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/* While SH7206 has a DSP.. */
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boot_cpu_data.flags |= CPU_HAS_DSP;
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#elif defined(CONFIG_CPU_SUBTYPE_MXG)
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boot_cpu_data.type = CPU_MXG;
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@ -0,0 +1,331 @@
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/*
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* SH7201 setup
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*
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* Copyright (C) 2008 Peter Griffin pgriffin@mpc-data.co.uk
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/platform_device.h>
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#include <linux/init.h>
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#include <linux/serial.h>
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#include <linux/serial_sci.h>
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enum {
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UNUSED = 0,
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/* interrupt sources */
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IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
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PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
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ADC_ADI,
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MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D,
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MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F,
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MTU2_TGI1A, MTU2_TGI1B, MTU2_TCI1V, MTU2_TCI1U,
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MTU2_TGI2A, MTU2_TGI2B, MTU2_TCI2V, MTU2_TCI2U,
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MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D, MTU2_TCI3V,
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MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D, MTU2_TCI4V,
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MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W,
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RTC_ARM, RTC_PRD, RTC_CUP,
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WDT,
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IIC30_STPI, IIC30_NAKI, IIC30_RXI, IIC30_TXI, IIC30_TEI,
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IIC31_STPI, IIC31_NAKI, IIC31_RXI, IIC31_TXI, IIC31_TEI,
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IIC32_STPI, IIC32_NAKI, IIC32_RXI, IIC32_TXI, IIC32_TEI,
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DMAC0_DMINT0, DMAC1_DMINT1,
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DMAC2_DMINT2, DMAC3_DMINT3,
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SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI,
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SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI,
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SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI,
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SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI,
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SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI,
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SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI,
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SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI,
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SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI,
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DMAC0_DMINTA, DMAC4_DMINT4, DMAC5_DMINT5, DMAC6_DMINT6,
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DMAC7_DMINT7,
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RCAN0_ERS, RCAN0_OVR,
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RCAN0_SLE,
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RCAN0_RM0, RCAN0_RM1,
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RCAN1_ERS, RCAN1_OVR,
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RCAN1_SLE,
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RCAN1_RM0, RCAN1_RM1,
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SSI0_SSII, SSI1_SSII,
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TMR0_CMIA0, TMR0_CMIB0, TMR0_OVI0,
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TMR1_CMIA1, TMR1_CMIB1, TMR1_OVI1,
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/* interrupt groups */
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IRQ, PINT, ADC,
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MTU20_ABCD, MTU20_VEF, MTU21_AB, MTU21_VU, MTU22_AB, MTU22_VU,
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MTU23_ABCD, MTU24_ABCD, MTU25_UVW,
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RTC, IIC30, IIC31, IIC32,
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SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7,
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RCAN0, RCAN1, TMR0, TMR1
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};
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static struct intc_vect vectors[] __initdata = {
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INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
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INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
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INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
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INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
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INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
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INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
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INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
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INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
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INTC_IRQ(ADC_ADI, 92),
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INTC_IRQ(MTU2_TGI0A, 108), INTC_IRQ(MTU2_TGI0B, 109),
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INTC_IRQ(MTU2_TGI0C, 110), INTC_IRQ(MTU2_TGI0D, 111),
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INTC_IRQ(MTU2_TCI0V, 112),
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INTC_IRQ(MTU2_TGI0E, 113), INTC_IRQ(MTU2_TGI0F, 114),
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INTC_IRQ(MTU2_TGI1A, 116), INTC_IRQ(MTU2_TGI1B, 117),
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INTC_IRQ(MTU2_TCI1V, 120), INTC_IRQ(MTU2_TCI1U, 121),
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INTC_IRQ(MTU2_TGI2A, 124), INTC_IRQ(MTU2_TGI2B, 125),
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INTC_IRQ(MTU2_TCI2V, 128), INTC_IRQ(MTU2_TCI2U, 129),
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INTC_IRQ(MTU2_TGI3A, 132), INTC_IRQ(MTU2_TGI3B, 133),
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INTC_IRQ(MTU2_TGI3C, 134), INTC_IRQ(MTU2_TGI3D, 135),
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INTC_IRQ(MTU2_TCI3V, 136),
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INTC_IRQ(MTU2_TGI4A, 140), INTC_IRQ(MTU2_TGI4B, 141),
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INTC_IRQ(MTU2_TGI4C, 142), INTC_IRQ(MTU2_TGI4D, 143),
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INTC_IRQ(MTU2_TCI4V, 144),
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INTC_IRQ(MTU2_TGI5U, 148), INTC_IRQ(MTU2_TGI5V, 149),
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INTC_IRQ(MTU2_TGI5W, 150),
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INTC_IRQ(RTC_ARM, 152), INTC_IRQ(RTC_PRD, 153),
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INTC_IRQ(RTC_CUP, 154), INTC_IRQ(WDT, 156),
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INTC_IRQ(IIC30_STPI, 157), INTC_IRQ(IIC30_NAKI, 158),
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INTC_IRQ(IIC30_RXI, 159), INTC_IRQ(IIC30_TXI, 160),
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INTC_IRQ(IIC30_TEI, 161),
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INTC_IRQ(IIC31_STPI, 164), INTC_IRQ(IIC31_NAKI, 165),
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INTC_IRQ(IIC31_RXI, 166), INTC_IRQ(IIC31_TXI, 167),
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INTC_IRQ(IIC31_TEI, 168),
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INTC_IRQ(IIC32_STPI, 170), INTC_IRQ(IIC32_NAKI, 171),
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INTC_IRQ(IIC32_RXI, 172), INTC_IRQ(IIC32_TXI, 173),
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INTC_IRQ(IIC32_TEI, 174),
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INTC_IRQ(DMAC0_DMINT0, 176), INTC_IRQ(DMAC1_DMINT1, 177),
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INTC_IRQ(DMAC2_DMINT2, 178), INTC_IRQ(DMAC3_DMINT3, 179),
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INTC_IRQ(SCIF0_BRI, 180), INTC_IRQ(SCIF0_ERI, 181),
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INTC_IRQ(SCIF0_RXI, 182), INTC_IRQ(SCIF0_TXI, 183),
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INTC_IRQ(SCIF1_BRI, 184), INTC_IRQ(SCIF1_ERI, 185),
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INTC_IRQ(SCIF1_RXI, 186), INTC_IRQ(SCIF1_TXI, 187),
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INTC_IRQ(SCIF2_BRI, 188), INTC_IRQ(SCIF2_ERI, 189),
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INTC_IRQ(SCIF2_RXI, 190), INTC_IRQ(SCIF2_TXI, 191),
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INTC_IRQ(SCIF3_BRI, 192), INTC_IRQ(SCIF3_ERI, 193),
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INTC_IRQ(SCIF3_RXI, 194), INTC_IRQ(SCIF3_TXI, 195),
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INTC_IRQ(SCIF4_BRI, 196), INTC_IRQ(SCIF4_ERI, 197),
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INTC_IRQ(SCIF4_RXI, 198), INTC_IRQ(SCIF4_TXI, 199),
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INTC_IRQ(SCIF5_BRI, 200), INTC_IRQ(SCIF5_ERI, 201),
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INTC_IRQ(SCIF5_RXI, 202), INTC_IRQ(SCIF5_TXI, 203),
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INTC_IRQ(SCIF6_BRI, 204), INTC_IRQ(SCIF6_ERI, 205),
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INTC_IRQ(SCIF6_RXI, 206), INTC_IRQ(SCIF6_TXI, 207),
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INTC_IRQ(SCIF7_BRI, 208), INTC_IRQ(SCIF7_ERI, 209),
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INTC_IRQ(SCIF7_RXI, 210), INTC_IRQ(SCIF7_TXI, 211),
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INTC_IRQ(DMAC0_DMINTA, 212), INTC_IRQ(DMAC4_DMINT4, 216),
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INTC_IRQ(DMAC5_DMINT5, 217), INTC_IRQ(DMAC6_DMINT6, 218),
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INTC_IRQ(DMAC7_DMINT7, 219),
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INTC_IRQ(RCAN0_ERS, 228), INTC_IRQ(RCAN0_OVR, 229),
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INTC_IRQ(RCAN0_SLE, 230),
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INTC_IRQ(RCAN0_RM0, 231), INTC_IRQ(RCAN0_RM1, 232),
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INTC_IRQ(RCAN1_ERS, 234), INTC_IRQ(RCAN1_OVR, 235),
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INTC_IRQ(RCAN1_SLE, 236),
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INTC_IRQ(RCAN1_RM0, 237), INTC_IRQ(RCAN1_RM1, 238),
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INTC_IRQ(SSI0_SSII, 244), INTC_IRQ(SSI1_SSII, 245),
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INTC_IRQ(TMR0_CMIA0, 246), INTC_IRQ(TMR0_CMIB0, 247),
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INTC_IRQ(TMR0_OVI0, 248),
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INTC_IRQ(TMR1_CMIA1, 252), INTC_IRQ(TMR1_CMIB1, 253),
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INTC_IRQ(TMR1_OVI1, 254),
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};
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static struct intc_group groups[] __initdata = {
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INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
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PINT4, PINT5, PINT6, PINT7),
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INTC_GROUP(MTU20_ABCD, MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D),
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INTC_GROUP(MTU20_VEF, MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F),
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INTC_GROUP(MTU21_AB, MTU2_TGI1A, MTU2_TGI1B),
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INTC_GROUP(MTU21_VU, MTU2_TCI1V, MTU2_TCI1U),
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INTC_GROUP(MTU22_AB, MTU2_TGI2A, MTU2_TGI2B),
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INTC_GROUP(MTU22_VU, MTU2_TCI2V, MTU2_TCI2U),
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INTC_GROUP(MTU23_ABCD, MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D),
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INTC_GROUP(MTU24_ABCD, MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D),
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INTC_GROUP(MTU25_UVW, MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W),
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INTC_GROUP(RTC, RTC_ARM, RTC_PRD, RTC_CUP ),
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INTC_GROUP(IIC30, IIC30_STPI, IIC30_NAKI, IIC30_RXI, IIC30_TXI,
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IIC30_TEI),
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INTC_GROUP(IIC31, IIC31_STPI, IIC31_NAKI, IIC31_RXI, IIC31_TXI,
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IIC31_TEI),
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INTC_GROUP(IIC32, IIC32_STPI, IIC32_NAKI, IIC32_RXI, IIC32_TXI,
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IIC32_TEI),
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INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
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INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI),
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INTC_GROUP(SCIF2, SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI),
|
||||
INTC_GROUP(SCIF3, SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI),
|
||||
INTC_GROUP(SCIF4, SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI),
|
||||
INTC_GROUP(SCIF5, SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI),
|
||||
INTC_GROUP(SCIF6, SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI),
|
||||
INTC_GROUP(SCIF7, SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI),
|
||||
|
||||
INTC_GROUP(RCAN0, RCAN0_ERS, RCAN0_OVR, RCAN0_RM0, RCAN0_RM1,
|
||||
RCAN0_SLE),
|
||||
INTC_GROUP(RCAN1, RCAN1_ERS, RCAN1_OVR, RCAN1_RM0, RCAN1_RM1,
|
||||
RCAN1_SLE),
|
||||
|
||||
INTC_GROUP(TMR0, TMR0_CMIA0, TMR0_CMIB0, TMR0_OVI0),
|
||||
INTC_GROUP(TMR1, TMR1_CMIA1, TMR1_CMIB1, TMR1_OVI1),
|
||||
};
|
||||
|
||||
static struct intc_prio_reg prio_registers[] __initdata = {
|
||||
{ 0xfffe9418, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
|
||||
{ 0xfffe941a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
|
||||
{ 0xfffe9420, 0, 16, 4, /* IPR05 */ { PINT, 0, ADC_ADI, 0 } },
|
||||
{ 0xfffe9800, 0, 16, 4, /* IPR06 */ { 0, MTU20_ABCD, MTU20_VEF, MTU21_AB } },
|
||||
{ 0xfffe9802, 0, 16, 4, /* IPR07 */ { MTU21_VU, MTU22_AB, MTU22_VU, MTU23_ABCD } },
|
||||
{ 0xfffe9804, 0, 16, 4, /* IPR08 */ { MTU2_TCI3V, MTU24_ABCD, MTU2_TCI4V, MTU25_UVW } },
|
||||
|
||||
{ 0xfffe9806, 0, 16, 4, /* IPR09 */ { RTC, WDT, IIC30, 0 } },
|
||||
{ 0xfffe9808, 0, 16, 4, /* IPR10 */ { IIC31, IIC32, DMAC0_DMINT0, DMAC1_DMINT1 } },
|
||||
{ 0xfffe980a, 0, 16, 4, /* IPR11 */ { DMAC2_DMINT2, DMAC3_DMINT3, SCIF0 , SCIF1 } },
|
||||
{ 0xfffe980c, 0, 16, 4, /* IPR12 */ { SCIF2, SCIF3, SCIF4, SCIF5 } },
|
||||
{ 0xfffe980e, 0, 16, 4, /* IPR13 */ { SCIF6, SCIF7, DMAC0_DMINTA, DMAC4_DMINT4 } },
|
||||
{ 0xfffe9810, 0, 16, 4, /* IPR14 */ { DMAC5_DMINT5, DMAC6_DMINT6, DMAC7_DMINT7, 0 } },
|
||||
{ 0xfffe9812, 0, 16, 4, /* IPR15 */ { 0, RCAN0, RCAN1, 0 } },
|
||||
{ 0xfffe9814, 0, 16, 4, /* IPR16 */ { SSI0_SSII, SSI1_SSII, TMR0, TMR1 } },
|
||||
};
|
||||
|
||||
static struct intc_mask_reg mask_registers[] __initdata = {
|
||||
{ 0xfffe9408, 0, 16, /* PINTER */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
|
||||
};
|
||||
|
||||
static DECLARE_INTC_DESC(intc_desc, "sh7201", vectors, groups,
|
||||
mask_registers, prio_registers, NULL);
|
||||
|
||||
static struct plat_sci_port sci_platform_data[] = {
|
||||
{
|
||||
.mapbase = 0xfffe8000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 181, 182, 183, 180}
|
||||
}, {
|
||||
.mapbase = 0xfffe8800,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 185, 186, 187, 184}
|
||||
}, {
|
||||
.mapbase = 0xfffe9000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 189, 186, 187, 188}
|
||||
}, {
|
||||
.mapbase = 0xfffe9800,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 193, 194, 195, 192}
|
||||
}, {
|
||||
.mapbase = 0xfffea000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 196, 198, 199, 196}
|
||||
}, {
|
||||
.mapbase = 0xfffea800,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 201, 202, 203, 200}
|
||||
}, {
|
||||
.mapbase = 0xfffeb000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 205, 206, 207, 204}
|
||||
}, {
|
||||
.mapbase = 0xfffeb800,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 209, 210, 211, 208}
|
||||
}, {
|
||||
.flags = 0,
|
||||
}
|
||||
};
|
||||
|
||||
static struct platform_device sci_device = {
|
||||
.name = "sh-sci",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.platform_data = sci_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct resource rtc_resources[] = {
|
||||
[0] = {
|
||||
.start = 0xffff0800,
|
||||
.end = 0xffff2000 + 0x58 - 1,
|
||||
.flags = IORESOURCE_IO,
|
||||
},
|
||||
[1] = {
|
||||
/* Period IRQ */
|
||||
.start = 153,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[2] = {
|
||||
/* Carry IRQ */
|
||||
.start = 154,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[3] = {
|
||||
/* Alarm IRQ */
|
||||
.start = 152,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device rtc_device = {
|
||||
.name = "sh-rtc",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(rtc_resources),
|
||||
.resource = rtc_resources,
|
||||
};
|
||||
|
||||
static struct platform_device *sh7201_devices[] __initdata = {
|
||||
&sci_device,
|
||||
&rtc_device,
|
||||
};
|
||||
|
||||
static int __init sh7201_devices_setup(void)
|
||||
{
|
||||
return platform_add_devices(sh7201_devices,
|
||||
ARRAY_SIZE(sh7201_devices));
|
||||
}
|
||||
__initcall(sh7201_devices_setup);
|
||||
|
||||
void __init plat_irq_setup(void)
|
||||
{
|
||||
register_intc_controller(&intc_desc);
|
||||
}
|
||||
|
|
@ -417,6 +417,7 @@ void __init setup_arch(char **cmdline_p)
|
|||
}
|
||||
|
||||
static const char *cpu_name[] = {
|
||||
[CPU_SH7201] = "SH7201",
|
||||
[CPU_SH7203] = "SH7203", [CPU_SH7263] = "SH7263",
|
||||
[CPU_SH7206] = "SH7206", [CPU_SH7619] = "SH7619",
|
||||
[CPU_SH7705] = "SH7705", [CPU_SH7706] = "SH7706",
|
||||
|
|
|
|||
|
|
@ -34,7 +34,12 @@
|
|||
#define MTU2_TIER_1 0xfffe4384
|
||||
#define MTU2_TSR_1 0xfffe4385
|
||||
#define MTU2_TCNT_1 0xfffe4386 /* 16-bit counter */
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7201)
|
||||
#define MTU2_TGRA_1 0xfffe4388
|
||||
#else
|
||||
#define MTU2_TGRA_1 0xfffe438a
|
||||
#endif
|
||||
|
||||
#define STBCR3 0xfffe0408
|
||||
|
||||
|
|
|
|||
|
|
@ -133,13 +133,20 @@
|
|||
# define SCSPTR5 0xffef0024 /* 16 bit SCIF */
|
||||
# define SCIF_OPER 0x0001 /* Overrun error bit */
|
||||
# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7203) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7206) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7263)
|
||||
# define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
|
||||
# define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
|
||||
# define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
|
||||
# define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
|
||||
# if defined(CONFIG_CPU_SUBTYPE_SH7201)
|
||||
# define SCSPTR4 0xfffeA020 /* 16 bit SCIF */
|
||||
# define SCSPTR5 0xfffeA820 /* 16 bit SCIF */
|
||||
# define SCSPTR6 0xfffeB020 /* 16 bit SCIF */
|
||||
# define SCSPTR7 0xfffeB820 /* 16 bit SCIF */
|
||||
# endif
|
||||
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
|
||||
# define SCSPTR0 0xf8400020 /* 16 bit SCIF */
|
||||
|
|
@ -664,7 +671,8 @@ static inline int sci_rxd_in(struct uart_port *port)
|
|||
return ctrl_inw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
return 1;
|
||||
}
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7203) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7206) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7263)
|
||||
static inline int sci_rxd_in(struct uart_port *port)
|
||||
|
|
@ -677,6 +685,16 @@ static inline int sci_rxd_in(struct uart_port *port)
|
|||
return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
if (port->mapbase == 0xfffe9800)
|
||||
return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7201)
|
||||
if (port->mapbase == 0xfffeA000)
|
||||
return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
if (port->mapbase == 0xfffeA800)
|
||||
return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
if (port->mapbase == 0xfffeB000)
|
||||
return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
if (port->mapbase == 0xfffeB800)
|
||||
return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
#endif
|
||||
return 1;
|
||||
}
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
|
||||
|
|
|
|||
Loading…
Reference in New Issue