ARM: OMAP5: Add SMP support
Add OMAP5 SMP boot support using OMAP4 SMP code. The relevant code paths are runtime checked using cpu id Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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@ -276,6 +276,7 @@ extern void omap_secondary_startup(void);
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extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
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extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
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extern void omap_auxcoreboot_addr(u32 cpu_addr);
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extern void omap_auxcoreboot_addr(u32 cpu_addr);
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extern u32 omap_read_auxcoreboot0(void);
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extern u32 omap_read_auxcoreboot0(void);
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extern void omap5_secondary_startup(void);
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#endif
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#endif
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#if defined(CONFIG_SMP) && defined(CONFIG_PM)
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#if defined(CONFIG_SMP) && defined(CONFIG_PM)
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@ -19,6 +19,27 @@
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#include <linux/init.h>
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#include <linux/init.h>
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__CPUINIT
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__CPUINIT
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/* Physical address needed since MMU not enabled yet on secondary core */
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#define AUX_CORE_BOOT0_PA 0x48281800
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/*
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* OMAP5 specific entry point for secondary CPU to jump from ROM
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* code. This routine also provides a holding flag into which
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* secondary core is held until we're ready for it to initialise.
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* The primary core will update this flag using a hardware
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+ * register AuxCoreBoot0.
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*/
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ENTRY(omap5_secondary_startup)
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wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0
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ldr r0, [r2]
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mov r0, r0, lsr #5
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mrc p15, 0, r4, c0, c0, 5
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and r4, r4, #0x0f
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cmp r0, r4
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bne wait
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b secondary_startup
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END(omap5_secondary_startup)
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/*
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/*
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* OMAP4 specific entry point for secondary CPU to jump from ROM
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* OMAP4 specific entry point for secondary CPU to jump from ROM
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* code. This routine also provides a holding flag into which
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* code. This routine also provides a holding flag into which
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@ -33,6 +33,12 @@
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#include "common.h"
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#include "common.h"
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#include "clockdomain.h"
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#include "clockdomain.h"
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#define CPU_MASK 0xff0ffff0
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#define CPU_CORTEX_A9 0x410FC090
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#define CPU_CORTEX_A15 0x410FC0F0
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#define OMAP5_CORE_COUNT 0x2
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/* SCU base address */
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/* SCU base address */
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static void __iomem *scu_base;
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static void __iomem *scu_base;
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@ -133,7 +139,6 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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static void __init wakeup_secondary(void)
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static void __init wakeup_secondary(void)
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{
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{
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void __iomem *base = omap_get_wakeupgen_base();
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void __iomem *base = omap_get_wakeupgen_base();
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/*
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/*
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* Write the address of secondary startup routine into the
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* Write the address of secondary startup routine into the
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* AuxCoreBoot1 where ROM code will jump and start executing
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* AuxCoreBoot1 where ROM code will jump and start executing
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@ -162,16 +167,21 @@ static void __init wakeup_secondary(void)
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*/
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*/
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void __init smp_init_cpus(void)
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void __init smp_init_cpus(void)
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{
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{
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unsigned int i, ncores;
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unsigned int i = 0, ncores = 1, cpu_id;
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/*
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/* Use ARM cpuid check here, as SoC detection will not work so early */
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* Currently we can't call ioremap here because
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cpu_id = read_cpuid(CPUID_ID) & CPU_MASK;
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* SoC detection won't work until after init_early.
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if (cpu_id == CPU_CORTEX_A9) {
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*/
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/*
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scu_base = OMAP2_L4_IO_ADDRESS(OMAP44XX_SCU_BASE);
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* Currently we can't call ioremap here because
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BUG_ON(!scu_base);
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* SoC detection won't work until after init_early.
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*/
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ncores = scu_get_core_count(scu_base);
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scu_base = OMAP2_L4_IO_ADDRESS(OMAP44XX_SCU_BASE);
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BUG_ON(!scu_base);
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ncores = scu_get_core_count(scu_base);
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} else if (cpu_id == CPU_CORTEX_A15) {
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ncores = OMAP5_CORE_COUNT;
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}
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/* sanity check */
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/* sanity check */
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if (ncores > nr_cpu_ids) {
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if (ncores > nr_cpu_ids) {
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@ -193,6 +203,7 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
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* Initialise the SCU and wake up the secondary core using
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* Initialise the SCU and wake up the secondary core using
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* wakeup_secondary().
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* wakeup_secondary().
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*/
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*/
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scu_enable(scu_base);
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if (scu_base)
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scu_enable(scu_base);
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wakeup_secondary();
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wakeup_secondary();
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}
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}
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