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[ARM] 3995/1: iop13xx: add iop13xx support 

The iop348 processor integrates an Xscale (XSC3 512KB L2 Cache) core with a
Serial Attached SCSI (SAS) controller, multi-ported DDR2 memory
controller, 3 Application Direct Memory Access (DMA) controllers, a 133Mhz
PCI-X interface, a x8 PCI-Express interface, and other peripherals to form
a system-on-a-chip RAID subsystem engine.

The iop342 processor replaces the SAS controller with a second Xscale core
for dual core embedded applications.

The iop341 processor is the single core version of iop342.

This patch supports the two Intel customer reference platforms iq81340mc
for external storage and iq81340sc for direct attach (HBA) development.

The developer's manual is available here:
ftp://download.intel.com/design/iio/docs/31503701.pdf

Changelog:
* removed virtual addresses from resource definitions
* cleaned up some unnecessary #include's

Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Dan Williams 2006-12-07 02:59:39 +01:00 committed by Russell King
parent 4dbda6a50a
commit 285f5fa7e9
28 changed files with 3324 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
arch/arm/Kconfig
View File

@ -223,6 +223,12 @@ config ARCH_IOP33X
help
Support for Intel's IOP33X (XScale) family of processors.
config ARCH_IOP13XX
bool "IOP13xx-based"
select PCI
help
Support for Intel's IOP13XX (XScale) family of processors.
config ARCH_IXP4XX
bool "IXP4xx-based"
depends on MMU
@ -331,6 +337,8 @@ source "arch/arm/mach-iop32x/Kconfig"
source "arch/arm/mach-iop33x/Kconfig"
source "arch/arm/mach-iop13xx/Kconfig"
source "arch/arm/mach-ixp4xx/Kconfig"
source "arch/arm/mach-ixp2000/Kconfig"

1
arch/arm/Makefile
View File

@ -108,6 +108,7 @@ endif
machine-$(CONFIG_ARCH_CLPS711X) := clps711x
machine-$(CONFIG_ARCH_IOP32X) := iop32x
machine-$(CONFIG_ARCH_IOP33X) := iop33x
machine-$(CONFIG_ARCH_IOP13XX) := iop13xx
machine-$(CONFIG_ARCH_IXP4XX) := ixp4xx
machine-$(CONFIG_ARCH_IXP2000) := ixp2000
machine-$(CONFIG_ARCH_IXP23XX) := ixp23xx

20
arch/arm/mach-iop13xx/Kconfig Normal file
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@ -0,0 +1,20 @@
if ARCH_IOP13XX
menu "IOP13XX Implementation Options"
comment "IOP13XX Platform Support"
config MACH_IQ81340SC
bool "Enable IQ81340SC Hardware Support"
help
Say Y here if you want to support running on the Intel IQ81340SC
evaluation kit.
config MACH_IQ81340MC
bool "Enable IQ81340MC Hardware Support"
help
Say Y here if you want to support running on the Intel IQ81340MC
evaluation kit.
endmenu
endif

12
arch/arm/mach-iop13xx/Makefile Normal file
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@ -0,0 +1,12 @@
obj-y :=
obj-m :=
obj-n :=
obj- :=
obj-$(CONFIG_ARCH_IOP13XX) += setup.o
obj-$(CONFIG_ARCH_IOP13XX) += irq.o
obj-$(CONFIG_ARCH_IOP13XX) += time.o
obj-$(CONFIG_ARCH_IOP13XX) += pci.o
obj-$(CONFIG_ARCH_IOP13XX) += io.o
obj-$(CONFIG_MACH_IQ81340SC) += iq81340sc.o
obj-$(CONFIG_MACH_IQ81340MC) += iq81340mc.o

3
arch/arm/mach-iop13xx/Makefile.boot Normal file
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@ -0,0 +1,3 @@
zreladdr-y := 0x00008000
params_phys-y := 0x00000100
initrd_phys-y := 0x00800000

93
arch/arm/mach-iop13xx/io.c Normal file
View File

@ -0,0 +1,93 @@
/*
* iop13xx custom ioremap implementation
* Copyright (c) 2005-2006, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
* Place - Suite 330, Boston, MA 02111-1307 USA.
*
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <asm/hardware.h>
#include <asm/io.h>
void * __iomem __iop13xx_ioremap(unsigned long cookie, size_t size,
unsigned long flags)
{
void __iomem * retval;
switch (cookie) {
case IOP13XX_PCIX_LOWER_MEM_RA ... IOP13XX_PCIX_UPPER_MEM_RA:
if (unlikely(!iop13xx_atux_mem_base))
retval = NULL;
else
retval = (void *)(iop13xx_atux_mem_base +
(cookie - IOP13XX_PCIX_LOWER_MEM_RA));
break;
case IOP13XX_PCIE_LOWER_MEM_RA ... IOP13XX_PCIE_UPPER_MEM_RA:
if (unlikely(!iop13xx_atue_mem_base))
retval = NULL;
else
retval = (void *)(iop13xx_atue_mem_base +
(cookie - IOP13XX_PCIE_LOWER_MEM_RA));
break;
case IOP13XX_PBI_LOWER_MEM_RA ... IOP13XX_PBI_UPPER_MEM_RA:
retval = __ioremap(IOP13XX_PBI_LOWER_MEM_PA +
(cookie - IOP13XX_PBI_LOWER_MEM_RA),
size, flags);
break;
case IOP13XX_PCIE_LOWER_IO_PA ... IOP13XX_PCIE_UPPER_IO_PA:
retval = (void *) IOP13XX_PCIE_IO_PHYS_TO_VIRT(cookie);
break;
case IOP13XX_PCIX_LOWER_IO_PA ... IOP13XX_PCIX_UPPER_IO_PA:
retval = (void *) IOP13XX_PCIX_IO_PHYS_TO_VIRT(cookie);
break;
case IOP13XX_PMMR_PHYS_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_PA:
retval = (void *) IOP13XX_PMMR_PHYS_TO_VIRT(cookie);
break;
default:
retval = __ioremap(cookie, size, flags);
}
return retval;
}
EXPORT_SYMBOL(__iop13xx_ioremap);
void __iop13xx_iounmap(void __iomem *addr)
{
extern void __iounmap(volatile void __iomem *addr);
if (iop13xx_atue_mem_base)
if (addr >= (void __iomem *) iop13xx_atue_mem_base &&
addr < (void __iomem *) (iop13xx_atue_mem_base +
iop13xx_atue_mem_size))
goto skip;
if (iop13xx_atux_mem_base)
if (addr >= (void __iomem *) iop13xx_atux_mem_base &&
addr < (void __iomem *) (iop13xx_atux_mem_base +
iop13xx_atux_mem_size))
goto skip;
switch ((u32) addr) {
case IOP13XX_PCIE_LOWER_IO_VA ... IOP13XX_PCIE_UPPER_IO_VA:
case IOP13XX_PCIX_LOWER_IO_VA ... IOP13XX_PCIX_UPPER_IO_VA:
case IOP13XX_PMMR_VIRT_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_VA:
goto skip;
}
__iounmap(addr);
skip:
return;
}
EXPORT_SYMBOL(__iop13xx_iounmap);

98
arch/arm/mach-iop13xx/iq81340mc.c Normal file
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@ -0,0 +1,98 @@
/*
* iq81340mc board support
* Copyright (c) 2005-2006, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
* Place - Suite 330, Boston, MA 02111-1307 USA.
*
*/
#include <linux/pci.h>
#include <asm/hardware.h>
#include <asm/irq.h>
#include <asm/mach/pci.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/arch/pci.h>
#include <asm/mach/time.h>
extern int init_atu; /* Flag to select which ATU(s) to initialize / disable */
static int __init
iq81340mc_pcix_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
{
switch (idsel) {
case 1:
switch (pin) {
case 1: return ATUX_INTB;
case 2: return ATUX_INTC;
case 3: return ATUX_INTD;
case 4: return ATUX_INTA;
default: return -1;
}
case 2:
switch (pin) {
case 1: return ATUX_INTC;
case 2: return ATUX_INTD;
case 3: return ATUX_INTC;
case 4: return ATUX_INTD;
default: return -1;
}
default: return -1;
}
}
static struct hw_pci iq81340mc_pci __initdata = {
.swizzle = pci_std_swizzle,
.nr_controllers = 0,
.setup = iop13xx_pci_setup,
.map_irq = iq81340mc_pcix_map_irq,
.scan = iop13xx_scan_bus,
.preinit = iop13xx_pci_init,
};
static int __init iq81340mc_pci_init(void)
{
iop13xx_atu_select(&iq81340mc_pci);
pci_common_init(&iq81340mc_pci);
iop13xx_map_pci_memory();
return 0;
}
static void __init iq81340mc_init(void)
{
iop13xx_platform_init();
iq81340mc_pci_init();
}
static void __init iq81340mc_timer_init(void)
{
iop13xx_init_time(400000000);
}
static struct sys_timer iq81340mc_timer = {
.init = iq81340mc_timer_init,
.offset = iop13xx_gettimeoffset,
};
MACHINE_START(IQ81340MC, "Intel IQ81340MC")
/* Maintainer: Dan Williams <dan.j.williams@intel.com> */
.phys_io = PHYS_IO,
.io_pg_offst = IO_PG_OFFSET,
.map_io = iop13xx_map_io,
.init_irq = iop13xx_init_irq,
.timer = &iq81340mc_timer,
.boot_params = BOOT_PARAM_OFFSET,
.init_machine = iq81340mc_init,
MACHINE_END

100
arch/arm/mach-iop13xx/iq81340sc.c Normal file
View File

@ -0,0 +1,100 @@
/*
* iq81340sc board support
* Copyright (c) 2005-2006, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
* Place - Suite 330, Boston, MA 02111-1307 USA.
*
*/
#include <linux/pci.h>
#include <asm/hardware.h>
#include <asm/irq.h>
#include <asm/mach/pci.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/arch/pci.h>
#include <asm/mach/time.h>
extern int init_atu;
static int __init
iq81340sc_atux_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
{
WARN_ON(idsel < 1 || idsel > 2);
switch (idsel) {
case 1:
switch (pin) {
case 1: return ATUX_INTB;
case 2: return ATUX_INTC;
case 3: return ATUX_INTD;
case 4: return ATUX_INTA;
default: return -1;
}
case 2:
switch (pin) {
case 1: return ATUX_INTC;
case 2: return ATUX_INTC;
case 3: return ATUX_INTC;
case 4: return ATUX_INTC;
default: return -1;
}
default: return -1;
}
}
static struct hw_pci iq81340sc_pci __initdata = {
.swizzle = pci_std_swizzle,
.nr_controllers = 0,
.setup = iop13xx_pci_setup,
.scan = iop13xx_scan_bus,
.map_irq = iq81340sc_atux_map_irq,
.preinit = iop13xx_pci_init
};
static int __init iq81340sc_pci_init(void)
{
iop13xx_atu_select(&iq81340sc_pci);
pci_common_init(&iq81340sc_pci);
iop13xx_map_pci_memory();
return 0;
}
static void __init iq81340sc_init(void)
{
iop13xx_platform_init();
iq81340sc_pci_init();
}
static void __init iq81340sc_timer_init(void)
{
iop13xx_init_time(400000000);
}
static struct sys_timer iq81340sc_timer = {
.init = iq81340sc_timer_init,
.offset = iop13xx_gettimeoffset,
};
MACHINE_START(IQ81340SC, "Intel IQ81340SC")
/* Maintainer: Dan Williams <dan.j.williams@intel.com> */
.phys_io = PHYS_IO,
.io_pg_offst = IO_PG_OFFSET,
.map_io = iop13xx_map_io,
.init_irq = iop13xx_init_irq,
.timer = &iq81340sc_timer,
.boot_params = BOOT_PARAM_OFFSET,
.init_machine = iq81340sc_init,
MACHINE_END

286
arch/arm/mach-iop13xx/irq.c Normal file
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@ -0,0 +1,286 @@
/*
* iop13xx IRQ handling / support functions
* Copyright (c) 2005-2006, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
* Place - Suite 330, Boston, MA 02111-1307 USA.
*
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/sysctl.h>
#include <asm/uaccess.h>
#include <asm/mach/irq.h>
#include <asm/irq.h>
#include <asm/hardware.h>
#include <asm/mach-types.h>
#include <asm/arch/irqs.h>
/* INTCTL0 CP6 R0 Page 4
*/
static inline u32 read_intctl_0(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c0, c4, 0":"=r" (val));
return val;
}
static inline void write_intctl_0(u32 val)
{
asm volatile("mcr p6, 0, %0, c0, c4, 0"::"r" (val));
}
/* INTCTL1 CP6 R1 Page 4
*/
static inline u32 read_intctl_1(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c1, c4, 0":"=r" (val));
return val;
}
static inline void write_intctl_1(u32 val)
{
asm volatile("mcr p6, 0, %0, c1, c4, 0"::"r" (val));
}
/* INTCTL2 CP6 R2 Page 4
*/
static inline u32 read_intctl_2(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c2, c4, 0":"=r" (val));
return val;
}
static inline void write_intctl_2(u32 val)
{
asm volatile("mcr p6, 0, %0, c2, c4, 0"::"r" (val));
}
/* INTCTL3 CP6 R3 Page 4
*/
static inline u32 read_intctl_3(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c3, c4, 0":"=r" (val));
return val;
}
static inline void write_intctl_3(u32 val)
{
asm volatile("mcr p6, 0, %0, c3, c4, 0"::"r" (val));
}
/* INTSTR0 CP6 R0 Page 5
*/
static inline u32 read_intstr_0(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c0, c5, 0":"=r" (val));
return val;
}
static inline void write_intstr_0(u32 val)
{
asm volatile("mcr p6, 0, %0, c0, c5, 0"::"r" (val));
}
/* INTSTR1 CP6 R1 Page 5
*/
static inline u32 read_intstr_1(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c1, c5, 0":"=r" (val));
return val;
}
static void write_intstr_1(u32 val)
{
asm volatile("mcr p6, 0, %0, c1, c5, 0"::"r" (val));
}
/* INTSTR2 CP6 R2 Page 5
*/
static inline u32 read_intstr_2(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c2, c5, 0":"=r" (val));
return val;
}
static void write_intstr_2(u32 val)
{
asm volatile("mcr p6, 0, %0, c2, c5, 0"::"r" (val));
}
/* INTSTR3 CP6 R3 Page 5
*/
static inline u32 read_intstr_3(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c3, c5, 0":"=r" (val));
return val;
}
static void write_intstr_3(u32 val)
{
asm volatile("mcr p6, 0, %0, c3, c5, 0"::"r" (val));
}
/* INTBASE CP6 R0 Page 2
*/
static inline u32 read_intbase(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c0, c2, 0":"=r" (val));
return val;
}
static void write_intbase(u32 val)
{
asm volatile("mcr p6, 0, %0, c0, c2, 0"::"r" (val));
}
/* INTSIZE CP6 R2 Page 2
*/
static inline u32 read_intsize(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c2, c2, 0":"=r" (val));
return val;
}
static void write_intsize(u32 val)
{
asm volatile("mcr p6, 0, %0, c2, c2, 0"::"r" (val));
}
/* 0 = Interrupt Masked and 1 = Interrupt not masked */
static void
iop13xx_irq_mask0 (unsigned int irq)
{
u32 cp_flags = iop13xx_cp6_save();
write_intctl_0(read_intctl_0() & ~(1 << (irq - 0)));
iop13xx_cp6_restore(cp_flags);
}
static void
iop13xx_irq_mask1 (unsigned int irq)
{
u32 cp_flags = iop13xx_cp6_save();
write_intctl_1(read_intctl_1() & ~(1 << (irq - 32)));
iop13xx_cp6_restore(cp_flags);
}
static void
iop13xx_irq_mask2 (unsigned int irq)
{
u32 cp_flags = iop13xx_cp6_save();
write_intctl_2(read_intctl_2() & ~(1 << (irq - 64)));
iop13xx_cp6_restore(cp_flags);
}
static void
iop13xx_irq_mask3 (unsigned int irq)
{
u32 cp_flags = iop13xx_cp6_save();
write_intctl_3(read_intctl_3() & ~(1 << (irq - 96)));
iop13xx_cp6_restore(cp_flags);
}
static void
iop13xx_irq_unmask0(unsigned int irq)
{
u32 cp_flags = iop13xx_cp6_save();
write_intctl_0(read_intctl_0() | (1 << (irq - 0)));
iop13xx_cp6_restore(cp_flags);
}
static void
iop13xx_irq_unmask1(unsigned int irq)
{
u32 cp_flags = iop13xx_cp6_save();
write_intctl_1(read_intctl_1() | (1 << (irq - 32)));
iop13xx_cp6_restore(cp_flags);
}
static void
iop13xx_irq_unmask2(unsigned int irq)
{
u32 cp_flags = iop13xx_cp6_save();
write_intctl_2(read_intctl_2() | (1 << (irq - 64)));
iop13xx_cp6_restore(cp_flags);
}
static void
iop13xx_irq_unmask3(unsigned int irq)
{
u32 cp_flags = iop13xx_cp6_save();
write_intctl_3(read_intctl_3() | (1 << (irq - 96)));
iop13xx_cp6_restore(cp_flags);
}
static struct irqchip iop13xx_irqchip0 = {
.ack = iop13xx_irq_mask0,
.mask = iop13xx_irq_mask0,
.unmask = iop13xx_irq_unmask0,
};
static struct irqchip iop13xx_irqchip1 = {
.ack = iop13xx_irq_mask1,
.mask = iop13xx_irq_mask1,
.unmask = iop13xx_irq_unmask1,
};
static struct irqchip iop13xx_irqchip2 = {
.ack = iop13xx_irq_mask2,
.mask = iop13xx_irq_mask2,
.unmask = iop13xx_irq_unmask2,
};
static struct irqchip iop13xx_irqchip3 = {
.ack = iop13xx_irq_mask3,
.mask = iop13xx_irq_mask3,
.unmask = iop13xx_irq_unmask3,
};
void __init iop13xx_init_irq(void)
{
unsigned int i;
u32 cp_flags = iop13xx_cp6_save();
/* disable all interrupts */
write_intctl_0(0);
write_intctl_1(0);
write_intctl_2(0);
write_intctl_3(0);
/* treat all as IRQ */
write_intstr_0(0);
write_intstr_1(0);
write_intstr_2(0);
write_intstr_3(0);
/* initialize the interrupt vector generator */
write_intbase(INTBASE);
write_intsize(INTSIZE_4);
for(i = 0; i < NR_IOP13XX_IRQS; i++) {
if (i < 32)
set_irq_chip(i, &iop13xx_irqchip0);
else if (i < 64)
set_irq_chip(i, &iop13xx_irqchip1);
else if (i < 96)
set_irq_chip(i, &iop13xx_irqchip2);
else
set_irq_chip(i, &iop13xx_irqchip3);
set_irq_handler(i, do_level_IRQ);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
iop13xx_cp6_restore(cp_flags);
}

1113
arch/arm/mach-iop13xx/pci.c Normal file
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File diff suppressed because it is too large Load Diff

406
arch/arm/mach-iop13xx/setup.c Normal file
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@ -0,0 +1,406 @@
/*
* iop13xx platform Initialization
* Copyright (c) 2005-2006, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
* Place - Suite 330, Boston, MA 02111-1307 USA.
*
*/
#include <linux/serial_8250.h>
#ifdef CONFIG_MTD_PHYSMAP
#include <linux/mtd/physmap.h>
#endif
#include <asm/mach/map.h>
#include <asm/hardware.h>
#include <asm/irq.h>
#define IOP13XX_UART_XTAL 33334000
#define IOP13XX_SETUP_DEBUG 0
#define PRINTK(x...) ((void)(IOP13XX_SETUP_DEBUG && printk(x)))
/* Standard IO mapping for all IOP13XX based systems
*/
static struct map_desc iop13xx_std_desc[] __initdata = {
{ /* mem mapped registers */
.virtual = IOP13XX_PMMR_VIRT_MEM_BASE,
.pfn = __phys_to_pfn(IOP13XX_PMMR_PHYS_MEM_BASE),
.length = IOP13XX_PMMR_SIZE,
.type = MT_DEVICE,
}, { /* PCIE IO space */
.virtual = IOP13XX_PCIE_LOWER_IO_VA,
.pfn = __phys_to_pfn(IOP13XX_PCIE_LOWER_IO_PA),
.length = IOP13XX_PCIX_IO_WINDOW_SIZE,
.type = MT_DEVICE,
}, { /* PCIX IO space */
.virtual = IOP13XX_PCIX_LOWER_IO_VA,
.pfn = __phys_to_pfn(IOP13XX_PCIX_LOWER_IO_PA),
.length = IOP13XX_PCIX_IO_WINDOW_SIZE,
.type = MT_DEVICE,
},
};
static struct resource iop13xx_uart0_resources[] = {
[0] = {
.start = IOP13XX_UART0_PHYS,
.end = IOP13XX_UART0_PHYS + 0x3f,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_IOP13XX_UART0,
.end = IRQ_IOP13XX_UART0,
.flags = IORESOURCE_IRQ
}
};
static struct resource iop13xx_uart1_resources[] = {
[0] = {
.start = IOP13XX_UART1_PHYS,
.end = IOP13XX_UART1_PHYS + 0x3f,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_IOP13XX_UART1,
.end = IRQ_IOP13XX_UART1,
.flags = IORESOURCE_IRQ
}
};
static struct plat_serial8250_port iop13xx_uart0_data[] = {
{
.membase = (char*)(IOP13XX_UART0_VIRT),
.mapbase = (IOP13XX_UART0_PHYS),
.irq = IRQ_IOP13XX_UART0,
.uartclk = IOP13XX_UART_XTAL,
.regshift = 2,
.iotype = UPIO_MEM,
.flags = UPF_SKIP_TEST,
},
{ },
};
static struct plat_serial8250_port iop13xx_uart1_data[] = {
{
.membase = (char*)(IOP13XX_UART1_VIRT),
.mapbase = (IOP13XX_UART1_PHYS),
.irq = IRQ_IOP13XX_UART1,
.uartclk = IOP13XX_UART_XTAL,
.regshift = 2,
.iotype = UPIO_MEM,
.flags = UPF_SKIP_TEST,
},
{ },
};
/* The ids are fixed up later in iop13xx_platform_init */
static struct platform_device iop13xx_uart0 = {
.name = "serial8250",
.id = 0,
.dev.platform_data = iop13xx_uart0_data,
.num_resources = 2,
.resource = iop13xx_uart0_resources,
};
static struct platform_device iop13xx_uart1 = {
.name = "serial8250",
.id = 0,
.dev.platform_data = iop13xx_uart1_data,
.num_resources = 2,
.resource = iop13xx_uart1_resources
};
static struct resource iop13xx_i2c_0_resources[] = {
[0] = {
.start = IOP13XX_I2C0_PHYS,
.end = IOP13XX_I2C0_PHYS + 0x18,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_IOP13XX_I2C_0,
.end = IRQ_IOP13XX_I2C_0,
.flags = IORESOURCE_IRQ
}
};
static struct resource iop13xx_i2c_1_resources[] = {
[0] = {
.start = IOP13XX_I2C1_PHYS,
.end = IOP13XX_I2C1_PHYS + 0x18,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_IOP13XX_I2C_1,
.end = IRQ_IOP13XX_I2C_1,
.flags = IORESOURCE_IRQ
}
};
static struct resource iop13xx_i2c_2_resources[] = {
[0] = {
.start = IOP13XX_I2C2_PHYS,
.end = IOP13XX_I2C2_PHYS + 0x18,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_IOP13XX_I2C_2,
.end = IRQ_IOP13XX_I2C_2,
.flags = IORESOURCE_IRQ
}
};
/* I2C controllers. The IOP13XX uses the same block as the IOP3xx, so
* we just use the same device name.
*/
/* The ids are fixed up later in iop13xx_platform_init */
static struct platform_device iop13xx_i2c_0_controller = {
.name = "IOP3xx-I2C",
.id = 0,
.num_resources = 2,
.resource = iop13xx_i2c_0_resources
};
static struct platform_device iop13xx_i2c_1_controller = {
.name = "IOP3xx-I2C",
.id = 0,
.num_resources = 2,
.resource = iop13xx_i2c_1_resources
};
static struct platform_device iop13xx_i2c_2_controller = {
.name = "IOP3xx-I2C",
.id = 0,
.num_resources = 2,
.resource = iop13xx_i2c_2_resources
};
#ifdef CONFIG_MTD_PHYSMAP
/* PBI Flash Device
*/
static struct physmap_flash_data iq8134x_flash_data = {
.width = 2,
};
static struct resource iq8134x_flash_resource = {
.start = IQ81340_FLASHBASE,
.end = 0,
.flags = IORESOURCE_MEM,
};
static struct platform_device iq8134x_flash = {
.name = "physmap-flash",
.id = 0,
.dev = { .platform_data = &iq8134x_flash_data, },
.num_resources = 1,
.resource = &iq8134x_flash_resource,
};
static unsigned long iq8134x_probe_flash_size(void)
{
uint8_t __iomem *flash_addr = ioremap(IQ81340_FLASHBASE, PAGE_SIZE);
int i;
char query[3];
unsigned long size = 0;
int width = iq8134x_flash_data.width;
if (flash_addr) {
/* send CFI 'query' command */
writew(0x98, flash_addr);
/* check for CFI compliance */
for (i = 0; i < 3 * width; i += width)
query[i / width] = readb(flash_addr + (0x10 * width) + i);
/* read the size */
if (memcmp(query, "QRY", 3) == 0)
size = 1 << readb(flash_addr + (0x27 * width));
/* send CFI 'read array' command */
writew(0xff, flash_addr);
iounmap(flash_addr);
}
return size;
}
#endif
void __init iop13xx_map_io(void)
{
/* Initialize the Static Page Table maps */
iotable_init(iop13xx_std_desc, ARRAY_SIZE(iop13xx_std_desc));
}
static int init_uart = 0;
static int init_i2c = 0;
void __init iop13xx_platform_init(void)
{
int i;
u32 uart_idx, i2c_idx, plat_idx;
struct platform_device *iop13xx_devices[IQ81340_MAX_PLAT_DEVICES];
/* set the bases so we can read the device id */
iop13xx_set_atu_mmr_bases();
memset(iop13xx_devices, 0, sizeof(iop13xx_devices));
if (init_uart == IOP13XX_INIT_UART_DEFAULT) {
switch (iop13xx_dev_id()) {
/* enable both uarts on iop341 and iop342 */
case 0x3380:
case 0x3384:
case 0x3388:
case 0x338c:
case 0x3382:
case 0x3386:
case 0x338a:
case 0x338e:
init_uart |= IOP13XX_INIT_UART_0;
init_uart |= IOP13XX_INIT_UART_1;
break;
/* only enable uart 1 */
default:
init_uart |= IOP13XX_INIT_UART_1;
}
}
if (init_i2c == IOP13XX_INIT_I2C_DEFAULT) {
switch (iop13xx_dev_id()) {
/* enable all i2c units on iop341 and iop342 */
case 0x3380:
case 0x3384:
case 0x3388:
case 0x338c:
case 0x3382:
case 0x3386:
case 0x338a:
case 0x338e:
init_i2c |= IOP13XX_INIT_I2C_0;
init_i2c |= IOP13XX_INIT_I2C_1;
init_i2c |= IOP13XX_INIT_I2C_2;
break;
/* only enable i2c 1 and 2 */
default:
init_i2c |= IOP13XX_INIT_I2C_1;
init_i2c |= IOP13XX_INIT_I2C_2;
}
}
plat_idx = 0;
uart_idx = 0;
i2c_idx = 0;
/* uart 1 (if enabled) is ttyS0 */
if (init_uart & IOP13XX_INIT_UART_1) {
PRINTK("Adding uart1 to platform device list\n");
iop13xx_uart1.id = uart_idx++;
iop13xx_devices[plat_idx++] = &iop13xx_uart1;
}
if (init_uart & IOP13XX_INIT_UART_0) {
PRINTK("Adding uart0 to platform device list\n");
iop13xx_uart0.id = uart_idx++;
iop13xx_devices[plat_idx++] = &iop13xx_uart0;
}
for(i = 0; i < IQ81340_NUM_I2C; i++) {
if ((init_i2c & (1 << i)) && IOP13XX_SETUP_DEBUG)
printk("Adding i2c%d to platform device list\n", i);
switch(init_i2c & (1 << i)) {
case IOP13XX_INIT_I2C_0:
iop13xx_i2c_0_controller.id = i2c_idx++;
iop13xx_devices[plat_idx++] =
&iop13xx_i2c_0_controller;
break;
case IOP13XX_INIT_I2C_1:
iop13xx_i2c_1_controller.id = i2c_idx++;
iop13xx_devices[plat_idx++] =
&iop13xx_i2c_1_controller;
break;
case IOP13XX_INIT_I2C_2:
iop13xx_i2c_2_controller.id = i2c_idx++;
iop13xx_devices[plat_idx++] =
&iop13xx_i2c_2_controller;
break;
}
}
#ifdef CONFIG_MTD_PHYSMAP
iq8134x_flash_resource.end = iq8134x_flash_resource.start +
iq8134x_probe_flash_size();
if (iq8134x_flash_resource.end > iq8134x_flash_resource.start)
iop13xx_devices[plat_idx++] = &iq8134x_flash;
else
printk(KERN_ERR "%s: Failed to probe flash size\n", __FUNCTION__);
#endif
platform_add_devices(iop13xx_devices, plat_idx);
}
static int __init iop13xx_init_uart_setup(char *str)
{
if (str) {
while (*str != '\0') {
switch(*str) {
case '0':
init_uart |= IOP13XX_INIT_UART_0;
break;
case '1':
init_uart |= IOP13XX_INIT_UART_1;
break;
case ',':
case '=':
break;
default:
PRINTK("\"iop13xx_init_uart\" malformed"
" at character: \'%c\'", *str);
*(str + 1) = '\0';
init_uart = IOP13XX_INIT_UART_DEFAULT;
}
str++;
}
}
return 1;
}
static int __init iop13xx_init_i2c_setup(char *str)
{
if (str) {
while (*str != '\0') {
switch(*str) {
case '0':
init_i2c |= IOP13XX_INIT_I2C_0;
break;
case '1':
init_i2c |= IOP13XX_INIT_I2C_1;
break;
case '2':
init_i2c |= IOP13XX_INIT_I2C_2;
break;
case ',':
case '=':
break;
default:
PRINTK("\"iop13xx_init_i2c\" malformed"
" at character: \'%c\'", *str);
*(str + 1) = '\0';
init_i2c = IOP13XX_INIT_I2C_DEFAULT;
}
str++;
}
}
return 1;
}
__setup("iop13xx_init_uart", iop13xx_init_uart_setup);
__setup("iop13xx_init_i2c", iop13xx_init_i2c_setup);

102
arch/arm/mach-iop13xx/time.c Normal file
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@ -0,0 +1,102 @@
/*
* arch/arm/mach-iop13xx/time.c
*
* Timer code for IOP13xx (copied from IOP32x/IOP33x implementation)
*
* Author: Deepak Saxena <dsaxena@mvista.com>
*
* Copyright 2002-2003 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/time.h>
#include <linux/init.h>
#include <linux/timex.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/uaccess.h>
#include <asm/mach/irq.h>
#include <asm/mach/time.h>
static unsigned long ticks_per_jiffy;
static unsigned long ticks_per_usec;
static unsigned long next_jiffy_time;
static inline u32 read_tcr1(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c3, c9, 0" : "=r" (val));
return val;
}
unsigned long iop13xx_gettimeoffset(void)
{
unsigned long offset;
u32 cp_flags;
cp_flags = iop13xx_cp6_save();
offset = next_jiffy_time - read_tcr1();
iop13xx_cp6_restore(cp_flags);
return offset / ticks_per_usec;
}
static irqreturn_t
iop13xx_timer_interrupt(int irq, void *dev_id)
{
u32 cp_flags = iop13xx_cp6_save();
write_seqlock(&xtime_lock);
asm volatile("mcr p6, 0, %0, c6, c9, 0" : : "r" (1));
while ((signed long)(next_jiffy_time - read_tcr1())
>= ticks_per_jiffy) {
timer_tick();
next_jiffy_time -= ticks_per_jiffy;
}
write_sequnlock(&xtime_lock);
iop13xx_cp6_restore(cp_flags);
return IRQ_HANDLED;
}
static struct irqaction iop13xx_timer_irq = {
.name = "IOP13XX Timer Tick",
.handler = iop13xx_timer_interrupt,
.flags = IRQF_DISABLED | IRQF_TIMER,
};
void __init iop13xx_init_time(unsigned long tick_rate)
{
u32 timer_ctl;
u32 cp_flags;
ticks_per_jiffy = (tick_rate + HZ/2) / HZ;
ticks_per_usec = tick_rate / 1000000;
next_jiffy_time = 0xffffffff;
timer_ctl = IOP13XX_TMR_EN | IOP13XX_TMR_PRIVILEGED |
IOP13XX_TMR_RELOAD | IOP13XX_TMR_RATIO_1_1;
/*
* We use timer 0 for our timer interrupt, and timer 1 as
* monotonic counter for tracking missed jiffies.
*/
cp_flags = iop13xx_cp6_save();
asm volatile("mcr p6, 0, %0, c4, c9, 0" : : "r" (ticks_per_jiffy - 1));
asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (timer_ctl));
asm volatile("mcr p6, 0, %0, c5, c9, 0" : : "r" (0xffffffff));
asm volatile("mcr p6, 0, %0, c1, c9, 0" : : "r" (timer_ctl));
iop13xx_cp6_restore(cp_flags);
setup_irq(IRQ_IOP13XX_TIMER0, &iop13xx_timer_irq);
}

2
arch/arm/mm/Kconfig
View File

@ -333,7 +333,7 @@ config CPU_XSCALE
# XScale Core Version 3
config CPU_XSC3
bool
depends on ARCH_IXP23XX
depends on ARCH_IXP23XX || ARCH_IOP13XX
default y
select CPU_32v5
select CPU_ABRT_EV5T

6
drivers/i2c/busses/Kconfig
View File

@ -195,11 +195,11 @@ config I2C_IBM_IIC
will be called i2c-ibm_iic.
config I2C_IOP3XX
tristate "Intel IOP3xx and IXP4xx on-chip I2C interface"
depends on (ARCH_IOP32X || ARCH_IOP33X || ARCH_IXP4XX) && I2C
tristate "Intel IOPx3xx and IXP4xx on-chip I2C interface"
depends on (ARCH_IOP32X || ARCH_IOP33X || ARCH_IXP4XX || ARCH_IOP13XX) && I2C
help
Say Y here if you want to use the IIC bus controller on
the Intel IOP3xx I/O Processors or IXP4xx Network Processors.
the Intel IOPx3xx I/O Processors or IXP4xx Network Processors.
This driver can also be built as a module. If so, the module
will be called i2c-iop3xx.

26
include/asm-arm/arch-iop13xx/debug-macro.S Normal file
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@ -0,0 +1,26 @@
/*
* include/asm-arm/arch-iop13xx/debug-macro.S
*
* Debugging macro include header
*
* Copyright (C) 1994-1999 Russell King
* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
.macro addruart, rx
mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ mmu enabled?
moveq \rx, #0xff000000 @ physical
orreq \rx, \rx, #0x00d80000
movne \rx, #0xfe000000 @ virtual
orrne \rx, \rx, #0x00e80000
orr \rx, \rx, #0x00002300
orr \rx, \rx, #0x00000040
.endm
#define UART_SHIFT 2
#include <asm/hardware/debug-8250.S>

3
include/asm-arm/arch-iop13xx/dma.h Normal file
View File

@ -0,0 +1,3 @@
#ifndef _IOP13XX_DMA_H
#define _IOP13XX_DMA_H_
#endif

39
include/asm-arm/arch-iop13xx/entry-macro.S Normal file
View File

@ -0,0 +1,39 @@
/*
* iop13xx low level irq macros
* Copyright (c) 2005-2006, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
* Place - Suite 330, Boston, MA 02111-1307 USA.
*
*/
.macro disable_fiq
.endm
/*
* Note: a 1-cycle window exists where iintvec will return the value
* of iintbase, so we explicitly check for "bad zeros"
*/
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mrc p15, 0, \tmp, c15, c1, 0
orr \tmp, \tmp, #(1 << 6)
mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access
mrc p6, 0, \irqnr, c3, c2, 0 @ Read IINTVEC
cmp \irqnr, #0
mrceq p6, 0, \irqnr, c3, c2, 0 @ Re-read on potentially bad zero
adds \irqstat, \irqnr, #1 @ Check for 0xffffffff
movne \irqnr, \irqnr, lsr #2 @ Convert to irqnr
biceq \tmp, \tmp, #(1 << 6)
mcreq p15, 0, \tmp, c15, c1, 0 @ Disable cp6 access if no more interrupts
.endm

28
include/asm-arm/arch-iop13xx/hardware.h Normal file
View File

@ -0,0 +1,28 @@
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
#include <asm/types.h>
#define pcibios_assign_all_busses() 1
#ifndef __ASSEMBLY__
extern unsigned long iop13xx_pcibios_min_io;
extern unsigned long iop13xx_pcibios_min_mem;
extern u16 iop13xx_dev_id(void);
extern void iop13xx_set_atu_mmr_bases(void);
#endif
#define PCIBIOS_MIN_IO (iop13xx_pcibios_min_io)
#define PCIBIOS_MIN_MEM (iop13xx_pcibios_min_mem)
/*
* Generic chipset bits
*
*/
#include "iop13xx.h"
/*
* Board specific bits
*/
#include "iq81340.h"
#endif /* _ASM_ARCH_HARDWARE_H */

41
include/asm-arm/arch-iop13xx/io.h Normal file
View File

@ -0,0 +1,41 @@
/*
* iop13xx custom ioremap implementation
* Copyright (c) 2005-2006, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
* Place - Suite 330, Boston, MA 02111-1307 USA.
*
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#define IO_SPACE_LIMIT 0xffffffff
#define __io(a) (a)
#define __mem_pci(a) (a)
#define __mem_isa(a) (a)
extern void __iomem * __ioremap(unsigned long, size_t, unsigned long);
extern void __iomem *__iop13xx_ioremap(unsigned long cookie, size_t size,
unsigned long flags);
extern void __iop13xx_iounmap(void __iomem *addr);
extern u32 iop13xx_atue_mem_base;
extern u32 iop13xx_atux_mem_base;
extern size_t iop13xx_atue_mem_size;
extern size_t iop13xx_atux_mem_size;
#define __arch_ioremap(a, s, f) __iop13xx_ioremap(a, s, f)
#define __arch_iounmap(a) __iop13xx_iounmap(a)
#endif

492
include/asm-arm/arch-iop13xx/iop13xx.h Normal file
View File

@ -0,0 +1,492 @@
#ifndef _IOP13XX_HW_H_
#define _IOP13XX_HW_H_
#ifndef __ASSEMBLY__
/* The ATU offsets can change based on the strapping */
extern u32 iop13xx_atux_pmmr_offset;
extern u32 iop13xx_atue_pmmr_offset;
void iop13xx_init_irq(void);
void iop13xx_map_io(void);
void iop13xx_platform_init(void);
void iop13xx_init_irq(void);
void iop13xx_init_time(unsigned long tickrate);
unsigned long iop13xx_gettimeoffset(void);
/* handle cp6 access
* to do: handle access in entry-armv5.S and unify with
* the iop3xx implementation
* note: use iop13xx_cp6_enable_irq_save and iop13xx_cp6_irq_restore (irq.h)
* when interrupts are enabled
*/
static inline unsigned long iop13xx_cp6_save(void)
{
u32 temp, cp_flags;
asm volatile (
"mrc p15, 0, %1, c15, c1, 0\n\t"
"orr %0, %1, #(1 << 6)\n\t"
"mcr p15, 0, %0, c15, c1, 0\n\t"
: "=r" (temp), "=r"(cp_flags));
return cp_flags;
}
static inline void iop13xx_cp6_restore(unsigned long cp_flags)
{
asm volatile (
"mcr p15, 0, %0, c15, c1, 0\n\t"
: : "r" (cp_flags) );
}
/* CPUID CP6 R0 Page 0 */
static inline int iop13xx_cpu_id(void)
{
int id;
asm volatile("mrc p6, 0, %0, c0, c0, 0":"=r" (id));
return id;
}
#endif
/*
* IOP13XX I/O and Mem space regions for PCI autoconfiguration
*/
#define IOP13XX_MAX_RAM_SIZE 0x80000000UL /* 2GB */
#define IOP13XX_PCI_OFFSET IOP13XX_MAX_RAM_SIZE
/* PCI MAP
* 0x0000.0000 - 0x8000.0000 1:1 mapping with Physical RAM
* 0x8000.0000 - 0x8800.0000 PCIX/PCIE memory window (128MB)
*/
#define IOP13XX_PCIX_IO_WINDOW_SIZE 0x10000UL
#define IOP13XX_PCIX_LOWER_IO_PA 0xfffb0000UL
#define IOP13XX_PCIX_LOWER_IO_VA 0xfec60000UL
#define IOP13XX_PCIX_LOWER_IO_BA 0x0fff0000UL
#define IOP13XX_PCIX_UPPER_IO_PA (IOP13XX_PCIX_LOWER_IO_PA +\
IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
#define IOP13XX_PCIX_UPPER_IO_VA (IOP13XX_PCIX_LOWER_IO_VA +\
IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
#define IOP13XX_PCIX_IO_OFFSET (IOP13XX_PCIX_LOWER_IO_VA -\
IOP13XX_PCIX_LOWER_IO_BA)
#define IOP13XX_PCIX_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
(IOP13XX_PCIX_LOWER_IO_PA\
- IOP13XX_PCIX_LOWER_IO_VA))
#define IOP13XX_PCIX_MEM_PHYS_OFFSET 0x100000000ULL
#define IOP13XX_PCIX_MEM_WINDOW_SIZE 0x3a000000UL
#define IOP13XX_PCIX_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET)
#define IOP13XX_PCIX_LOWER_MEM_PA (IOP13XX_PCIX_MEM_PHYS_OFFSET +\
IOP13XX_PCIX_LOWER_MEM_BA)
#define IOP13XX_PCIX_UPPER_MEM_PA (IOP13XX_PCIX_LOWER_MEM_PA +\
IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
#define IOP13XX_PCIX_UPPER_MEM_BA (IOP13XX_PCIX_LOWER_MEM_BA +\
IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
#define IOP13XX_PCIX_MEM_COOKIE 0x80000000UL
#define IOP13XX_PCIX_LOWER_MEM_RA IOP13XX_PCIX_MEM_COOKIE
#define IOP13XX_PCIX_UPPER_MEM_RA (IOP13XX_PCIX_LOWER_MEM_RA +\
IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
#define IOP13XX_PCIX_MEM_OFFSET (IOP13XX_PCIX_MEM_COOKIE -\
IOP13XX_PCIX_LOWER_MEM_BA)
/* PCI-E ranges */
#define IOP13XX_PCIE_IO_WINDOW_SIZE 0x10000UL
#define IOP13XX_PCIE_LOWER_IO_PA 0xfffd0000UL
#define IOP13XX_PCIE_LOWER_IO_VA 0xfed70000UL
#define IOP13XX_PCIE_LOWER_IO_BA 0x0fff0000UL
#define IOP13XX_PCIE_UPPER_IO_PA (IOP13XX_PCIE_LOWER_IO_PA +\
IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
#define IOP13XX_PCIE_UPPER_IO_VA (IOP13XX_PCIE_LOWER_IO_VA +\
IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
#define IOP13XX_PCIE_UPPER_IO_BA (IOP13XX_PCIE_LOWER_IO_BA +\
IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
#define IOP13XX_PCIE_IO_OFFSET (IOP13XX_PCIE_LOWER_IO_VA -\
IOP13XX_PCIE_LOWER_IO_BA)
#define IOP13XX_PCIE_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
(IOP13XX_PCIE_LOWER_IO_PA\
- IOP13XX_PCIE_LOWER_IO_VA))
#define IOP13XX_PCIE_MEM_PHYS_OFFSET 0x200000000ULL
#define IOP13XX_PCIE_MEM_WINDOW_SIZE 0x3a000000UL
#define IOP13XX_PCIE_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET)
#define IOP13XX_PCIE_LOWER_MEM_PA (IOP13XX_PCIE_MEM_PHYS_OFFSET +\
IOP13XX_PCIE_LOWER_MEM_BA)
#define IOP13XX_PCIE_UPPER_MEM_PA (IOP13XX_PCIE_LOWER_MEM_PA +\
IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
#define IOP13XX_PCIE_UPPER_MEM_BA (IOP13XX_PCIE_LOWER_MEM_BA +\
IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
/* All 0xc000.0000 - 0xfdff.ffff addresses belong to PCIe */
#define IOP13XX_PCIE_MEM_COOKIE 0xc0000000UL
#define IOP13XX_PCIE_LOWER_MEM_RA IOP13XX_PCIE_MEM_COOKIE
#define IOP13XX_PCIE_UPPER_MEM_RA (IOP13XX_PCIE_LOWER_MEM_RA +\
IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
#define IOP13XX_PCIE_MEM_OFFSET (IOP13XX_PCIE_MEM_COOKIE -\
IOP13XX_PCIE_LOWER_MEM_BA)
/* PBI Ranges */
#define IOP13XX_PBI_LOWER_MEM_PA 0xf0000000UL
#define IOP13XX_PBI_MEM_WINDOW_SIZE 0x04000000UL
#define IOP13XX_PBI_MEM_COOKIE 0xfa000000UL
#define IOP13XX_PBI_LOWER_MEM_RA IOP13XX_PBI_MEM_COOKIE
#define IOP13XX_PBI_UPPER_MEM_RA (IOP13XX_PBI_LOWER_MEM_RA +\
IOP13XX_PBI_MEM_WINDOW_SIZE - 1)
/*
* IOP13XX chipset registers
*/
#define IOP13XX_PMMR_PHYS_MEM_BASE 0xffd80000UL /* PMMR phys. address */
#define IOP13XX_PMMR_VIRT_MEM_BASE 0xfee80000UL /* PMMR phys. address */
#define IOP13XX_PMMR_MEM_WINDOW_SIZE 0x80000
#define IOP13XX_PMMR_UPPER_MEM_VA (IOP13XX_PMMR_VIRT_MEM_BASE +\
IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
#define IOP13XX_PMMR_UPPER_MEM_PA (IOP13XX_PMMR_PHYS_MEM_BASE +\
IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
#define IOP13XX_PMMR_VIRT_TO_PHYS(addr) (u32) ((u32) addr +\
(IOP13XX_PMMR_PHYS_MEM_BASE\
- IOP13XX_PMMR_VIRT_MEM_BASE))
#define IOP13XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
(IOP13XX_PMMR_PHYS_MEM_BASE\
- IOP13XX_PMMR_VIRT_MEM_BASE))
#define IOP13XX_REG_ADDR32(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
#define IOP13XX_REG_ADDR16(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
#define IOP13XX_REG_ADDR8(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
#define IOP13XX_REG_ADDR32_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
#define IOP13XX_REG_ADDR16_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
#define IOP13XX_REG_ADDR8_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
#define IOP13XX_PMMR_SIZE 0x00080000
/*=================== Defines for Platform Devices =====================*/
#define IOP13XX_UART0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002300)
#define IOP13XX_UART1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002340)
#define IOP13XX_UART0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002300)
#define IOP13XX_UART1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002340)
#define IOP13XX_I2C0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002500)
#define IOP13XX_I2C1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002520)
#define IOP13XX_I2C2_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002540)
#define IOP13XX_I2C0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002500)
#define IOP13XX_I2C1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002520)
#define IOP13XX_I2C2_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002540)
/* ATU selection flags */
/* IOP13XX_INIT_ATU_DEFAULT = Rely on CONFIG_IOP13XX_ATU* */
#define IOP13XX_INIT_ATU_DEFAULT (0)
#define IOP13XX_INIT_ATU_ATUX (1 << 0)
#define IOP13XX_INIT_ATU_ATUE (1 << 1)
#define IOP13XX_INIT_ATU_NONE (1 << 2)
/* UART selection flags */
/* IOP13XX_INIT_UART_DEFAULT = Rely on CONFIG_IOP13XX_UART* */
#define IOP13XX_INIT_UART_DEFAULT (0)
#define IOP13XX_INIT_UART_0 (1 << 0)
#define IOP13XX_INIT_UART_1 (1 << 1)
/* I2C selection flags */
/* IOP13XX_INIT_I2C_DEFAULT = Rely on CONFIG_IOP13XX_I2C* */
#define IOP13XX_INIT_I2C_DEFAULT (0)
#define IOP13XX_INIT_I2C_0 (1 << 0)
#define IOP13XX_INIT_I2C_1 (1 << 1)
#define IOP13XX_INIT_I2C_2 (1 << 2)
#define IQ81340_NUM_UART 2
#define IQ81340_NUM_I2C 3
#define IQ81340_NUM_PHYS_MAP_FLASH 1
#define IQ81340_MAX_PLAT_DEVICES (IQ81340_NUM_UART +\
IQ81340_NUM_I2C +\
IQ81340_NUM_PHYS_MAP_FLASH)
/*========================== PMMR offsets for key registers ============*/
#define IOP13XX_ATU0_PMMR_OFFSET 0x00048000
#define IOP13XX_ATU1_PMMR_OFFSET 0x0004c000
#define IOP13XX_ATU2_PMMR_OFFSET 0x0004d000
#define IOP13XX_ADMA0_PMMR_OFFSET 0x00000000
#define IOP13XX_ADMA1_PMMR_OFFSET 0x00000200
#define IOP13XX_ADMA2_PMMR_OFFSET 0x00000400
#define IOP13XX_PBI_PMMR_OFFSET 0x00001580
#define IOP13XX_ESSR0_PMMR_OFFSET 0x00002188
#define IOP13XX_ESSR0 IOP13XX_REG_ADDR32(0x00002188)
#define IOP13XX_ESSR0_IFACE_MASK 0x00004000 /* Interface PCI-X / PCI-E */
#define IOP13XX_CONTROLLER_ONLY (1 << 14)
#define IOP13XX_INTERFACE_SEL_PCIX (1 << 15)
#define IOP13XX_PMON_PMMR_OFFSET 0x0001A000
#define IOP13XX_PMON_BASE (IOP13XX_PMMR_VIRT_MEM_BASE +\
IOP13XX_PMON_PMMR_OFFSET)
#define IOP13XX_PMON_PHYSBASE (IOP13XX_PMMR_PHYS_MEM_BASE +\
IOP13XX_PMON_PMMR_OFFSET)
#define IOP13XX_PMON_CMD0 (IOP13XX_PMON_BASE + 0x0)
#define IOP13XX_PMON_EVR0 (IOP13XX_PMON_BASE + 0x4)
#define IOP13XX_PMON_STS0 (IOP13XX_PMON_BASE + 0x8)
#define IOP13XX_PMON_DATA0 (IOP13XX_PMON_BASE + 0xC)
#define IOP13XX_PMON_CMD3 (IOP13XX_PMON_BASE + 0x30)
#define IOP13XX_PMON_EVR3 (IOP13XX_PMON_BASE + 0x34)
#define IOP13XX_PMON_STS3 (IOP13XX_PMON_BASE + 0x38)
#define IOP13XX_PMON_DATA3 (IOP13XX_PMON_BASE + 0x3C)
#define IOP13XX_PMON_CMD7 (IOP13XX_PMON_BASE + 0x70)
#define IOP13XX_PMON_EVR7 (IOP13XX_PMON_BASE + 0x74)
#define IOP13XX_PMON_STS7 (IOP13XX_PMON_BASE + 0x78)
#define IOP13XX_PMON_DATA7 (IOP13XX_PMON_BASE + 0x7C)
#define IOP13XX_PMONEN (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E040)
#define IOP13XX_PMONSTAT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E044)
/*================================ATU===================================*/
#define IOP13XX_ATUX_OFFSET(ofs) IOP13XX_REG_ADDR32(\
iop13xx_atux_pmmr_offset + (ofs))
#define IOP13XX_ATUX_DID IOP13XX_REG_ADDR16(\
iop13xx_atux_pmmr_offset + 0x2)
#define IOP13XX_ATUX_ATUCMD IOP13XX_REG_ADDR16(\
iop13xx_atux_pmmr_offset + 0x4)
#define IOP13XX_ATUX_ATUSR IOP13XX_REG_ADDR16(\
iop13xx_atux_pmmr_offset + 0x6)
#define IOP13XX_ATUX_IABAR0 IOP13XX_ATUX_OFFSET(0x10)
#define IOP13XX_ATUX_IAUBAR0 IOP13XX_ATUX_OFFSET(0x14)
#define IOP13XX_ATUX_IABAR1 IOP13XX_ATUX_OFFSET(0x18)
#define IOP13XX_ATUX_IAUBAR1 IOP13XX_ATUX_OFFSET(0x1c)
#define IOP13XX_ATUX_IABAR2 IOP13XX_ATUX_OFFSET(0x20)
#define IOP13XX_ATUX_IAUBAR2 IOP13XX_ATUX_OFFSET(0x24)
#define IOP13XX_ATUX_IALR0 IOP13XX_ATUX_OFFSET(0x40)
#define IOP13XX_ATUX_IATVR0 IOP13XX_ATUX_OFFSET(0x44)
#define IOP13XX_ATUX_IAUTVR0 IOP13XX_ATUX_OFFSET(0x48)
#define IOP13XX_ATUX_IALR1 IOP13XX_ATUX_OFFSET(0x4c)
#define IOP13XX_ATUX_IATVR1 IOP13XX_ATUX_OFFSET(0x50)
#define IOP13XX_ATUX_IAUTVR1 IOP13XX_ATUX_OFFSET(0x54)
#define IOP13XX_ATUX_IALR2 IOP13XX_ATUX_OFFSET(0x58)
#define IOP13XX_ATUX_IATVR2 IOP13XX_ATUX_OFFSET(0x5c)
#define IOP13XX_ATUX_IAUTVR2 IOP13XX_ATUX_OFFSET(0x60)
#define IOP13XX_ATUX_ATUCR IOP13XX_ATUX_OFFSET(0x70)
#define IOP13XX_ATUX_PCSR IOP13XX_ATUX_OFFSET(0x74)
#define IOP13XX_ATUX_ATUISR IOP13XX_ATUX_OFFSET(0x78)
#define IOP13XX_ATUX_PCIXSR IOP13XX_ATUX_OFFSET(0xD4)
#define IOP13XX_ATUX_IABAR3 IOP13XX_ATUX_OFFSET(0x200)
#define IOP13XX_ATUX_IAUBAR3 IOP13XX_ATUX_OFFSET(0x204)
#define IOP13XX_ATUX_IALR3 IOP13XX_ATUX_OFFSET(0x208)
#define IOP13XX_ATUX_IATVR3 IOP13XX_ATUX_OFFSET(0x20c)
#define IOP13XX_ATUX_IAUTVR3 IOP13XX_ATUX_OFFSET(0x210)
#define IOP13XX_ATUX_OIOBAR IOP13XX_ATUX_OFFSET(0x300)
#define IOP13XX_ATUX_OIOWTVR IOP13XX_ATUX_OFFSET(0x304)
#define IOP13XX_ATUX_OUMBAR0 IOP13XX_ATUX_OFFSET(0x308)
#define IOP13XX_ATUX_OUMWTVR0 IOP13XX_ATUX_OFFSET(0x30c)
#define IOP13XX_ATUX_OUMBAR1 IOP13XX_ATUX_OFFSET(0x310)
#define IOP13XX_ATUX_OUMWTVR1 IOP13XX_ATUX_OFFSET(0x314)
#define IOP13XX_ATUX_OUMBAR2 IOP13XX_ATUX_OFFSET(0x318)
#define IOP13XX_ATUX_OUMWTVR2 IOP13XX_ATUX_OFFSET(0x31c)
#define IOP13XX_ATUX_OUMBAR3 IOP13XX_ATUX_OFFSET(0x320)
#define IOP13XX_ATUX_OUMWTVR3 IOP13XX_ATUX_OFFSET(0x324)
#define IOP13XX_ATUX_OUDMABAR IOP13XX_ATUX_OFFSET(0x328)
#define IOP13XX_ATUX_OUMSIBAR IOP13XX_ATUX_OFFSET(0x32c)
#define IOP13XX_ATUX_OCCAR IOP13XX_ATUX_OFFSET(0x330)
#define IOP13XX_ATUX_OCCDR IOP13XX_ATUX_OFFSET(0x334)
#define IOP13XX_ATUX_ATUCR_OUT_EN (1 << 1)
#define IOP13XX_ATUX_PCSR_CENTRAL_RES (1 << 25)
#define IOP13XX_ATUX_PCSR_P_RSTOUT (1 << 21)
#define IOP13XX_ATUX_PCSR_OUT_Q_BUSY (1 << 15)
#define IOP13XX_ATUX_PCSR_IN_Q_BUSY (1 << 14)
#define IOP13XX_ATUX_PCSR_FREQ_OFFSET (16)
#define IOP13XX_ATUX_STAT_PCI_IFACE_ERR (1 << 18)
#define IOP13XX_ATUX_STAT_VPD_ADDR (1 << 17)
#define IOP13XX_ATUX_STAT_INT_PAR_ERR (1 << 16)
#define IOP13XX_ATUX_STAT_CFG_WRITE (1 << 15)
#define IOP13XX_ATUX_STAT_ERR_COR (1 << 14)
#define IOP13XX_ATUX_STAT_TX_SCEM (1 << 13)
#define IOP13XX_ATUX_STAT_REC_SCEM (1 << 12)
#define IOP13XX_ATUX_STAT_POWER_TRAN (1 << 11)
#define IOP13XX_ATUX_STAT_TX_SERR (1 << 10)
#define IOP13XX_ATUX_STAT_DET_PAR_ERR (1 << 9 )
#define IOP13XX_ATUX_STAT_BIST (1 << 8 )
#define IOP13XX_ATUX_STAT_INT_REC_MABORT (1 << 7 )
#define IOP13XX_ATUX_STAT_REC_SERR (1 << 4 )
#define IOP13XX_ATUX_STAT_EXT_REC_MABORT (1 << 3 )
#define IOP13XX_ATUX_STAT_EXT_REC_TABORT (1 << 2 )
#define IOP13XX_ATUX_STAT_EXT_SIG_TABORT (1 << 1 )
#define IOP13XX_ATUX_STAT_MASTER_DATA_PAR (1 << 0 )
#define IOP13XX_ATUX_PCIXSR_BUS_NUM (8)
#define IOP13XX_ATUX_PCIXSR_DEV_NUM (3)
#define IOP13XX_ATUX_PCIXSR_FUNC_NUM (0)
#define IOP13XX_ATUX_IALR_DISABLE 0x00000001
#define IOP13XX_ATUX_OUMBAR_ENABLE 0x80000000
#define IOP13XX_ATUE_OFFSET(ofs) IOP13XX_REG_ADDR32(\
iop13xx_atue_pmmr_offset + (ofs))
#define IOP13XX_ATUE_DID IOP13XX_REG_ADDR16(\
iop13xx_atue_pmmr_offset + 0x2)
#define IOP13XX_ATUE_ATUCMD IOP13XX_REG_ADDR16(\
iop13xx_atue_pmmr_offset + 0x4)
#define IOP13XX_ATUE_ATUSR IOP13XX_REG_ADDR16(\
iop13xx_atue_pmmr_offset + 0x6)
#define IOP13XX_ATUE_IABAR0 IOP13XX_ATUE_OFFSET(0x10)
#define IOP13XX_ATUE_IAUBAR0 IOP13XX_ATUE_OFFSET(0x14)
#define IOP13XX_ATUE_IABAR1 IOP13XX_ATUE_OFFSET(0x18)
#define IOP13XX_ATUE_IAUBAR1 IOP13XX_ATUE_OFFSET(0x1c)
#define IOP13XX_ATUE_IABAR2 IOP13XX_ATUE_OFFSET(0x20)
#define IOP13XX_ATUE_IAUBAR2 IOP13XX_ATUE_OFFSET(0x24)
#define IOP13XX_ATUE_IALR0 IOP13XX_ATUE_OFFSET(0x40)
#define IOP13XX_ATUE_IATVR0 IOP13XX_ATUE_OFFSET(0x44)
#define IOP13XX_ATUE_IAUTVR0 IOP13XX_ATUE_OFFSET(0x48)
#define IOP13XX_ATUE_IALR1 IOP13XX_ATUE_OFFSET(0x4c)
#define IOP13XX_ATUE_IATVR1 IOP13XX_ATUE_OFFSET(0x50)
#define IOP13XX_ATUE_IAUTVR1 IOP13XX_ATUE_OFFSET(0x54)
#define IOP13XX_ATUE_IALR2 IOP13XX_ATUE_OFFSET(0x58)
#define IOP13XX_ATUE_IATVR2 IOP13XX_ATUE_OFFSET(0x5c)
#define IOP13XX_ATUE_IAUTVR2 IOP13XX_ATUE_OFFSET(0x60)
#define IOP13XX_ATUE_PE_LSTS IOP13XX_REG_ADDR16(\
iop13xx_atue_pmmr_offset + 0xe2)
#define IOP13XX_ATUE_OIOWTVR IOP13XX_ATUE_OFFSET(0x304)
#define IOP13XX_ATUE_OUMBAR0 IOP13XX_ATUE_OFFSET(0x308)
#define IOP13XX_ATUE_OUMWTVR0 IOP13XX_ATUE_OFFSET(0x30c)
#define IOP13XX_ATUE_OUMBAR1 IOP13XX_ATUE_OFFSET(0x310)
#define IOP13XX_ATUE_OUMWTVR1 IOP13XX_ATUE_OFFSET(0x314)
#define IOP13XX_ATUE_OUMBAR2 IOP13XX_ATUE_OFFSET(0x318)
#define IOP13XX_ATUE_OUMWTVR2 IOP13XX_ATUE_OFFSET(0x31c)
#define IOP13XX_ATUE_OUMBAR3 IOP13XX_ATUE_OFFSET(0x320)
#define IOP13XX_ATUE_OUMWTVR3 IOP13XX_ATUE_OFFSET(0x324)
#define IOP13XX_ATUE_ATUCR IOP13XX_ATUE_OFFSET(0x70)
#define IOP13XX_ATUE_PCSR IOP13XX_ATUE_OFFSET(0x74)
#define IOP13XX_ATUE_ATUISR IOP13XX_ATUE_OFFSET(0x78)
#define IOP13XX_ATUE_OIOBAR IOP13XX_ATUE_OFFSET(0x300)
#define IOP13XX_ATUE_OCCAR IOP13XX_ATUE_OFFSET(0x32c)
#define IOP13XX_ATUE_OCCDR IOP13XX_ATUE_OFFSET(0x330)
#define IOP13XX_ATUE_PIE_STS IOP13XX_ATUE_OFFSET(0x384)
#define IOP13XX_ATUE_PIE_MSK IOP13XX_ATUE_OFFSET(0x388)
#define IOP13XX_ATUE_ATUCR_IVM (1 << 6)
#define IOP13XX_ATUE_ATUCR_OUT_EN (1 << 1)
#define IOP13XX_ATUE_OCCAR_BUS_NUM (24)
#define IOP13XX_ATUE_OCCAR_DEV_NUM (19)
#define IOP13XX_ATUE_OCCAR_FUNC_NUM (16)
#define IOP13XX_ATUE_OCCAR_EXT_REG (8)
#define IOP13XX_ATUE_OCCAR_REG (2)
#define IOP13XX_ATUE_PCSR_BUS_NUM (24)
#define IOP13XX_ATUE_PCSR_DEV_NUM (19)
#define IOP13XX_ATUE_PCSR_FUNC_NUM (16)
#define IOP13XX_ATUE_PCSR_OUT_Q_BUSY (1 << 15)
#define IOP13XX_ATUE_PCSR_IN_Q_BUSY (1 << 14)
#define IOP13XX_ATUE_PCSR_END_POINT (1 << 13)
#define IOP13XX_ATUE_PCSR_LLRB_BUSY (1 << 12)
#define IOP13XX_ATUE_PCSR_BUS_NUM_MASK (0xff)
#define IOP13XX_ATUE_PCSR_DEV_NUM_MASK (0x1f)
#define IOP13XX_ATUE_PCSR_FUNC_NUM_MASK (0x7)
#define IOP13XX_ATUE_PCSR_CORE_RESET (8)
#define IOP13XX_ATUE_PCSR_FUNC_NUM (16)
#define IOP13XX_ATUE_LSTS_TRAINING (1 << 11)
#define IOP13XX_ATUE_STAT_SLOT_PWR_MSG (1 << 28)
#define IOP13XX_ATUE_STAT_PME (1 << 27)
#define IOP13XX_ATUE_STAT_HOT_PLUG_MSG (1 << 26)
#define IOP13XX_ATUE_STAT_IVM (1 << 25)
#define IOP13XX_ATUE_STAT_BIST (1 << 24)
#define IOP13XX_ATUE_STAT_CFG_WRITE (1 << 18)
#define IOP13XX_ATUE_STAT_VPD_ADDR (1 << 17)
#define IOP13XX_ATUE_STAT_POWER_TRAN (1 << 16)
#define IOP13XX_ATUE_STAT_HALT_ON_ERROR (1 << 13)
#define IOP13XX_ATUE_STAT_ROOT_SYS_ERR (1 << 12)
#define IOP13XX_ATUE_STAT_ROOT_ERR_MSG (1 << 11)
#define IOP13XX_ATUE_STAT_PCI_IFACE_ERR (1 << 10)
#define IOP13XX_ATUE_STAT_ERR_COR (1 << 9 )
#define IOP13XX_ATUE_STAT_ERR_UNCOR (1 << 8 )
#define IOP13XX_ATUE_STAT_CRS (1 << 7 )
#define IOP13XX_ATUE_STAT_LNK_DWN (1 << 6 )
#define IOP13XX_ATUE_STAT_INT_REC_MABORT (1 << 5 )
#define IOP13XX_ATUE_STAT_DET_PAR_ERR (1 << 4 )
#define IOP13XX_ATUE_STAT_EXT_REC_MABORT (1 << 3 )
#define IOP13XX_ATUE_STAT_SIG_TABORT (1 << 2 )
#define IOP13XX_ATUE_STAT_EXT_REC_TABORT (1 << 1 )
#define IOP13XX_ATUE_STAT_MASTER_DATA_PAR (1 << 0 )
#define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_COMP_REQ (1 << 31)
#define IOP13XX_ATUE_ESTAT_REC_COMPLETER_ABORT (1 << 30)
#define IOP13XX_ATUE_ESTAT_TX_POISONED_TLP (1 << 29)
#define IOP13XX_ATUE_ESTAT_TX_PAR_ERR (1 << 28)
#define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_REQ (1 << 20)
#define IOP13XX_ATUE_ESTAT_REC_ECRC_ERR (1 << 19)
#define IOP13XX_ATUE_ESTAT_REC_MALFORMED_TLP (1 << 18)
#define IOP13XX_ATUE_ESTAT_TX_RECEIVER_OVERFLOW (1 << 17)
#define IOP13XX_ATUE_ESTAT_REC_UNEXPECTED_COMP (1 << 16)
#define IOP13XX_ATUE_ESTAT_INT_COMP_ABORT (1 << 15)
#define IOP13XX_ATUE_ESTAT_COMP_TIMEOUT (1 << 14)
#define IOP13XX_ATUE_ESTAT_FLOW_CONTROL_ERR (1 << 13)
#define IOP13XX_ATUE_ESTAT_REC_POISONED_TLP (1 << 12)
#define IOP13XX_ATUE_ESTAT_DATA_LNK_ERR (1 << 4 )
#define IOP13XX_ATUE_ESTAT_TRAINING_ERR (1 << 0 )
#define IOP13XX_ATUE_IALR_DISABLE (0x00000001)
#define IOP13XX_ATUE_OUMBAR_ENABLE (0x80000000)
#define IOP13XX_ATU_OUMBAR_FUNC_NUM (28)
#define IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK (0x7)
/*=======================================================================*/
/*==============================ADMA UNITS===============================*/
#define IOP13XX_ADMA_PHYS_BASE(chan) IOP13XX_REG_ADDR32_PHYS((chan << 9))
#define IOP13XX_ADMA_UPPER_PA(chan) (IOP13XX_ADMA_PHYS_BASE(chan) + 0xc0)
#define IOP13XX_ADMA_OFFSET(chan, ofs) IOP13XX_REG_ADDR32((chan << 9) + (ofs))
#define IOP13XX_ADMA_ACCR(chan) IOP13XX_ADMA_OFFSET(chan, 0x0)
#define IOP13XX_ADMA_ACSR(chan) IOP13XX_ADMA_OFFSET(chan, 0x4)
#define IOP13XX_ADMA_ADAR(chan) IOP13XX_ADMA_OFFSET(chan, 0x8)
#define IOP13XX_ADMA_IIPCR(chan) IOP13XX_ADMA_OFFSET(chan, 0x18)
#define IOP13XX_ADMA_IIPAR(chan) IOP13XX_ADMA_OFFSET(chan, 0x1c)
#define IOP13XX_ADMA_IIPUAR(chan) IOP13XX_ADMA_OFFSET(chan, 0x20)
#define IOP13XX_ADMA_ANDAR(chan) IOP13XX_ADMA_OFFSET(chan, 0x24)
#define IOP13XX_ADMA_ADCR(chan) IOP13XX_ADMA_OFFSET(chan, 0x28)
#define IOP13XX_ADMA_CARMD(chan) IOP13XX_ADMA_OFFSET(chan, 0x2c)
#define IOP13XX_ADMA_ABCR(chan) IOP13XX_ADMA_OFFSET(chan, 0x30)
#define IOP13XX_ADMA_DLADR(chan) IOP13XX_ADMA_OFFSET(chan, 0x34)
#define IOP13XX_ADMA_DUADR(chan) IOP13XX_ADMA_OFFSET(chan, 0x38)
#define IOP13XX_ADMA_SLAR(src, chan) IOP13XX_ADMA_OFFSET(chan, 0x3c + (src <<3))
#define IOP13XX_ADMA_SUAR(src, chan) IOP13XX_ADMA_OFFSET(chan, 0x40 + (src <<3))
/*==============================XSI BRIDGE===============================*/
#define IOP13XX_XBG_BECSR IOP13XX_REG_ADDR32(0x178c)
#define IOP13XX_XBG_BERAR IOP13XX_REG_ADDR32(0x1790)
#define IOP13XX_XBG_BERUAR IOP13XX_REG_ADDR32(0x1794)
#define is_atue_occdr_error(x) ((__raw_readl(IOP13XX_XBG_BERAR) == \
IOP13XX_PMMR_VIRT_TO_PHYS(\
IOP13XX_ATUE_OCCDR))\
&& (__raw_readl(IOP13XX_XBG_BECSR) & 1))
#define is_atux_occdr_error(x) ((__raw_readl(IOP13XX_XBG_BERAR) == \
IOP13XX_PMMR_VIRT_TO_PHYS(\
IOP13XX_ATUX_OCCDR))\
&& (__raw_readl(IOP13XX_XBG_BECSR) & 1))
/*=======================================================================*/
#define IOP13XX_PBI_OFFSET(ofs) IOP13XX_REG_ADDR32(IOP13XX_PBI_PMMR_OFFSET +\
(ofs))
#define IOP13XX_PBI_CR IOP13XX_PBI_OFFSET(0x0)
#define IOP13XX_PBI_SR IOP13XX_PBI_OFFSET(0x4)
#define IOP13XX_PBI_BAR0 IOP13XX_PBI_OFFSET(0x8)
#define IOP13XX_PBI_LR0 IOP13XX_PBI_OFFSET(0xc)
#define IOP13XX_PBI_BAR1 IOP13XX_PBI_OFFSET(0x10)
#define IOP13XX_PBI_LR1 IOP13XX_PBI_OFFSET(0x14)
#define IOP13XX_TMR_TC 0x01
#define IOP13XX_TMR_EN 0x02
#define IOP13XX_TMR_RELOAD 0x04
#define IOP13XX_TMR_PRIVILEGED 0x08
#define IOP13XX_TMR_RATIO_1_1 0x00
#define IOP13XX_TMR_RATIO_4_1 0x10
#define IOP13XX_TMR_RATIO_8_1 0x20
#define IOP13XX_TMR_RATIO_16_1 0x30
#endif /* _IOP13XX_HW_H_ */

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#ifndef _IQ81340_H_
#define _IQ81340_H_
#define IQ81340_PCE_BAR0 IOP13XX_PBI_LOWER_MEM_RA
#define IQ81340_PCE_BAR1 (IQ81340_PCE_BAR0 + 0x02000000)
#define IQ81340_FLASHBASE IQ81340_PCE_BAR0 /* Flash */
#define IQ81340_PCE_BAR1_OFFSET(a) (IQ81340_PCE_BAR1 + (a))
#define IQ81340_PRD_CODE IQ81340_PCE_BAR1_OFFSET(0)
#define IQ81340_BRD_STEP IQ81340_PCE_BAR1_OFFSET(0x10000)
#define IQ81340_CPLD_REV IQ81340_PCE_BAR1_OFFSET(0x20000)
#define IQ81340_LED IQ81340_PCE_BAR1_OFFSET(0x30000)
#define IQ81340_LHEX IQ81340_PCE_BAR1_OFFSET(0x40000)
#define IQ81340_RHEX IQ81340_PCE_BAR1_OFFSET(0x50000)
#define IQ81340_BUZZER IQ81340_PCE_BAR1_OFFSET(0x60000)
#define IQ81340_32K_NVRAM IQ81340_PCE_BAR1_OFFSET(0x70000)
#define IQ81340_256K_NVRAM IQ81340_PCE_BAR1_OFFSET(0x80000)
#define IQ81340_ROTARY_SW IQ81340_PCE_BAR1_OFFSET(0xd0000)
#define IQ81340_BATT_STAT IQ81340_PCE_BAR1_OFFSET(0xf0000)
#define IQ81340_CMP_FLSH IQ81340_PCE_BAR1_OFFSET(0x1000000) /* 16MB */
#define PBI_CF_IDE_BASE (IQ81340_CMP_FLSH)
#define PBI_CF_BAR_ADDR (IOP13XX_PBI_BAR1)
/* These are the values used in the Machine description */
#define PHYS_IO 0xfeffff00
#define IO_PG_OFFSET 0xffffff00
#define BOOT_PARAM_OFFSET 0x00000100
#endif /* _IQ81340_H_ */

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#ifndef _IOP13XX_IRQS_H_
#define _IOP13XX_IRQS_H_
#ifndef __ASSEMBLER__
#include <linux/types.h>
#include <asm/system.h> /* local_irq_save */
#include <asm/arch/iop13xx.h> /* iop13xx_cp6_* */
/* INTPND0 CP6 R0 Page 3
*/
static inline u32 read_intpnd_0(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c0, c3, 0":"=r" (val));
return val;
}
/* INTPND1 CP6 R1 Page 3
*/
static inline u32 read_intpnd_1(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c1, c3, 0":"=r" (val));
return val;
}
/* INTPND2 CP6 R2 Page 3
*/
static inline u32 read_intpnd_2(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c2, c3, 0":"=r" (val));
return val;
}
/* INTPND3 CP6 R3 Page 3
*/
static inline u32 read_intpnd_3(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c3, c3, 0":"=r" (val));
return val;
}
static inline void
iop13xx_cp6_enable_irq_save(unsigned long *cp_flags, unsigned long *irq_flags)
{
local_irq_save(*irq_flags);
*cp_flags = iop13xx_cp6_save();
}
static inline void
iop13xx_cp6_irq_restore(unsigned long *cp_flags,
unsigned long *irq_flags)
{
iop13xx_cp6_restore(*cp_flags);
local_irq_restore(*irq_flags);
}
#endif
#define INTBASE 0
#define INTSIZE_4 1
/*
* iop34x chipset interrupts
*/
#define IOP13XX_IRQ(x) (IOP13XX_IRQ_OFS + (x))
/*
* On IRQ or FIQ register
*/
#define IRQ_IOP13XX_ADMA0_EOT (0)
#define IRQ_IOP13XX_ADMA0_EOC (1)
#define IRQ_IOP13XX_ADMA1_EOT (2)
#define IRQ_IOP13XX_ADMA1_EOC (3)
#define IRQ_IOP13XX_ADMA2_EOT (4)
#define IRQ_IOP13XX_ADMA2_EOC (5)
#define IRQ_IOP134_WATCHDOG (6)
#define IRQ_IOP13XX_RSVD_7 (7)
#define IRQ_IOP13XX_TIMER0 (8)
#define IRQ_IOP13XX_TIMER1 (9)
#define IRQ_IOP13XX_I2C_0 (10)
#define IRQ_IOP13XX_I2C_1 (11)
#define IRQ_IOP13XX_MSG (12)
#define IRQ_IOP13XX_MSGIBQ (13)
#define IRQ_IOP13XX_ATU_IM (14)
#define IRQ_IOP13XX_ATU_BIST (15)
#define IRQ_IOP13XX_PPMU (16)
#define IRQ_IOP13XX_COREPMU (17)
#define IRQ_IOP13XX_CORECACHE (18)
#define IRQ_IOP13XX_RSVD_19 (19)
#define IRQ_IOP13XX_RSVD_20 (20)
#define IRQ_IOP13XX_RSVD_21 (21)
#define IRQ_IOP13XX_RSVD_22 (22)
#define IRQ_IOP13XX_RSVD_23 (23)
#define IRQ_IOP13XX_XINT0 (24)
#define IRQ_IOP13XX_XINT1 (25)
#define IRQ_IOP13XX_XINT2 (26)
#define IRQ_IOP13XX_XINT3 (27)
#define IRQ_IOP13XX_XINT4 (28)
#define IRQ_IOP13XX_XINT5 (29)
#define IRQ_IOP13XX_XINT6 (30)
#define IRQ_IOP13XX_XINT7 (31)
/* IINTSRC1 bit */
#define IRQ_IOP13XX_XINT8 (32) /* 0 */
#define IRQ_IOP13XX_XINT9 (33) /* 1 */
#define IRQ_IOP13XX_XINT10 (34) /* 2 */
#define IRQ_IOP13XX_XINT11 (35) /* 3 */
#define IRQ_IOP13XX_XINT12 (36) /* 4 */
#define IRQ_IOP13XX_XINT13 (37) /* 5 */
#define IRQ_IOP13XX_XINT14 (38) /* 6 */
#define IRQ_IOP13XX_XINT15 (39) /* 7 */
#define IRQ_IOP13XX_RSVD_40 (40) /* 8 */
#define IRQ_IOP13XX_RSVD_41 (41) /* 9 */
#define IRQ_IOP13XX_RSVD_42 (42) /* 10 */
#define IRQ_IOP13XX_RSVD_43 (43) /* 11 */
#define IRQ_IOP13XX_RSVD_44 (44) /* 12 */
#define IRQ_IOP13XX_RSVD_45 (45) /* 13 */
#define IRQ_IOP13XX_RSVD_46 (46) /* 14 */
#define IRQ_IOP13XX_RSVD_47 (47) /* 15 */
#define IRQ_IOP13XX_RSVD_48 (48) /* 16 */
#define IRQ_IOP13XX_RSVD_49 (49) /* 17 */
#define IRQ_IOP13XX_RSVD_50 (50) /* 18 */
#define IRQ_IOP13XX_UART0 (51) /* 19 */
#define IRQ_IOP13XX_UART1 (52) /* 20 */
#define IRQ_IOP13XX_PBIE (53) /* 21 */
#define IRQ_IOP13XX_ATU_CRW (54) /* 22 */
#define IRQ_IOP13XX_ATU_ERR (55) /* 23 */
#define IRQ_IOP13XX_MCU_ERR (56) /* 24 */
#define IRQ_IOP13XX_ADMA0_ERR (57) /* 25 */
#define IRQ_IOP13XX_ADMA1_ERR (58) /* 26 */
#define IRQ_IOP13XX_ADMA2_ERR (59) /* 27 */
#define IRQ_IOP13XX_RSVD_60 (60) /* 28 */
#define IRQ_IOP13XX_RSVD_61 (61) /* 29 */
#define IRQ_IOP13XX_MSG_ERR (62) /* 30 */
#define IRQ_IOP13XX_RSVD_63 (63) /* 31 */
/* IINTSRC2 bit */
#define IRQ_IOP13XX_INTERPROC (64) /* 0 */
#define IRQ_IOP13XX_RSVD_65 (65) /* 1 */
#define IRQ_IOP13XX_RSVD_66 (66) /* 2 */
#define IRQ_IOP13XX_RSVD_67 (67) /* 3 */
#define IRQ_IOP13XX_RSVD_68 (68) /* 4 */
#define IRQ_IOP13XX_RSVD_69 (69) /* 5 */
#define IRQ_IOP13XX_RSVD_70 (70) /* 6 */
#define IRQ_IOP13XX_RSVD_71 (71) /* 7 */
#define IRQ_IOP13XX_RSVD_72 (72) /* 8 */
#define IRQ_IOP13XX_RSVD_73 (73) /* 9 */
#define IRQ_IOP13XX_RSVD_74 (74) /* 10 */
#define IRQ_IOP13XX_RSVD_75 (75) /* 11 */
#define IRQ_IOP13XX_RSVD_76 (76) /* 12 */
#define IRQ_IOP13XX_RSVD_77 (77) /* 13 */
#define IRQ_IOP13XX_RSVD_78 (78) /* 14 */
#define IRQ_IOP13XX_RSVD_79 (79) /* 15 */
#define IRQ_IOP13XX_RSVD_80 (80) /* 16 */
#define IRQ_IOP13XX_RSVD_81 (81) /* 17 */
#define IRQ_IOP13XX_RSVD_82 (82) /* 18 */
#define IRQ_IOP13XX_RSVD_83 (83) /* 19 */
#define IRQ_IOP13XX_RSVD_84 (84) /* 20 */
#define IRQ_IOP13XX_RSVD_85 (85) /* 21 */
#define IRQ_IOP13XX_RSVD_86 (86) /* 22 */
#define IRQ_IOP13XX_RSVD_87 (87) /* 23 */
#define IRQ_IOP13XX_RSVD_88 (88) /* 24 */
#define IRQ_IOP13XX_RSVD_89 (89) /* 25 */
#define IRQ_IOP13XX_RSVD_90 (90) /* 26 */
#define IRQ_IOP13XX_RSVD_91 (91) /* 27 */
#define IRQ_IOP13XX_RSVD_92 (92) /* 28 */
#define IRQ_IOP13XX_RSVD_93 (93) /* 29 */
#define IRQ_IOP13XX_SIB_ERR (94) /* 30 */
#define IRQ_IOP13XX_SRAM_ERR (95) /* 31 */
/* IINTSRC3 bit */
#define IRQ_IOP13XX_I2C_2 (96) /* 0 */
#define IRQ_IOP13XX_ATUE_BIST (97) /* 1 */
#define IRQ_IOP13XX_ATUE_CRW (98) /* 2 */
#define IRQ_IOP13XX_ATUE_ERR (99) /* 3 */
#define IRQ_IOP13XX_IMU (100) /* 4 */
#define IRQ_IOP13XX_RSVD_101 (101) /* 5 */
#define IRQ_IOP13XX_RSVD_102 (102) /* 6 */
#define IRQ_IOP13XX_TPMI0_OUT (103) /* 7 */
#define IRQ_IOP13XX_TPMI1_OUT (104) /* 8 */
#define IRQ_IOP13XX_TPMI2_OUT (105) /* 9 */
#define IRQ_IOP13XX_TPMI3_OUT (106) /* 10 */
#define IRQ_IOP13XX_ATUE_IMA (107) /* 11 */
#define IRQ_IOP13XX_ATUE_IMB (108) /* 12 */
#define IRQ_IOP13XX_ATUE_IMC (109) /* 13 */
#define IRQ_IOP13XX_ATUE_IMD (110) /* 14 */
#define IRQ_IOP13XX_MU_MSI_TB (111) /* 15 */
#define IRQ_IOP13XX_RSVD_112 (112) /* 16 */
#define IRQ_IOP13XX_RSVD_113 (113) /* 17 */
#define IRQ_IOP13XX_RSVD_114 (114) /* 18 */
#define IRQ_IOP13XX_RSVD_115 (115) /* 19 */
#define IRQ_IOP13XX_RSVD_116 (116) /* 20 */
#define IRQ_IOP13XX_RSVD_117 (117) /* 21 */
#define IRQ_IOP13XX_RSVD_118 (118) /* 22 */
#define IRQ_IOP13XX_RSVD_119 (119) /* 23 */
#define IRQ_IOP13XX_RSVD_120 (120) /* 24 */
#define IRQ_IOP13XX_RSVD_121 (121) /* 25 */
#define IRQ_IOP13XX_RSVD_122 (122) /* 26 */
#define IRQ_IOP13XX_RSVD_123 (123) /* 27 */
#define IRQ_IOP13XX_RSVD_124 (124) /* 28 */
#define IRQ_IOP13XX_RSVD_125 (125) /* 29 */
#define IRQ_IOP13XX_RSVD_126 (126) /* 30 */
#define IRQ_IOP13XX_HPI (127) /* 31 */
#define NR_IOP13XX_IRQS (IRQ_IOP13XX_HPI + 1)
#define NR_IRQS NR_IOP13XX_IRQS
#endif /* _IOP13XX_IRQ_H_ */

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#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
#include <asm/arch/hardware.h>
/*
* Physical DRAM offset.
*/
#define PHYS_OFFSET UL(0x00000000)
#define TASK_SIZE UL(0x3f000000)
#define PAGE_OFFSET UL(0x40000000)
#define TASK_UNMAPPED_BASE ((TASK_SIZE + 0x01000000) / 3)
#ifndef __ASSEMBLY__
#if defined(CONFIG_ARCH_IOP13XX)
#define IOP13XX_PMMR_V_START (IOP13XX_PMMR_VIRT_MEM_BASE)
#define IOP13XX_PMMR_V_END (IOP13XX_PMMR_VIRT_MEM_BASE + IOP13XX_PMMR_SIZE)
#define IOP13XX_PMMR_P_START (IOP13XX_PMMR_PHYS_MEM_BASE)
#define IOP13XX_PMMR_P_END (IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_SIZE)
/*
* Virtual view <-> PCI DMA view memory address translations
* virt_to_bus: Used to translate the virtual address to an
* address suitable to be passed to set_dma_addr
* bus_to_virt: Used to convert an address for DMA operations
* to an address that the kernel can use.
*/
/* RAM has 1:1 mapping on the PCIe/x Busses */
#define __virt_to_bus(x) (__virt_to_phys(x))
#define __bus_to_virt(x) (__phys_to_virt(x))
#define virt_to_lbus(x) \
(( ((void*)(x) >= (void*)IOP13XX_PMMR_V_START) && \
((void*)(x) < (void*)IOP13XX_PMMR_V_END) ) ? \
((x) - IOP13XX_PMMR_VIRT_MEM_BASE + IOP13XX_PMMR_PHYS_MEM_BASE) : \
((x) - PAGE_OFFSET + PHYS_OFFSET))
#define lbus_to_virt(x) \
(( ((x) >= IOP13XX_PMMR_P_START) && ((x) < IOP13XX_PMMR_P_END) ) ? \
((x) - IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_VIRT_MEM_BASE ) : \
((x) - PHYS_OFFSET + PAGE_OFFSET))
/* Device is an lbus device if it is on the platform bus of the IOP13XX */
#define is_lbus_device(dev) (dev &&\
(strncmp(dev->bus->name, "platform", 8) == 0))
#define __arch_page_to_dma(dev, page) \
({is_lbus_device(dev) ? (dma_addr_t)virt_to_lbus(page_address(page)) : \
(dma_addr_t)__virt_to_bus(page_address(page));})
#define __arch_dma_to_virt(dev, addr) \
({is_lbus_device(dev) ? lbus_to_virt(addr) : __bus_to_virt(addr);})
#define __arch_virt_to_dma(dev, addr) \
({is_lbus_device(dev) ? virt_to_lbus(addr) : __virt_to_bus(addr);})
#endif /* CONFIG_ARCH_IOP13XX */
#endif /* !ASSEMBLY */
#define PFN_TO_NID(addr) (0)
#endif

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#ifndef _IOP13XX_PCI_H_
#define _IOP13XX_PCI_H_
#include <asm/arch/irqs.h>
#include <asm/io.h>
struct pci_sys_data;
struct hw_pci;
int iop13xx_pci_setup(int nr, struct pci_sys_data *sys);
struct pci_bus *iop13xx_scan_bus(int nr, struct pci_sys_data *);
void iop13xx_atu_select(struct hw_pci *plat_pci);
void iop13xx_pci_init(void);
void iop13xx_map_pci_memory(void);
#define IOP_PCI_STATUS_ERROR (PCI_STATUS_PARITY | \
PCI_STATUS_SIG_TARGET_ABORT | \
PCI_STATUS_REC_TARGET_ABORT | \
PCI_STATUS_REC_TARGET_ABORT | \
PCI_STATUS_REC_MASTER_ABORT | \
PCI_STATUS_SIG_SYSTEM_ERROR | \
PCI_STATUS_DETECTED_PARITY)
#define IOP13XX_ATUE_ATUISR_ERROR (IOP13XX_ATUE_STAT_HALT_ON_ERROR | \
IOP13XX_ATUE_STAT_ROOT_SYS_ERR | \
IOP13XX_ATUE_STAT_PCI_IFACE_ERR | \
IOP13XX_ATUE_STAT_ERR_COR | \
IOP13XX_ATUE_STAT_ERR_UNCOR | \
IOP13XX_ATUE_STAT_CRS | \
IOP13XX_ATUE_STAT_DET_PAR_ERR | \
IOP13XX_ATUE_STAT_EXT_REC_MABORT | \
IOP13XX_ATUE_STAT_SIG_TABORT | \
IOP13XX_ATUE_STAT_EXT_REC_TABORT | \
IOP13XX_ATUE_STAT_MASTER_DATA_PAR)
#define IOP13XX_ATUX_ATUISR_ERROR (IOP13XX_ATUX_STAT_TX_SCEM | \
IOP13XX_ATUX_STAT_REC_SCEM | \
IOP13XX_ATUX_STAT_TX_SERR | \
IOP13XX_ATUX_STAT_DET_PAR_ERR | \
IOP13XX_ATUX_STAT_INT_REC_MABORT | \
IOP13XX_ATUX_STAT_REC_SERR | \
IOP13XX_ATUX_STAT_EXT_REC_MABORT | \
IOP13XX_ATUX_STAT_EXT_REC_TABORT | \
IOP13XX_ATUX_STAT_EXT_SIG_TABORT | \
IOP13XX_ATUX_STAT_MASTER_DATA_PAR)
/* PCI interrupts
*/
#define ATUX_INTA IRQ_IOP13XX_XINT0
#define ATUX_INTB IRQ_IOP13XX_XINT1
#define ATUX_INTC IRQ_IOP13XX_XINT2
#define ATUX_INTD IRQ_IOP13XX_XINT3
#define ATUE_INTA IRQ_IOP13XX_ATUE_IMA
#define ATUE_INTB IRQ_IOP13XX_ATUE_IMB
#define ATUE_INTC IRQ_IOP13XX_ATUE_IMC
#define ATUE_INTD IRQ_IOP13XX_ATUE_IMD
#endif /* _IOP13XX_PCI_H_ */

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/*
* linux/include/asm-arm/arch-iop13xx/system.h
*
* Copyright (C) 2004 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <asm/arch/iop13xx.h>
static inline void arch_idle(void)
{
cpu_do_idle();
}
/* WDTCR CP6 R7 Page 9 */
static inline u32 read_wdtcr(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c7, c9, 0":"=r" (val));
return val;
}
static inline void write_wdtcr(u32 val)
{
asm volatile("mcr p6, 0, %0, c7, c9, 0"::"r" (val));
}
/* WDTSR CP6 R8 Page 9 */
static inline u32 read_wdtsr(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c8, c9, 0":"=r" (val));
return val;
}
static inline void write_wdtsr(u32 val)
{
asm volatile("mcr p6, 0, %0, c8, c9, 0"::"r" (val));
}
#define IOP13XX_WDTCR_EN_ARM 0x1e1e1e1e
#define IOP13XX_WDTCR_EN 0xe1e1e1e1
#define IOP13XX_WDTCR_DIS_ARM 0x1f1f1f1f
#define IOP13XX_WDTCR_DIS 0xf1f1f1f1
#define IOP13XX_WDTSR_WRITE_EN (1 << 31)
#define IOP13XX_WDTCR_IB_RESET (1 << 0)
static inline void arch_reset(char mode)
{
/*
* Reset the internal bus (warning both cores are reset)
*/
u32 cp_flags = iop13xx_cp6_save();
write_wdtcr(IOP13XX_WDTCR_EN_ARM);
write_wdtcr(IOP13XX_WDTCR_EN);
write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET);
write_wdtcr(0x1000);
iop13xx_cp6_restore(cp_flags);
for(;;);
}

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#include <asm/hardware.h>
#define CLOCK_TICK_RATE (100 * HZ)

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include/asm-arm/arch-iop13xx/uncompress.h Normal file
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#include <asm/types.h>
#include <linux/serial_reg.h>
#include <asm/hardware.h>
#include <asm/processor.h>
#define UART_BASE ((volatile u32 *)IOP13XX_UART1_PHYS)
#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
static inline void putc(char c)
{
while ((UART_BASE[UART_LSR] & TX_DONE) != TX_DONE)
cpu_relax();
UART_BASE[UART_TX] = c;
}
static inline void flush(void)
{
}
/*
* nothing to do
*/
#define arch_decomp_setup()
#define arch_decomp_wdog()

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#ifndef _VMALLOC_H_
#define _VMALLOC_H_
#define VMALLOC_END 0xfa000000UL
#endif