OpenE2K
/
linux
6
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

blackfin: bf60x: enable gptimer clock source 

Signed-off-by: Steven Miao <realmz6@gmail.com>
Signed-off-by: Bob Liu <lliubbo@gmail.com>
This commit is contained in:
Steven Miao 2012-05-16 18:11:10 +08:00 committed by Bob Liu
parent e578bbdeb8
commit 2879bb30d7
3 changed files with 211 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

104
arch/blackfin/include/asm/gptimers.h
View File

@ -43,6 +43,13 @@
# define TIMER8_GROUP_REG TMRS4_ENABLE
# define TIMER_GROUP2 1
#endif
/*
* BF609: 8 timers:
*/
#if defined(CONFIG_BF60x)
# define MAX_BLACKFIN_GPTIMERS 8
# define TIMER0_GROUP_REG TIMER_RUN
#endif
/*
* All others: 3 timers:
*/
@ -104,6 +111,72 @@
# define FS2_TIMER_BIT TIMER1bit
#endif
#ifdef CONFIG_BF60x
/*
* Timer Configuration Register Bits
*/
#define TIMER_EMU_RUN 0x8000
#define TIMER_BPER_EN 0x4000
#define TIMER_BWID_EN 0x2000
#define TIMER_BDLY_EN 0x1000
#define TIMER_OUT_DIS 0x0800
#define TIMER_TIN_SEL 0x0400
#define TIMER_CLK_SEL 0x0300
#define TIMER_CLK_SCLK 0x0000
#define TIMER_CLK_ALT_CLK0 0x0100
#define TIMER_CLK_ALT_CLK1 0x0300
#define TIMER_PULSE_HI 0x0080
#define TIMER_SLAVE_TRIG 0x0040
#define TIMER_IRQ_MODE 0x0030
#define TIMER_IRQ_ACT_EDGE 0x0000
#define TIMER_IRQ_DLY 0x0010
#define TIMER_IRQ_WID_DLY 0x0020
#define TIMER_IRQ_PER 0x0030
#define TIMER_MODE 0x000f
#define TIMER_MODE_WDOG_P 0x0008
#define TIMER_MODE_WDOG_W 0x0009
#define TIMER_MODE_PWM_CONT 0x000c
#define TIMER_MODE_PWM 0x000d
#define TIMER_MODE_WDTH 0x000a
#define TIMER_MODE_WDTH_D 0x000b
#define TIMER_MODE_EXT_CLK 0x000e
#define TIMER_MODE_PININT 0x000f
/*
* Timer Status Register Bits
*/
#define TIMER_STATUS_TIMIL0 0x0001
#define TIMER_STATUS_TIMIL1 0x0002
#define TIMER_STATUS_TIMIL2 0x0004
#define TIMER_STATUS_TIMIL3 0x0008
#define TIMER_STATUS_TIMIL4 0x0010
#define TIMER_STATUS_TIMIL5 0x0020
#define TIMER_STATUS_TIMIL6 0x0040
#define TIMER_STATUS_TIMIL7 0x0080
#define TIMER_STATUS_TOVF0 0x0001 /* timer 0 overflow error */
#define TIMER_STATUS_TOVF1 0x0002
#define TIMER_STATUS_TOVF2 0x0004
#define TIMER_STATUS_TOVF3 0x0008
#define TIMER_STATUS_TOVF4 0x0010
#define TIMER_STATUS_TOVF5 0x0020
#define TIMER_STATUS_TOVF6 0x0040
#define TIMER_STATUS_TOVF7 0x0080
/*
* Timer Slave Enable Status : write 1 to clear
*/
#define TIMER_STATUS_TRUN0 0x0001
#define TIMER_STATUS_TRUN1 0x0002
#define TIMER_STATUS_TRUN2 0x0004
#define TIMER_STATUS_TRUN3 0x0008
#define TIMER_STATUS_TRUN4 0x0010
#define TIMER_STATUS_TRUN5 0x0020
#define TIMER_STATUS_TRUN6 0x0040
#define TIMER_STATUS_TRUN7 0x0080
#else
/*
* Timer Configuration Register Bits
*/
@ -170,12 +243,18 @@
#define TIMER_STATUS_TRUN10 0x4000
#define TIMER_STATUS_TRUN11 0x8000
#endif
/* The actual gptimer API */
void set_gptimer_pwidth(unsigned int timer_id, uint32_t width);
uint32_t get_gptimer_pwidth(unsigned int timer_id);
void set_gptimer_period(unsigned int timer_id, uint32_t period);
uint32_t get_gptimer_period(unsigned int timer_id);
#ifdef CONFIG_BF60x
void set_gptimer_delay(unsigned int timer_id, uint32_t delay);
uint32_t get_gptimer_delay(unsigned int timer_id);
#endif
uint32_t get_gptimer_count(unsigned int timer_id);
int get_gptimer_intr(unsigned int timer_id);
void clear_gptimer_intr(unsigned int timer_id);
@ -217,16 +296,41 @@ struct bfin_gptimer_regs {
u32 counter;
u32 period;
u32 width;
#ifdef CONFIG_BF60x
u32 delay;
#endif
};
/*
* bfin group timer registers layout
*/
#ifndef CONFIG_BF60x
struct bfin_gptimer_group_regs {
__BFP(enable);
__BFP(disable);
u32 status;
};
#else
struct bfin_gptimer_group_regs {
__BFP(run);
__BFP(enable);
__BFP(disable);
__BFP(stop_cfg);
__BFP(stop_cfg_set);
__BFP(stop_cfg_clr);
__BFP(data_imsk);
__BFP(stat_imsk);
__BFP(tr_msk);
__BFP(tr_ie);
__BFP(data_ilat);
__BFP(stat_ilat);
__BFP(err_status);
__BFP(bcast_per);
__BFP(bcast_wid);
__BFP(bcast_dly);
};
#endif
#undef __BFP

83
arch/blackfin/kernel/gptimers.c
View File

@ -23,7 +23,11 @@
printk(KERN_DEBUG "%s:%s:%i: Assertion failed: " #expr "\n", __FILE__, __func__, __LINE__);
#endif
#define BFIN_TIMER_NUM_GROUP (BFIN_TIMER_OCTET(MAX_BLACKFIN_GPTIMERS - 1) + 1)
#ifndef CONFIG_BF60x
# define BFIN_TIMER_NUM_GROUP (BFIN_TIMER_OCTET(MAX_BLACKFIN_GPTIMERS - 1) + 1)
#else
# define BFIN_TIMER_NUM_GROUP 1
#endif
static struct bfin_gptimer_regs * const timer_regs[MAX_BLACKFIN_GPTIMERS] =
{
@ -158,6 +162,74 @@ uint32_t get_gptimer_count(unsigned int timer_id)
}
EXPORT_SYMBOL(get_gptimer_count);
#ifdef CONFIG_BF60x
void set_gptimer_delay(unsigned int timer_id, uint32_t delay)
{
tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
bfin_write(&timer_regs[timer_id]->delay, delay);
SSYNC();
}
EXPORT_SYMBOL(set_gptimer_delay);
uint32_t get_gptimer_delay(unsigned int timer_id)
{
tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
return bfin_read(&timer_regs[timer_id]->delay);
}
EXPORT_SYMBOL(get_gptimer_delay);
#endif
#ifdef CONFIG_BF60x
int get_gptimer_intr(unsigned int timer_id)
{
tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
return !!(bfin_read(&group_regs[BFIN_TIMER_OCTET(timer_id)]->data_ilat) & timil_mask[timer_id]);
}
EXPORT_SYMBOL(get_gptimer_intr);
void clear_gptimer_intr(unsigned int timer_id)
{
tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
bfin_write(&group_regs[BFIN_TIMER_OCTET(timer_id)]->data_ilat, timil_mask[timer_id]);
}
EXPORT_SYMBOL(clear_gptimer_intr);
int get_gptimer_over(unsigned int timer_id)
{
tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
return !!(bfin_read(&group_regs[BFIN_TIMER_OCTET(timer_id)]->stat_ilat) & tovf_mask[timer_id]);
}
EXPORT_SYMBOL(get_gptimer_over);
void clear_gptimer_over(unsigned int timer_id)
{
tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
bfin_write(&group_regs[BFIN_TIMER_OCTET(timer_id)]->stat_ilat, tovf_mask[timer_id]);
}
EXPORT_SYMBOL(clear_gptimer_over);
int get_gptimer_run(unsigned int timer_id)
{
tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
return !!(bfin_read(&group_regs[BFIN_TIMER_OCTET(timer_id)]->run) & trun_mask[timer_id]);
}
EXPORT_SYMBOL(get_gptimer_run);
uint32_t get_gptimer_status(unsigned int group)
{
tassert(group < BFIN_TIMER_NUM_GROUP);
return bfin_read(&group_regs[group]->data_ilat);
}
EXPORT_SYMBOL(get_gptimer_status);
void set_gptimer_status(unsigned int group, uint32_t value)
{
tassert(group < BFIN_TIMER_NUM_GROUP);
bfin_write(&group_regs[group]->data_ilat, value);
SSYNC();
}
EXPORT_SYMBOL(set_gptimer_status);
#else
uint32_t get_gptimer_status(unsigned int group)
{
tassert(group < BFIN_TIMER_NUM_GROUP);
@ -212,6 +284,7 @@ int get_gptimer_run(unsigned int timer_id)
return !!(read_gptimer_status(timer_id) & trun_mask[timer_id]);
}
EXPORT_SYMBOL(get_gptimer_run);
#endif
void set_gptimer_config(unsigned int timer_id, uint16_t config)
{
@ -231,6 +304,12 @@ EXPORT_SYMBOL(get_gptimer_config);
void enable_gptimers(uint16_t mask)
{
int i;
#ifdef CONFIG_BF60x
uint16_t imask;
imask = bfin_read16(TIMER_DATA_IMSK);
imask &= ~mask;
bfin_write16(TIMER_DATA_IMSK, imask);
#endif
tassert((mask & ~BLACKFIN_GPTIMER_IDMASK) == 0);
for (i = 0; i < BFIN_TIMER_NUM_GROUP; ++i) {
bfin_write(&group_regs[i]->enable, mask & 0xFF);
@ -255,10 +334,12 @@ void disable_gptimers(uint16_t mask)
{
int i;
_disable_gptimers(mask);
#ifndef CONFIG_BF60x
for (i = 0; i < MAX_BLACKFIN_GPTIMERS; ++i)
if (mask & (1 << i))
bfin_write(&group_regs[BFIN_TIMER_OCTET(i)]->status, trun_mask[i]);
SSYNC();
#endif
}
EXPORT_SYMBOL(disable_gptimers);

27
arch/blackfin/kernel/time-ts.c
View File

@ -66,8 +66,14 @@ void __init setup_gptimer0(void)
{
disable_gptimers(TIMER0bit);
#ifdef CONFIG_BF60x
bfin_write16(TIMER_DATA_IMSK, 0);
set_gptimer_config(TIMER0_id, TIMER_OUT_DIS
| TIMER_MODE_PWM_CONT | TIMER_PULSE_HI | TIMER_IRQ_PER);
#else
set_gptimer_config(TIMER0_id, \
TIMER_OUT_DIS | TIMER_PERIOD_CNT | TIMER_MODE_PWM);
#endif
set_gptimer_period(TIMER0_id, -1);
set_gptimer_pwidth(TIMER0_id, -2);
SSYNC();
@ -135,9 +141,15 @@ static void bfin_gptmr0_set_mode(enum clock_event_mode mode,
{
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC: {
#ifndef CONFIG_BF60x
set_gptimer_config(TIMER0_id, \
TIMER_OUT_DIS | TIMER_IRQ_ENA | \
TIMER_PERIOD_CNT | TIMER_MODE_PWM);
#else
set_gptimer_config(TIMER0_id, TIMER_OUT_DIS
| TIMER_MODE_PWM_CONT | TIMER_PULSE_HI | TIMER_IRQ_PER);
#endif
set_gptimer_period(TIMER0_id, get_sclk() / HZ);
set_gptimer_pwidth(TIMER0_id, get_sclk() / HZ - 1);
enable_gptimers(TIMER0bit);
@ -145,8 +157,14 @@ static void bfin_gptmr0_set_mode(enum clock_event_mode mode,
}
case CLOCK_EVT_MODE_ONESHOT:
disable_gptimers(TIMER0bit);
#ifndef CONFIG_BF60x
set_gptimer_config(TIMER0_id, \
TIMER_OUT_DIS | TIMER_IRQ_ENA | TIMER_MODE_PWM);
#else
set_gptimer_config(TIMER0_id, TIMER_OUT_DIS | TIMER_MODE_PWM
| TIMER_PULSE_HI | TIMER_IRQ_WID_DLY);
#endif
set_gptimer_period(TIMER0_id, 0);
break;
case CLOCK_EVT_MODE_UNUSED:
@ -160,7 +178,7 @@ static void bfin_gptmr0_set_mode(enum clock_event_mode mode,
static void bfin_gptmr0_ack(void)
{
set_gptimer_status(TIMER_GROUP1, TIMER_STATUS_TIMIL0);
clear_gptimer_intr(TIMER0_id);
}
static void __init bfin_gptmr0_init(void)
@ -197,7 +215,7 @@ static struct clock_event_device clockevent_gptmr0 = {
.rating = 300,
.irq = IRQ_TIMER0,
.shift = 32,
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
.set_next_event = bfin_gptmr0_set_next_event,
.set_mode = bfin_gptmr0_set_mode,
};
@ -307,6 +325,11 @@ void bfin_coretmr_clockevent_init(void)
unsigned int cpu = smp_processor_id();
struct clock_event_device *evt = &per_cpu(coretmr_events, cpu);
#ifdef CONFIG_SMP
evt->broadcast = smp_timer_broadcast;
#endif
#ifdef CONFIG_SMP
evt->broadcast = smp_timer_broadcast;
#endif