- New Hi3660 mailbox driver
- Fix TEGRA Kconfig warning - Broadcom: use dma_pool_zalloc instead of dma_pool_alloc+memset -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJax2MRAAoJEH/ZZH/HmD+Vl1sP/0vd6J5GHRkvu6FFz9TjCrhI f3zDl6kphiMYym4rs6nThWnLwgp4Pbakg1ILV0WC3I+RPKTi38Ob9aYSlg1HfwPb xHVBMYBNnypAubVKS3fqtekldTY7ABLIcLbDah5L/lk/1uDzoDwTuJVH5RDyccwU h4/56lq66Qiyw15gobFg2PdYo2wVKdmyQP8aT9xPncyuKeS4lT4V8Twu6MS7OHt3 ZEHVU1QIxEWdYVUqi9TJGCfyNsK9MmoLVP/ppeOnk8cTbd+uhhLuSZSBGEyFQsPV UR9m/EG4waqNd8gQKytUu/ylV8iedXPKjAhKhOSDTixjOz9VOGq/BdP5U3eFZ+4V eN46q4a1t8pTv3YtaGe5OYaloUNXYGW80RTHumDncOCZSv93ykMDkIDF6uHyRAUv 1yrZrKHJtYpffL0wf45qhcu0/Qc3SVsP59XDz5CkjmFAYa9h8n5lp9QbF7y7aH1M wxhKyZxBleQI+HSgDJIr9uJigUdrZYYYVrw77z55Z8DpuQJd9kTZNt0aLljgkUrf Ll9BZsGJ2QnDzXWss9DKfNBSbgcp1cJlwj87q7t+AxHg43SGQfqtSBtlunfMSdem 7UGZf0Nw+ejeyoOl/qRXSpJzST7HCvZdA7nojK47jyF4gejxTKkaaWPFszYnlVvI yhqpXyS5D3fY7NkZ4Gqo =tUhj -----END PGP SIGNATURE----- Merge tag 'mailbox-v4.17' of git://git.linaro.org/landing-teams/working/fujitsu/integration Pull mailbox updates from Jassi Brar: - New Hi3660 mailbox driver - Fix TEGRA Kconfig warning - Broadcom: use dma_pool_zalloc instead of dma_pool_alloc+memset * tag 'mailbox-v4.17' of git://git.linaro.org/landing-teams/working/fujitsu/integration: mailbox: Add support for Hi3660 mailbox dt-bindings: mailbox: Introduce Hi3660 controller binding mailbox: tegra: relax TEGRA_HSP_MBOX Kconfig dependencies maillbox: bcm-flexrm-mailbox: Use dma_pool_zalloc()
This commit is contained in:
Linus Torvalds
commit
28da7be5eb
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@ -0,0 +1,51 @@
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Hisilicon Hi3660 Mailbox Controller
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Hisilicon Hi3660 mailbox controller supports up to 32 channels. Messages
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are passed between processors, including application & communication
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processors, MCU, HIFI, etc. Each channel is unidirectional and accessed
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by using MMIO registers; it supports maximum to 8 words message.
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Controller
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----------
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Required properties:
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- compatible: : Shall be "hisilicon,hi3660-mbox"
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- reg: : Offset and length of the device's register set
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- #mbox-cells: : Must be 3
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<&phandle channel dst_irq ack_irq>
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phandle : Label name of controller
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channel : Channel number
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dst_irq : Remote interrupt vector
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ack_irq : Local interrupt vector
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- interrupts: : Contains the two IRQ lines for mailbox.
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Example:
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mailbox: mailbox@e896b000 {
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compatible = "hisilicon,hi3660-mbox";
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reg = <0x0 0xe896b000 0x0 0x1000>;
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interrupts = <0x0 0xc0 0x4>,
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<0x0 0xc1 0x4>;
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#mbox-cells = <3>;
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};
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Client
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------
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Required properties:
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- compatible : See the client docs
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- mboxes : Standard property to specify a Mailbox (See ./mailbox.txt)
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Cells must match 'mbox-cells' (See Controller docs above)
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Optional properties
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- mbox-names : Name given to channels seen in the 'mboxes' property.
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Example:
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stub_clock: stub_clock@e896b500 {
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compatible = "hisilicon,hi3660-stub-clk";
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reg = <0x0 0xe896b500 0x0 0x0100>;
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#clock-cells = <1>;
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mboxes = <&mailbox 13 3 0>;
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};
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@ -108,6 +108,14 @@ config TI_MESSAGE_MANAGER
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multiple processors within the SoC. Select this driver if your
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platform has support for the hardware block.
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config HI3660_MBOX
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tristate "Hi3660 Mailbox"
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depends on ARCH_HISI && OF
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help
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An implementation of the hi3660 mailbox. It is used to send message
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between application processors and other processors/MCU/DSP. Select
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Y here if you want to use Hi3660 mailbox controller.
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config HI6220_MBOX
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tristate "Hi6220 Mailbox"
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depends on ARCH_HISI
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@ -134,7 +142,7 @@ config QCOM_APCS_IPC
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config TEGRA_HSP_MBOX
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bool "Tegra HSP (Hardware Synchronization Primitives) Driver"
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depends on ARCH_TEGRA_186_SOC
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depends on ARCH_TEGRA
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help
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The Tegra HSP driver is used for the interprocessor communication
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between different remote processors and host processors on Tegra186
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@ -27,6 +27,8 @@ obj-$(CONFIG_TI_MESSAGE_MANAGER) += ti-msgmgr.o
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obj-$(CONFIG_XGENE_SLIMPRO_MBOX) += mailbox-xgene-slimpro.o
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obj-$(CONFIG_HI3660_MBOX) += hi3660-mailbox.o
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obj-$(CONFIG_HI6220_MBOX) += hi6220-mailbox.o
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obj-$(CONFIG_BCM_PDC_MBOX) += bcm-pdc-mailbox.o
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@ -1268,7 +1268,7 @@ static int flexrm_startup(struct mbox_chan *chan)
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}
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/* Allocate completion memory */
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ring->cmpl_base = dma_pool_alloc(ring->mbox->cmpl_pool,
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ring->cmpl_base = dma_pool_zalloc(ring->mbox->cmpl_pool,
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GFP_KERNEL, &ring->cmpl_dma_base);
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if (!ring->cmpl_base) {
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dev_err(ring->mbox->dev,
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@ -1277,7 +1277,6 @@ static int flexrm_startup(struct mbox_chan *chan)
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ret = -ENOMEM;
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goto fail_free_bd_memory;
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}
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memset(ring->cmpl_base, 0, RING_CMPL_SIZE);
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/* Request IRQ */
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if (ring->irq == UINT_MAX) {
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@ -0,0 +1,312 @@
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// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2017-2018 Hisilicon Limited.
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// Copyright (c) 2017-2018 Linaro Limited.
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/mailbox_controller.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include "mailbox.h"
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#define MBOX_CHAN_MAX 32
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#define MBOX_RX 0x0
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#define MBOX_TX 0x1
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#define MBOX_BASE(mbox, ch) ((mbox)->base + ((ch) * 0x40))
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#define MBOX_SRC_REG 0x00
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#define MBOX_DST_REG 0x04
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#define MBOX_DCLR_REG 0x08
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#define MBOX_DSTAT_REG 0x0c
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#define MBOX_MODE_REG 0x10
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#define MBOX_IMASK_REG 0x14
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#define MBOX_ICLR_REG 0x18
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#define MBOX_SEND_REG 0x1c
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#define MBOX_DATA_REG 0x20
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#define MBOX_IPC_LOCK_REG 0xa00
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#define MBOX_IPC_UNLOCK 0x1acce551
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#define MBOX_AUTOMATIC_ACK 1
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#define MBOX_STATE_IDLE BIT(4)
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#define MBOX_STATE_ACK BIT(7)
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#define MBOX_MSG_LEN 8
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/**
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* Hi3660 mailbox channel information
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*
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* A channel can be used for TX or RX, it can trigger remote
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* processor interrupt to notify remote processor and can receive
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* interrupt if has incoming message.
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*
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* @dst_irq: Interrupt vector for remote processor
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* @ack_irq: Interrupt vector for local processor
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*/
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struct hi3660_chan_info {
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unsigned int dst_irq;
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unsigned int ack_irq;
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};
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/**
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* Hi3660 mailbox controller data
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*
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* Mailbox controller includes 32 channels and can allocate
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* channel for message transferring.
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*
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* @dev: Device to which it is attached
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* @base: Base address of the register mapping region
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* @chan: Representation of channels in mailbox controller
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* @mchan: Representation of channel info
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* @controller: Representation of a communication channel controller
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*/
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struct hi3660_mbox {
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struct device *dev;
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void __iomem *base;
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struct mbox_chan chan[MBOX_CHAN_MAX];
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struct hi3660_chan_info mchan[MBOX_CHAN_MAX];
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struct mbox_controller controller;
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};
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static struct hi3660_mbox *to_hi3660_mbox(struct mbox_controller *mbox)
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{
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return container_of(mbox, struct hi3660_mbox, controller);
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}
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static int hi3660_mbox_check_state(struct mbox_chan *chan)
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{
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unsigned long ch = (unsigned long)chan->con_priv;
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struct hi3660_mbox *mbox = to_hi3660_mbox(chan->mbox);
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struct hi3660_chan_info *mchan = &mbox->mchan[ch];
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void __iomem *base = MBOX_BASE(mbox, ch);
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unsigned long val;
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unsigned int ret;
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/* Mailbox is idle so directly bail out */
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if (readl(base + MBOX_MODE_REG) & MBOX_STATE_IDLE)
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return 0;
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/* Wait for acknowledge from remote */
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ret = readx_poll_timeout_atomic(readl, base + MBOX_MODE_REG,
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val, (val & MBOX_STATE_ACK), 1000, 300000);
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if (ret) {
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dev_err(mbox->dev, "%s: timeout for receiving ack\n", __func__);
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return ret;
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}
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/* Ensure channel is released */
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writel(0xffffffff, base + MBOX_IMASK_REG);
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writel(BIT(mchan->ack_irq), base + MBOX_SRC_REG);
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return 0;
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}
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static int hi3660_mbox_unlock(struct mbox_chan *chan)
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{
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struct hi3660_mbox *mbox = to_hi3660_mbox(chan->mbox);
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unsigned int val, retry = 3;
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do {
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writel(MBOX_IPC_UNLOCK, mbox->base + MBOX_IPC_LOCK_REG);
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val = readl(mbox->base + MBOX_IPC_LOCK_REG);
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if (!val)
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break;
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udelay(10);
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} while (retry--);
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if (val)
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dev_err(mbox->dev, "%s: failed to unlock mailbox\n", __func__);
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return (!val) ? 0 : -ETIMEDOUT;
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}
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static int hi3660_mbox_acquire_channel(struct mbox_chan *chan)
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{
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unsigned long ch = (unsigned long)chan->con_priv;
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struct hi3660_mbox *mbox = to_hi3660_mbox(chan->mbox);
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struct hi3660_chan_info *mchan = &mbox->mchan[ch];
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void __iomem *base = MBOX_BASE(mbox, ch);
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unsigned int val, retry;
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for (retry = 10; retry; retry--) {
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/* Check if channel is in idle state */
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if (readl(base + MBOX_MODE_REG) & MBOX_STATE_IDLE) {
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writel(BIT(mchan->ack_irq), base + MBOX_SRC_REG);
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/* Check ack bit has been set successfully */
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val = readl(base + MBOX_SRC_REG);
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if (val & BIT(mchan->ack_irq))
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break;
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}
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}
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if (!retry)
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dev_err(mbox->dev, "%s: failed to acquire channel\n", __func__);
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return retry ? 0 : -ETIMEDOUT;
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}
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static int hi3660_mbox_startup(struct mbox_chan *chan)
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{
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int ret;
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ret = hi3660_mbox_check_state(chan);
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if (ret)
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return ret;
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ret = hi3660_mbox_unlock(chan);
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if (ret)
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return ret;
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ret = hi3660_mbox_acquire_channel(chan);
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if (ret)
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return ret;
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return 0;
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}
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static int hi3660_mbox_send_data(struct mbox_chan *chan, void *msg)
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{
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unsigned long ch = (unsigned long)chan->con_priv;
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struct hi3660_mbox *mbox = to_hi3660_mbox(chan->mbox);
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struct hi3660_chan_info *mchan = &mbox->mchan[ch];
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void __iomem *base = MBOX_BASE(mbox, ch);
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u32 *buf = msg;
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unsigned int i;
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/* Ensure channel is released */
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writel_relaxed(0xffffffff, base + MBOX_IMASK_REG);
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writel_relaxed(BIT(mchan->ack_irq), base + MBOX_SRC_REG);
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/* Clear mask for destination interrupt */
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writel_relaxed(~BIT(mchan->dst_irq), base + MBOX_IMASK_REG);
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/* Config destination for interrupt vector */
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writel_relaxed(BIT(mchan->dst_irq), base + MBOX_DST_REG);
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/* Automatic acknowledge mode */
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writel_relaxed(MBOX_AUTOMATIC_ACK, base + MBOX_MODE_REG);
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/* Fill message data */
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for (i = 0; i < MBOX_MSG_LEN; i++)
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writel_relaxed(buf[i], base + MBOX_DATA_REG + i * 4);
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/* Trigger data transferring */
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writel(BIT(mchan->ack_irq), base + MBOX_SEND_REG);
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return 0;
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}
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static struct mbox_chan_ops hi3660_mbox_ops = {
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.startup = hi3660_mbox_startup,
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.send_data = hi3660_mbox_send_data,
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};
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static struct mbox_chan *hi3660_mbox_xlate(struct mbox_controller *controller,
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const struct of_phandle_args *spec)
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{
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struct hi3660_mbox *mbox = to_hi3660_mbox(controller);
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struct hi3660_chan_info *mchan;
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unsigned int ch = spec->args[0];
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if (ch >= MBOX_CHAN_MAX) {
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dev_err(mbox->dev, "Invalid channel idx %d\n", ch);
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return ERR_PTR(-EINVAL);
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}
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mchan = &mbox->mchan[ch];
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mchan->dst_irq = spec->args[1];
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mchan->ack_irq = spec->args[2];
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return &mbox->chan[ch];
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}
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static const struct of_device_id hi3660_mbox_of_match[] = {
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{ .compatible = "hisilicon,hi3660-mbox", },
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{},
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};
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MODULE_DEVICE_TABLE(of, hi3660_mbox_of_match);
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static int hi3660_mbox_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct hi3660_mbox *mbox;
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struct mbox_chan *chan;
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struct resource *res;
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unsigned long ch;
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int err;
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mbox = devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL);
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if (!mbox)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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mbox->base = devm_ioremap_resource(dev, res);
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if (IS_ERR(mbox->base))
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return PTR_ERR(mbox->base);
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mbox->dev = dev;
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mbox->controller.dev = dev;
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mbox->controller.chans = mbox->chan;
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mbox->controller.num_chans = MBOX_CHAN_MAX;
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mbox->controller.ops = &hi3660_mbox_ops;
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mbox->controller.of_xlate = hi3660_mbox_xlate;
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/* Initialize mailbox channel data */
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chan = mbox->chan;
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for (ch = 0; ch < MBOX_CHAN_MAX; ch++)
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chan[ch].con_priv = (void *)ch;
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err = mbox_controller_register(&mbox->controller);
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if (err) {
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dev_err(dev, "Failed to register mailbox %d\n", err);
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return err;
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}
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platform_set_drvdata(pdev, mbox);
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dev_info(dev, "Mailbox enabled\n");
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return 0;
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}
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static int hi3660_mbox_remove(struct platform_device *pdev)
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{
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struct hi3660_mbox *mbox = platform_get_drvdata(pdev);
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mbox_controller_unregister(&mbox->controller);
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return 0;
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}
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static struct platform_driver hi3660_mbox_driver = {
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.probe = hi3660_mbox_probe,
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.remove = hi3660_mbox_remove,
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.driver = {
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.name = "hi3660-mbox",
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.of_match_table = hi3660_mbox_of_match,
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},
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};
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static int __init hi3660_mbox_init(void)
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{
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return platform_driver_register(&hi3660_mbox_driver);
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}
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core_initcall(hi3660_mbox_init);
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static void __exit hi3660_mbox_exit(void)
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{
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platform_driver_unregister(&hi3660_mbox_driver);
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}
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module_exit(hi3660_mbox_exit);
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MODULE_LICENSE("GPL");
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MODULE_DESCRIPTION("Hisilicon Hi3660 Mailbox Controller");
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MODULE_AUTHOR("Leo Yan <leo.yan@linaro.org>");
|
||||
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