[POWERPC] 83xx: Handle mpc8360 rev. 2.1 RGMII timing erratum
If on a rev. 2.1, adjust UCC clock and data timing characteristics as specified in the rev.2.1 erratum #2. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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@ -96,14 +96,39 @@ static void __init mpc836x_mds_setup_arch(void)
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if ((np = of_find_compatible_node(NULL, "network", "ucc_geth"))
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!= NULL){
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uint svid;
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/* Reset the Ethernet PHY */
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bcsr_regs[9] &= ~0x20;
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#define BCSR9_GETHRST 0x20
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clrbits8(&bcsr_regs[9], BCSR9_GETHRST);
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udelay(1000);
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bcsr_regs[9] |= 0x20;
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setbits8(&bcsr_regs[9], BCSR9_GETHRST);
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/* handle mpc8360ea rev.2.1 erratum 2: RGMII Timing */
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svid = mfspr(SPRN_SVR);
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if (svid == 0x80480021) {
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void __iomem *immap;
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immap = ioremap(get_immrbase() + 0x14a8, 8);
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/*
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* IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
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* IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
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*/
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setbits32(immap, 0x0c003000);
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/*
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* IMMR + 0x14AC[20:27] = 10101010
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* (data delay for both UCC's)
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*/
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clrsetbits_be32(immap + 4, 0xff0, 0xaa0);
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iounmap(immap);
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}
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iounmap(bcsr_regs);
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of_node_put(np);
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}
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#endif /* CONFIG_QUICC_ENGINE */
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}
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