[PATCH] sata_sil24: separate out sil24_init_controller()
Separate out controller initialization from sil24_init_one() into sil24_init_controller(). This will be used by resume. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
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@ -988,6 +988,64 @@ static void sil24_host_stop(struct ata_host_set *host_set)
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kfree(hpriv);
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kfree(hpriv);
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}
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}
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static void sil24_init_controller(struct pci_dev *pdev, int n_ports,
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unsigned long host_flags,
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void __iomem *host_base,
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void __iomem *port_base)
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{
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u32 tmp;
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int i;
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/* GPIO off */
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writel(0, host_base + HOST_FLASH_CMD);
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/* clear global reset & mask interrupts during initialization */
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writel(0, host_base + HOST_CTRL);
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/* init ports */
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for (i = 0; i < n_ports; i++) {
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void __iomem *port = port_base + i * PORT_REGS_SIZE;
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/* Initial PHY setting */
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writel(0x20c, port + PORT_PHY_CFG);
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/* Clear port RST */
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tmp = readl(port + PORT_CTRL_STAT);
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if (tmp & PORT_CS_PORT_RST) {
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writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
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tmp = ata_wait_register(port + PORT_CTRL_STAT,
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PORT_CS_PORT_RST,
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PORT_CS_PORT_RST, 10, 100);
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if (tmp & PORT_CS_PORT_RST)
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dev_printk(KERN_ERR, &pdev->dev,
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"failed to clear port RST\n");
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}
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/* Configure IRQ WoC */
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if (host_flags & SIL24_FLAG_PCIX_IRQ_WOC)
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writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT);
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else
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writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
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/* Zero error counters. */
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writel(0x8000, port + PORT_DECODE_ERR_THRESH);
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writel(0x8000, port + PORT_CRC_ERR_THRESH);
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writel(0x8000, port + PORT_HSHK_ERR_THRESH);
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writel(0x0000, port + PORT_DECODE_ERR_CNT);
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writel(0x0000, port + PORT_CRC_ERR_CNT);
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writel(0x0000, port + PORT_HSHK_ERR_CNT);
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/* Always use 64bit activation */
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writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
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/* Clear port multiplier enable and resume bits */
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writel(PORT_CS_PM_EN | PORT_CS_RESUME, port + PORT_CTRL_CLR);
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}
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/* Turn on interrupts */
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writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
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}
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static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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{
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{
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static int printed_version = 0;
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static int printed_version = 0;
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@ -1076,9 +1134,6 @@ static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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}
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}
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}
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}
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/* GPIO off */
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writel(0, host_base + HOST_FLASH_CMD);
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/* Apply workaround for completion IRQ loss on PCI-X errata */
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/* Apply workaround for completion IRQ loss on PCI-X errata */
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if (probe_ent->host_flags & SIL24_FLAG_PCIX_IRQ_WOC) {
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if (probe_ent->host_flags & SIL24_FLAG_PCIX_IRQ_WOC) {
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tmp = readl(host_base + HOST_CTRL);
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tmp = readl(host_base + HOST_CTRL);
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@ -1090,56 +1145,18 @@ static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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probe_ent->host_flags &= ~SIL24_FLAG_PCIX_IRQ_WOC;
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probe_ent->host_flags &= ~SIL24_FLAG_PCIX_IRQ_WOC;
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}
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}
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/* clear global reset & mask interrupts during initialization */
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writel(0, host_base + HOST_CTRL);
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for (i = 0; i < probe_ent->n_ports; i++) {
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for (i = 0; i < probe_ent->n_ports; i++) {
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void __iomem *port = port_base + i * PORT_REGS_SIZE;
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unsigned long portu =
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unsigned long portu = (unsigned long)port;
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(unsigned long)port_base + i * PORT_REGS_SIZE;
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probe_ent->port[i].cmd_addr = portu;
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probe_ent->port[i].cmd_addr = portu;
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probe_ent->port[i].scr_addr = portu + PORT_SCONTROL;
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probe_ent->port[i].scr_addr = portu + PORT_SCONTROL;
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ata_std_ports(&probe_ent->port[i]);
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ata_std_ports(&probe_ent->port[i]);
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/* Initial PHY setting */
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writel(0x20c, port + PORT_PHY_CFG);
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/* Clear port RST */
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tmp = readl(port + PORT_CTRL_STAT);
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if (tmp & PORT_CS_PORT_RST) {
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writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
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tmp = ata_wait_register(port + PORT_CTRL_STAT,
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PORT_CS_PORT_RST,
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PORT_CS_PORT_RST, 10, 100);
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if (tmp & PORT_CS_PORT_RST)
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dev_printk(KERN_ERR, &pdev->dev,
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"failed to clear port RST\n");
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}
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/* Configure IRQ WoC */
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if (probe_ent->host_flags & SIL24_FLAG_PCIX_IRQ_WOC)
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writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT);
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else
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writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
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/* Zero error counters. */
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writel(0x8000, port + PORT_DECODE_ERR_THRESH);
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writel(0x8000, port + PORT_CRC_ERR_THRESH);
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writel(0x8000, port + PORT_HSHK_ERR_THRESH);
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writel(0x0000, port + PORT_DECODE_ERR_CNT);
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writel(0x0000, port + PORT_CRC_ERR_CNT);
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writel(0x0000, port + PORT_HSHK_ERR_CNT);
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/* Always use 64bit activation */
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writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
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/* Clear port multiplier enable and resume bits */
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writel(PORT_CS_PM_EN | PORT_CS_RESUME, port + PORT_CTRL_CLR);
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}
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}
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/* Turn on interrupts */
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sil24_init_controller(pdev, probe_ent->n_ports, probe_ent->host_flags,
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writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
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host_base, port_base);
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pci_set_master(pdev);
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pci_set_master(pdev);
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