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perf/x86/intel: Fix regression by default disabling perfmon v4 interrupt handling 

Kyle Huey reported that 'rr', a replay debugger, broke due to the following commit:

  af3bdb991a ("perf/x86/intel: Add a separate Arch Perfmon v4 PMI handler")

Rework the 'disable_counter_freezing' __setup() parameter such that we
can explicitly enable/disable it and switch to default disabled.

To this purpose, rename the parameter to "perf_v4_pmi=" which is a much
better description and allows requiring a bool argument.

[ mingo: Improved the changelog some more. ]

Reported-by: Kyle Huey <me@kylehuey.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Robert O'Callahan <robert@ocallahan.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Cc: acme@kernel.org
Link: http://lkml.kernel.org/r/20181120170842.GZ2131@hirez.programming.kicks-ass.net
Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Peter Zijlstra 2018-11-20 18:08:42 +01:00 committed by Ingo Molnar
parent 9ff01193a2
commit 2a5bf23d5b
2 changed files with 10 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
Documentation/admin-guide/kernel-parameters.txt
View File

@ -856,7 +856,8 @@
causing system reset or hang due to sending causing system reset or hang due to sending
INIT from AP to BSP. INIT from AP to BSP.
disable_counter_freezing [HW] perf_v4_pmi= [X86,INTEL]
Format: <bool>
Disable Intel PMU counter freezing feature. Disable Intel PMU counter freezing feature.
The feature only exists starting from The feature only exists starting from
Arch Perfmon v4 (Skylake and newer). Arch Perfmon v4 (Skylake and newer).

12
arch/x86/events/intel/core.c
View File

@ -2306,14 +2306,18 @@ static int handle_pmi_common(struct pt_regs *regs, u64 status)
return handled; return handled;
} }
static bool disable_counter_freezing; static bool disable_counter_freezing = true;
static int __init intel_perf_counter_freezing_setup(char *s) static int __init intel_perf_counter_freezing_setup(char *s)
{ {
disable_counter_freezing = true; bool res;
pr_info("Intel PMU Counter freezing feature disabled\n");
if (kstrtobool(s, &res))
return -EINVAL;
disable_counter_freezing = !res;
return 1; return 1;
} }
__setup("disable_counter_freezing", intel_perf_counter_freezing_setup); __setup("perf_v4_pmi=", intel_perf_counter_freezing_setup);
/* /*
* Simplified handler for Arch Perfmon v4: * Simplified handler for Arch Perfmon v4: