From 8e2840e06d7da7ae17b1fbc416155a40b22e00ad Mon Sep 17 00:00:00 2001 From: Tejun Heo Date: Wed, 17 Oct 2007 15:24:16 +0900 Subject: [PATCH 1/5] pata_acpi: fix build breakage if !CONFIG_PM There are configurations where CONFIG_ACPI but !CONFIG_PM. In this case, pata_acpi can be selected but won't build. Fix it. Reported by Avuton Olrich. Signed-off-by: Tejun Heo Cc: Avuton Olrich Signed-off-by: Jeff Garzik --- drivers/ata/pata_acpi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/ata/pata_acpi.c b/drivers/ata/pata_acpi.c index 5d3920f6fd69..0f6f7bcc3def 100644 --- a/drivers/ata/pata_acpi.c +++ b/drivers/ata/pata_acpi.c @@ -370,8 +370,10 @@ static struct pci_driver pacpi_pci_driver = { .id_table = pacpi_pci_tbl, .probe = pacpi_init_one, .remove = ata_pci_remove_one, +#ifdef CONFIG_PM .suspend = ata_pci_device_suspend, .resume = ata_pci_device_resume, +#endif }; static int __init pacpi_init(void) From faf0b2e5afe7dae072d2715763c7f992b612b628 Mon Sep 17 00:00:00 2001 From: Li Yang Date: Tue, 16 Oct 2007 20:58:38 +0800 Subject: [PATCH 2/5] drivers/ata: add support to Freescale 3.0Gbps SATA Controller This patch adds support for Freescale 3.0Gbps SATA Controller supporting Native Command Queueing(NCQ), device hotplug, and ATAPI. This controller can be found on MPC8315 and MPC8378. Signed-off-by: Ashish Kalra Signed-off-by: Li Yang Signed-off-by: Jeff Garzik --- drivers/ata/Kconfig | 9 + drivers/ata/Makefile | 1 + drivers/ata/sata_fsl.c | 1490 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 1500 insertions(+) create mode 100644 drivers/ata/sata_fsl.c diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index 33f5eb038773..f4dc0e395976 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig @@ -182,6 +182,15 @@ config PATA_ACPI firmware in the BIOS. This driver can sometimes handle otherwise unsupported hardware. +config SATA_FSL + tristate "Freescale 3.0Gbps SATA support" + depends on PPC_MPC837x + help + This option enables support for Freescale 3.0Gbps SATA controller. + It can be found on MPC837x and MPC8315. + + If unsure, say N. + config PATA_ALI tristate "ALi PATA support (Experimental)" depends on PCI && EXPERIMENTAL diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile index 6bdc307649e6..b13feb2c5dae 100644 --- a/drivers/ata/Makefile +++ b/drivers/ata/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_SATA_ULI) += sata_uli.o obj-$(CONFIG_SATA_MV) += sata_mv.o obj-$(CONFIG_SATA_INIC162X) += sata_inic162x.o obj-$(CONFIG_PDC_ADMA) += pdc_adma.o +obj-$(CONFIG_SATA_FSL) += sata_fsl.o obj-$(CONFIG_PATA_ALI) += pata_ali.o obj-$(CONFIG_PATA_AMD) += pata_amd.o diff --git a/drivers/ata/sata_fsl.c b/drivers/ata/sata_fsl.c new file mode 100644 index 000000000000..b4c37b9e413c --- /dev/null +++ b/drivers/ata/sata_fsl.c @@ -0,0 +1,1490 @@ +/* + * drivers/ata/sata_fsl.c + * + * Freescale 3.0Gbps SATA device driver + * + * Author: Ashish Kalra + * Li Yang + * + * Copyright (c) 2006-2007 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#include +#include +#include + +#include +#include +#include +#include +#include + +/* Controller information */ +enum { + SATA_FSL_QUEUE_DEPTH = 16, + SATA_FSL_MAX_PRD = 63, + SATA_FSL_MAX_PRD_USABLE = SATA_FSL_MAX_PRD - 1, + SATA_FSL_MAX_PRD_DIRECT = 16, /* Direct PRDT entries */ + + SATA_FSL_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | + ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | + ATA_FLAG_NCQ | ATA_FLAG_SKIP_D2H_BSY), + + SATA_FSL_MAX_CMDS = SATA_FSL_QUEUE_DEPTH, + SATA_FSL_CMD_HDR_SIZE = 16, /* 4 DWORDS */ + SATA_FSL_CMD_SLOT_SIZE = (SATA_FSL_MAX_CMDS * SATA_FSL_CMD_HDR_SIZE), + + /* + * SATA-FSL host controller supports a max. of (15+1) direct PRDEs, and + * chained indirect PRDEs upto a max count of 63. + * We are allocating an array of 63 PRDEs contigiously, but PRDE#15 will + * be setup as an indirect descriptor, pointing to it's next + * (contigious) PRDE. Though chained indirect PRDE arrays are + * supported,it will be more efficient to use a direct PRDT and + * a single chain/link to indirect PRDE array/PRDT. + */ + + SATA_FSL_CMD_DESC_CFIS_SZ = 32, + SATA_FSL_CMD_DESC_SFIS_SZ = 32, + SATA_FSL_CMD_DESC_ACMD_SZ = 16, + SATA_FSL_CMD_DESC_RSRVD = 16, + + SATA_FSL_CMD_DESC_SIZE = (SATA_FSL_CMD_DESC_CFIS_SZ + + SATA_FSL_CMD_DESC_SFIS_SZ + + SATA_FSL_CMD_DESC_ACMD_SZ + + SATA_FSL_CMD_DESC_RSRVD + + SATA_FSL_MAX_PRD * 16), + + SATA_FSL_CMD_DESC_OFFSET_TO_PRDT = + (SATA_FSL_CMD_DESC_CFIS_SZ + + SATA_FSL_CMD_DESC_SFIS_SZ + + SATA_FSL_CMD_DESC_ACMD_SZ + + SATA_FSL_CMD_DESC_RSRVD), + + SATA_FSL_CMD_DESC_AR_SZ = (SATA_FSL_CMD_DESC_SIZE * SATA_FSL_MAX_CMDS), + SATA_FSL_PORT_PRIV_DMA_SZ = (SATA_FSL_CMD_SLOT_SIZE + + SATA_FSL_CMD_DESC_AR_SZ), + + /* + * MPC8315 has two SATA controllers, SATA1 & SATA2 + * (one port per controller) + * MPC837x has 2/4 controllers, one port per controller + */ + + SATA_FSL_MAX_PORTS = 1, + + SATA_FSL_IRQ_FLAG = IRQF_SHARED, +}; + +/* +* Host Controller command register set - per port +*/ +enum { + CQ = 0, + CA = 8, + CC = 0x10, + CE = 0x18, + DE = 0x20, + CHBA = 0x24, + HSTATUS = 0x28, + HCONTROL = 0x2C, + CQPMP = 0x30, + SIGNATURE = 0x34, + ICC = 0x38, + + /* + * Host Status Register (HStatus) bitdefs + */ + ONLINE = (1 << 31), + GOING_OFFLINE = (1 << 30), + BIST_ERR = (1 << 29), + + FATAL_ERR_HC_MASTER_ERR = (1 << 18), + FATAL_ERR_PARITY_ERR_TX = (1 << 17), + FATAL_ERR_PARITY_ERR_RX = (1 << 16), + FATAL_ERR_DATA_UNDERRUN = (1 << 13), + FATAL_ERR_DATA_OVERRUN = (1 << 12), + FATAL_ERR_CRC_ERR_TX = (1 << 11), + FATAL_ERR_CRC_ERR_RX = (1 << 10), + FATAL_ERR_FIFO_OVRFL_TX = (1 << 9), + FATAL_ERR_FIFO_OVRFL_RX = (1 << 8), + + FATAL_ERROR_DECODE = FATAL_ERR_HC_MASTER_ERR | + FATAL_ERR_PARITY_ERR_TX | + FATAL_ERR_PARITY_ERR_RX | + FATAL_ERR_DATA_UNDERRUN | + FATAL_ERR_DATA_OVERRUN | + FATAL_ERR_CRC_ERR_TX | + FATAL_ERR_CRC_ERR_RX | + FATAL_ERR_FIFO_OVRFL_TX | FATAL_ERR_FIFO_OVRFL_RX, + + INT_ON_FATAL_ERR = (1 << 5), + INT_ON_PHYRDY_CHG = (1 << 4), + + INT_ON_SIGNATURE_UPDATE = (1 << 3), + INT_ON_SNOTIFY_UPDATE = (1 << 2), + INT_ON_SINGL_DEVICE_ERR = (1 << 1), + INT_ON_CMD_COMPLETE = 1, + + INT_ON_ERROR = INT_ON_FATAL_ERR | + INT_ON_PHYRDY_CHG | INT_ON_SINGL_DEVICE_ERR, + + /* + * Host Control Register (HControl) bitdefs + */ + HCONTROL_ONLINE_PHY_RST = (1 << 31), + HCONTROL_FORCE_OFFLINE = (1 << 30), + HCONTROL_PARITY_PROT_MOD = (1 << 14), + HCONTROL_DPATH_PARITY = (1 << 12), + HCONTROL_SNOOP_ENABLE = (1 << 10), + HCONTROL_PMP_ATTACHED = (1 << 9), + HCONTROL_COPYOUT_STATFIS = (1 << 8), + IE_ON_FATAL_ERR = (1 << 5), + IE_ON_PHYRDY_CHG = (1 << 4), + IE_ON_SIGNATURE_UPDATE = (1 << 3), + IE_ON_SNOTIFY_UPDATE = (1 << 2), + IE_ON_SINGL_DEVICE_ERR = (1 << 1), + IE_ON_CMD_COMPLETE = 1, + + DEFAULT_PORT_IRQ_ENABLE_MASK = IE_ON_FATAL_ERR | IE_ON_PHYRDY_CHG | + IE_ON_SIGNATURE_UPDATE | + IE_ON_SINGL_DEVICE_ERR | IE_ON_CMD_COMPLETE, + + EXT_INDIRECT_SEG_PRD_FLAG = (1 << 31), + DATA_SNOOP_ENABLE = (1 << 22), +}; + +/* + * SATA Superset Registers + */ +enum { + SSTATUS = 0, + SERROR = 4, + SCONTROL = 8, + SNOTIFY = 0xC, +}; + +/* + * Control Status Register Set + */ +enum { + TRANSCFG = 0, + TRANSSTATUS = 4, + LINKCFG = 8, + LINKCFG1 = 0xC, + LINKCFG2 = 0x10, + LINKSTATUS = 0x14, + LINKSTATUS1 = 0x18, + PHYCTRLCFG = 0x1C, + COMMANDSTAT = 0x20, +}; + +/* PHY (link-layer) configuration control */ +enum { + PHY_BIST_ENABLE = 0x01, +}; + +/* + * Command Header Table entry, i.e, command slot + * 4 Dwords per command slot, command header size == 64 Dwords. + */ +struct cmdhdr_tbl_entry { + u32 cda; + u32 prde_fis_len; + u32 ttl; + u32 desc_info; +}; + +/* + * Description information bitdefs + */ +enum { + VENDOR_SPECIFIC_BIST = (1 << 10), + CMD_DESC_SNOOP_ENABLE = (1 << 9), + FPDMA_QUEUED_CMD = (1 << 8), + SRST_CMD = (1 << 7), + BIST = (1 << 6), + ATAPI_CMD = (1 << 5), +}; + +/* + * Command Descriptor + */ +struct command_desc { + u8 cfis[8 * 4]; + u8 sfis[8 * 4]; + u8 acmd[4 * 4]; + u8 fill[4 * 4]; + u32 prdt[SATA_FSL_MAX_PRD_DIRECT * 4]; + u32 prdt_indirect[(SATA_FSL_MAX_PRD - SATA_FSL_MAX_PRD_DIRECT) * 4]; +}; + +/* + * Physical region table descriptor(PRD) + */ + +struct prde { + u32 dba; + u8 fill[2 * 4]; + u32 ddc_and_ext; +}; + +/* + * ata_port private data + * This is our per-port instance data. + */ +struct sata_fsl_port_priv { + struct cmdhdr_tbl_entry *cmdslot; + dma_addr_t cmdslot_paddr; + struct command_desc *cmdentry; + dma_addr_t cmdentry_paddr; + + /* + * SATA FSL controller has a Status FIS which should contain the + * received D2H FIS & taskfile registers. This SFIS is present in + * the command descriptor, and to have a ready reference to it, + * we are caching it here, quite similar to what is done in H/W on + * AHCI compliant devices by copying taskfile fields to a 32-bit + * register. + */ + + struct ata_taskfile tf; +}; + +/* + * ata_port->host_set private data + */ +struct sata_fsl_host_priv { + void __iomem *hcr_base; + void __iomem *ssr_base; + void __iomem *csr_base; +}; + +static inline unsigned int sata_fsl_tag(unsigned int tag, + void __iomem * hcr_base) +{ + /* We let libATA core do actual (queue) tag allocation */ + + /* all non NCQ/queued commands should have tag#0 */ + if (ata_tag_internal(tag)) { + DPRINTK("mapping internal cmds to tag#0\n"); + return 0; + } + + if (unlikely(tag >= SATA_FSL_QUEUE_DEPTH)) { + DPRINTK("tag %d invalid : out of range\n", tag); + return 0; + } + + if (unlikely((ioread32(hcr_base + CQ)) & (1 << tag))) { + DPRINTK("tag %d invalid : in use!!\n", tag); + return 0; + } + + return tag; +} + +static void sata_fsl_setup_cmd_hdr_entry(struct sata_fsl_port_priv *pp, + unsigned int tag, u32 desc_info, + u32 data_xfer_len, u8 num_prde, + u8 fis_len) +{ + dma_addr_t cmd_descriptor_address; + + cmd_descriptor_address = pp->cmdentry_paddr + + tag * SATA_FSL_CMD_DESC_SIZE; + + /* NOTE: both data_xfer_len & fis_len are Dword counts */ + + pp->cmdslot[tag].cda = cpu_to_le32(cmd_descriptor_address); + pp->cmdslot[tag].prde_fis_len = + cpu_to_le32((num_prde << 16) | (fis_len << 2)); + pp->cmdslot[tag].ttl = cpu_to_le32(data_xfer_len & ~0x03); + pp->cmdslot[tag].desc_info = cpu_to_le32((desc_info | (tag & 0x1F))); + + VPRINTK("cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x\n", + pp->cmdslot[tag].cda, + pp->cmdslot[tag].prde_fis_len, + pp->cmdslot[tag].ttl, pp->cmdslot[tag].desc_info); + +} + +static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd *qc, void *cmd_desc, + u32 * ttl, dma_addr_t cmd_desc_paddr) +{ + struct scatterlist *sg; + unsigned int num_prde = 0; + u32 ttl_dwords = 0; + + /* + * NOTE : direct & indirect prdt's are contigiously allocated + */ + struct prde *prd = (struct prde *)&((struct command_desc *) + cmd_desc)->prdt; + + struct prde *prd_ptr_to_indirect_ext = NULL; + unsigned indirect_ext_segment_sz = 0; + dma_addr_t indirect_ext_segment_paddr; + + VPRINTK("SATA FSL : cd = 0x%x, prd = 0x%x\n", cmd_desc, prd); + + indirect_ext_segment_paddr = cmd_desc_paddr + + SATA_FSL_CMD_DESC_OFFSET_TO_PRDT + SATA_FSL_MAX_PRD_DIRECT * 16; + + ata_for_each_sg(sg, qc) { + dma_addr_t sg_addr = sg_dma_address(sg); + u32 sg_len = sg_dma_len(sg); + + VPRINTK("SATA FSL : fill_sg, sg_addr = 0x%x, sg_len = %d\n", + sg_addr, sg_len); + + /* warn if each s/g element is not dword aligned */ + if (sg_addr & 0x03) + ata_port_printk(qc->ap, KERN_ERR, + "s/g addr unaligned : 0x%x\n", sg_addr); + if (sg_len & 0x03) + ata_port_printk(qc->ap, KERN_ERR, + "s/g len unaligned : 0x%x\n", sg_len); + + if ((num_prde == (SATA_FSL_MAX_PRD_DIRECT - 1)) && + !ata_sg_is_last(sg, qc)) { + VPRINTK("setting indirect prde\n"); + prd_ptr_to_indirect_ext = prd; + prd->dba = cpu_to_le32(indirect_ext_segment_paddr); + indirect_ext_segment_sz = 0; + ++prd; + ++num_prde; + } + + ttl_dwords += sg_len; + prd->dba = cpu_to_le32(sg_addr); + prd->ddc_and_ext = + cpu_to_le32(DATA_SNOOP_ENABLE | (sg_len & ~0x03)); + + VPRINTK("sg_fill, ttl=%d, dba=0x%x, ddc=0x%x\n", + ttl_dwords, prd->dba, prd->ddc_and_ext); + + ++num_prde; + ++prd; + if (prd_ptr_to_indirect_ext) + indirect_ext_segment_sz += sg_len; + } + + if (prd_ptr_to_indirect_ext) { + /* set indirect extension flag along with indirect ext. size */ + prd_ptr_to_indirect_ext->ddc_and_ext = + cpu_to_le32((EXT_INDIRECT_SEG_PRD_FLAG | + DATA_SNOOP_ENABLE | + (indirect_ext_segment_sz & ~0x03))); + } + + *ttl = ttl_dwords; + return num_prde; +} + +static void sata_fsl_qc_prep(struct ata_queued_cmd *qc) +{ + struct ata_port *ap = qc->ap; + struct sata_fsl_port_priv *pp = ap->private_data; + struct sata_fsl_host_priv *host_priv = ap->host->private_data; + void __iomem *hcr_base = host_priv->hcr_base; + unsigned int tag = sata_fsl_tag(qc->tag, hcr_base); + struct command_desc *cd; + u32 desc_info = CMD_DESC_SNOOP_ENABLE; + u32 num_prde = 0; + u32 ttl_dwords = 0; + dma_addr_t cd_paddr; + + cd = (struct command_desc *)pp->cmdentry + tag; + cd_paddr = pp->cmdentry_paddr + tag * SATA_FSL_CMD_DESC_SIZE; + + ata_tf_to_fis(&qc->tf, 0, 1, (u8 *) & cd->cfis); + + VPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x\n", + cd->cfis[0], cd->cfis[1], cd->cfis[2]); + + if (qc->tf.protocol == ATA_PROT_NCQ) { + VPRINTK("FPDMA xfer,Sctor cnt[0:7],[8:15] = %d,%d\n", + cd->cfis[3], cd->cfis[11]); + } + + /* setup "ACMD - atapi command" in cmd. desc. if this is ATAPI cmd */ + if (is_atapi_taskfile(&qc->tf)) { + desc_info |= ATAPI_CMD; + memset((void *)&cd->acmd, 0, 32); + memcpy((void *)&cd->acmd, qc->cdb, qc->dev->cdb_len); + } + + if (qc->flags & ATA_QCFLAG_DMAMAP) + num_prde = sata_fsl_fill_sg(qc, (void *)cd, + &ttl_dwords, cd_paddr); + + if (qc->tf.protocol == ATA_PROT_NCQ) + desc_info |= FPDMA_QUEUED_CMD; + + sata_fsl_setup_cmd_hdr_entry(pp, tag, desc_info, ttl_dwords, + num_prde, 5); + + VPRINTK("SATA FSL : xx_qc_prep, di = 0x%x, ttl = %d, num_prde = %d\n", + desc_info, ttl_dwords, num_prde); +} + +static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd *qc) +{ + struct ata_port *ap = qc->ap; + struct sata_fsl_host_priv *host_priv = ap->host->private_data; + void __iomem *hcr_base = host_priv->hcr_base; + unsigned int tag = sata_fsl_tag(qc->tag, hcr_base); + + VPRINTK("xx_qc_issue called,CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n", + ioread32(CQ + hcr_base), + ioread32(CA + hcr_base), + ioread32(CE + hcr_base), ioread32(CC + hcr_base)); + + /* Simply queue command to the controller/device */ + iowrite32(1 << tag, CQ + hcr_base); + + VPRINTK("xx_qc_issue called, tag=%d, CQ=0x%x, CA=0x%x\n", + tag, ioread32(CQ + hcr_base), ioread32(CA + hcr_base)); + + VPRINTK("CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x\n", + ioread32(CE + hcr_base), + ioread32(DE + hcr_base), + ioread32(CC + hcr_base), ioread32(COMMANDSTAT + csr_base)); + + return 0; +} + +static int sata_fsl_scr_write(struct ata_port *ap, unsigned int sc_reg_in, + u32 val) +{ + struct sata_fsl_host_priv *host_priv = ap->host->private_data; + void __iomem *ssr_base = host_priv->ssr_base; + unsigned int sc_reg; + + switch (sc_reg_in) { + case SCR_STATUS: + sc_reg = 0; + break; + case SCR_ERROR: + sc_reg = 1; + break; + case SCR_CONTROL: + sc_reg = 2; + break; + case SCR_ACTIVE: + sc_reg = 3; + break; + default: + return -EINVAL; + } + + VPRINTK("xx_scr_write, reg_in = %d\n", sc_reg); + + iowrite32(val, (void __iomem *)ssr_base + (sc_reg * 4)); + return 0; +} + +static int sata_fsl_scr_read(struct ata_port *ap, unsigned int sc_reg_in, + u32 *val) +{ + struct sata_fsl_host_priv *host_priv = ap->host->private_data; + void __iomem *ssr_base = host_priv->ssr_base; + unsigned int sc_reg; + + switch (sc_reg_in) { + case SCR_STATUS: + sc_reg = 0; + break; + case SCR_ERROR: + sc_reg = 1; + break; + case SCR_CONTROL: + sc_reg = 2; + break; + case SCR_ACTIVE: + sc_reg = 3; + break; + default: + return -EINVAL; + } + + VPRINTK("xx_scr_read, reg_in = %d\n", sc_reg); + + *val = ioread32((void __iomem *)ssr_base + (sc_reg * 4)); + return 0; +} + +static void sata_fsl_freeze(struct ata_port *ap) +{ + struct sata_fsl_host_priv *host_priv = ap->host->private_data; + void __iomem *hcr_base = host_priv->hcr_base; + u32 temp; + + VPRINTK("xx_freeze, CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x\n", + ioread32(CQ + hcr_base), + ioread32(CA + hcr_base), + ioread32(CE + hcr_base), ioread32(DE + hcr_base)); + VPRINTK("CmdStat = 0x%x\n", ioread32(csr_base + COMMANDSTAT)); + + /* disable interrupts on the controller/port */ + temp = ioread32(hcr_base + HCONTROL); + iowrite32((temp & ~0x3F), hcr_base + HCONTROL); + + VPRINTK("in xx_freeze : HControl = 0x%x, HStatus = 0x%x\n", + ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS)); +} + +static void sata_fsl_thaw(struct ata_port *ap) +{ + struct sata_fsl_host_priv *host_priv = ap->host->private_data; + void __iomem *hcr_base = host_priv->hcr_base; + u32 temp; + + /* ack. any pending IRQs for this controller/port */ + temp = ioread32(hcr_base + HSTATUS); + + VPRINTK("xx_thaw, pending IRQs = 0x%x\n", (temp & 0x3F)); + + if (temp & 0x3F) + iowrite32((temp & 0x3F), hcr_base + HSTATUS); + + /* enable interrupts on the controller/port */ + temp = ioread32(hcr_base + HCONTROL); + iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL); + + VPRINTK("xx_thaw : HControl = 0x%x, HStatus = 0x%x\n", + ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS)); +} + +/* + * NOTE : 1st D2H FIS from device does not update sfis in command descriptor. + */ +static inline void sata_fsl_cache_taskfile_from_d2h_fis(struct ata_queued_cmd + *qc, + struct ata_port *ap) +{ + struct sata_fsl_port_priv *pp = ap->private_data; + u8 fis[6 * 4]; + struct sata_fsl_host_priv *host_priv = ap->host->private_data; + void __iomem *hcr_base = host_priv->hcr_base; + unsigned int tag = sata_fsl_tag(qc->tag, hcr_base); + struct command_desc *cd; + + cd = pp->cmdentry + tag; + + memcpy(fis, &cd->sfis, 6 * 4); /* should we use memcpy_from_io() */ + ata_tf_from_fis(fis, &pp->tf); +} + +static u8 sata_fsl_check_status(struct ata_port *ap) +{ + struct sata_fsl_port_priv *pp = ap->private_data; + + return pp->tf.command; +} + +static void sata_fsl_tf_read(struct ata_port *ap, struct ata_taskfile *tf) +{ + struct sata_fsl_port_priv *pp = ap->private_data; + + *tf = pp->tf; +} + +static int sata_fsl_port_start(struct ata_port *ap) +{ + struct device *dev = ap->host->dev; + struct sata_fsl_port_priv *pp; + int retval; + void *mem; + dma_addr_t mem_dma; + struct sata_fsl_host_priv *host_priv = ap->host->private_data; + void __iomem *hcr_base = host_priv->hcr_base; + u32 temp; + + pp = kzalloc(sizeof(*pp), GFP_KERNEL); + if (!pp) + return -ENOMEM; + + /* + * allocate per command dma alignment pad buffer, which is used + * internally by libATA to ensure that all transfers ending on + * unaligned boundaries are padded, to align on Dword boundaries + */ + retval = ata_pad_alloc(ap, dev); + if (retval) { + kfree(pp); + return retval; + } + + mem = dma_alloc_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, &mem_dma, + GFP_KERNEL); + if (!mem) { + ata_pad_free(ap, dev); + kfree(pp); + return -ENOMEM; + } + memset(mem, 0, SATA_FSL_PORT_PRIV_DMA_SZ); + + pp->cmdslot = mem; + pp->cmdslot_paddr = mem_dma; + + mem += SATA_FSL_CMD_SLOT_SIZE; + mem_dma += SATA_FSL_CMD_SLOT_SIZE; + + pp->cmdentry = mem; + pp->cmdentry_paddr = mem_dma; + + ap->private_data = pp; + + VPRINTK("CHBA = 0x%x, cmdentry_phys = 0x%x\n", + pp->cmdslot_paddr, pp->cmdentry_paddr); + + /* Now, update the CHBA register in host controller cmd register set */ + iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA); + + /* + * Now, we can bring the controller on-line & also initiate + * the COMINIT sequence, we simply return here and the boot-probing + * & device discovery process is re-initiated by libATA using a + * Softreset EH (dummy) session. Hence, boot probing and device + * discovey will be part of sata_fsl_softreset() callback. + */ + + temp = ioread32(hcr_base + HCONTROL); + iowrite32((temp | HCONTROL_ONLINE_PHY_RST), hcr_base + HCONTROL); + + VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); + VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); + VPRINTK("CHBA = 0x%x\n", ioread32(hcr_base + CHBA)); + + /* + * Workaround for 8315DS board 3gbps link-up issue, + * currently limit SATA port to GEN1 speed + */ + sata_fsl_scr_read(ap, SCR_CONTROL, &temp); + temp &= ~(0xF << 4); + temp |= (0x1 << 4); + sata_fsl_scr_write(ap, SCR_CONTROL, temp); + + sata_fsl_scr_read(ap, SCR_CONTROL, &temp); + dev_printk(KERN_WARNING, dev, "scr_control, speed limited to %x\n", + temp); + + return 0; +} + +static void sata_fsl_port_stop(struct ata_port *ap) +{ + struct device *dev = ap->host->dev; + struct sata_fsl_port_priv *pp = ap->private_data; + struct sata_fsl_host_priv *host_priv = ap->host->private_data; + void __iomem *hcr_base = host_priv->hcr_base; + u32 temp; + + /* + * Force host controller to go off-line, aborting current operations + */ + temp = ioread32(hcr_base + HCONTROL); + temp &= ~HCONTROL_ONLINE_PHY_RST; + temp |= HCONTROL_FORCE_OFFLINE; + iowrite32(temp, hcr_base + HCONTROL); + + /* Poll for controller to go offline - should happen immediately */ + ata_wait_register(hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1); + + ap->private_data = NULL; + dma_free_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, + pp->cmdslot, pp->cmdslot_paddr); + + ata_pad_free(ap, dev); + kfree(pp); +} + +static unsigned int sata_fsl_dev_classify(struct ata_port *ap) +{ + struct sata_fsl_host_priv *host_priv = ap->host->private_data; + void __iomem *hcr_base = host_priv->hcr_base; + struct ata_taskfile tf; + u32 temp; + + temp = ioread32(hcr_base + SIGNATURE); + + VPRINTK("raw sig = 0x%x\n", temp); + VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); + VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); + + tf.lbah = (temp >> 24) & 0xff; + tf.lbam = (temp >> 16) & 0xff; + tf.lbal = (temp >> 8) & 0xff; + tf.nsect = temp & 0xff; + + return ata_dev_classify(&tf); +} + +static int sata_fsl_softreset(struct ata_port *ap, unsigned int *class, + unsigned long deadline) +{ + struct sata_fsl_port_priv *pp = ap->private_data; + struct sata_fsl_host_priv *host_priv = ap->host->private_data; + void __iomem *hcr_base = host_priv->hcr_base; + u32 temp; + struct ata_taskfile tf; + u8 *cfis; + u32 Serror; + int i = 0; + struct ata_queued_cmd qc; + u8 *buf; + dma_addr_t dma_address; + struct scatterlist *sg; + unsigned long start_jiffies; + + DPRINTK("in xx_softreset\n"); + +try_offline_again: + /* + * Force host controller to go off-line, aborting current operations + */ + temp = ioread32(hcr_base + HCONTROL); + temp &= ~HCONTROL_ONLINE_PHY_RST; + iowrite32(temp, hcr_base + HCONTROL); + + /* Poll for controller to go offline */ + temp = ata_wait_register(hcr_base + HSTATUS, ONLINE, ONLINE, 1, 500); + + if (temp & ONLINE) { + ata_port_printk(ap, KERN_ERR, + "Softreset failed, not off-lined %d\n", i); + + /* + * Try to offline controller atleast twice + */ + i++; + if (i == 2) + goto err; + else + goto try_offline_again; + } + + DPRINTK("softreset, controller off-lined\n"); + VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); + VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); + + /* + * PHY reset should remain asserted for atleast 1ms + */ + msleep(1); + + /* + * Now, bring the host controller online again, this can take time + * as PHY reset and communication establishment, 1st D2H FIS and + * device signature update is done, on safe side assume 500ms + * NOTE : Host online status may be indicated immediately!! + */ + + temp = ioread32(hcr_base + HCONTROL); + temp |= (HCONTROL_ONLINE_PHY_RST | HCONTROL_SNOOP_ENABLE); + iowrite32(temp, hcr_base + HCONTROL); + + temp = ata_wait_register(hcr_base + HSTATUS, ONLINE, 0, 1, 500); + + if (!(temp & ONLINE)) { + ata_port_printk(ap, KERN_ERR, + "Softreset failed, not on-lined\n"); + goto err; + } + + DPRINTK("softreset, controller off-lined & on-lined\n"); + VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); + VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); + + /* + * First, wait for the PHYRDY change to occur before waiting for + * the signature, and also verify if SStatus indicates device + * presence + */ + + temp = ata_wait_register(hcr_base + HSTATUS, 0xFF, 0, 1, 500); + if ((!(temp & 0x10)) || ata_port_offline(ap)) { + ata_port_printk(ap, KERN_WARNING, + "No Device OR PHYRDY change,Hstatus = 0x%x\n", + ioread32(hcr_base + HSTATUS)); + goto err; + } + + /* + * Wait for the first D2H from device,i.e,signature update notification + */ + start_jiffies = jiffies; + temp = ata_wait_register(hcr_base + HSTATUS, 0xFF, 0x10, + 500, jiffies_to_msecs(deadline - start_jiffies)); + + if ((temp & 0xFF) != 0x18) { + ata_port_printk(ap, KERN_WARNING, "No Signature Update\n"); + goto err; + } else { + ata_port_printk(ap, KERN_INFO, + "Signature Update detected @ %d msecs\n", + jiffies_to_msecs(jiffies - start_jiffies)); + } + + /* + * Send a device reset (SRST) explicitly on command slot #0 + * Check : will the command queue (reg) be cleared during offlining ?? + * Also we will be online only if Phy commn. has been established + * and device presence has been detected, therefore if we have + * reached here, we can send a command to the target device + */ + + if (ap->sactive) + goto skip_srst_do_ncq_error_handling; + + DPRINTK("Sending SRST/device reset\n"); + + ata_tf_init(ap->device, &tf); + cfis = (u8 *) & pp->cmdentry->cfis; + + /* device reset/SRST is a control register update FIS, uses tag0 */ + sata_fsl_setup_cmd_hdr_entry(pp, 0, + SRST_CMD | CMD_DESC_SNOOP_ENABLE, 0, 0, 5); + + tf.ctl |= ATA_SRST; /* setup SRST bit in taskfile control reg */ + ata_tf_to_fis(&tf, 0, 0, cfis); + + DPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x\n", + cfis[0], cfis[1], cfis[2], cfis[3]); + + /* + * Queue SRST command to the controller/device, ensure that no + * other commands are active on the controller/device + */ + + DPRINTK("@Softreset, CQ = 0x%x, CA = 0x%x, CC = 0x%x\n", + ioread32(CQ + hcr_base), + ioread32(CA + hcr_base), ioread32(CC + hcr_base)); + + iowrite32(0xFFFF, CC + hcr_base); + iowrite32(1, CQ + hcr_base); + + temp = ata_wait_register(CQ + hcr_base, 0x1, 0x1, 1, 5000); + if (temp & 0x1) { + ata_port_printk(ap, KERN_WARNING, "ATA_SRST issue failed\n"); + + DPRINTK("Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n", + ioread32(CQ + hcr_base), + ioread32(CA + hcr_base), ioread32(CC + hcr_base)); + + sata_fsl_scr_read(ap, SCR_ERROR, &Serror); + + DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); + DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); + DPRINTK("Serror = 0x%x\n", Serror); + goto err; + } + + msleep(1); + + /* + * SATA device enters reset state after receving a Control register + * FIS with SRST bit asserted and it awaits another H2D Control reg. + * FIS with SRST bit cleared, then the device does internal diags & + * initialization, followed by indicating it's initialization status + * using ATA signature D2H register FIS to the host controller. + */ + + sata_fsl_setup_cmd_hdr_entry(pp, 0, CMD_DESC_SNOOP_ENABLE, 0, 0, 5); + + tf.ctl &= ~ATA_SRST; /* 2nd H2D Ctl. register FIS */ + ata_tf_to_fis(&tf, 0, 0, cfis); + + iowrite32(1, CQ + hcr_base); + msleep(150); /* ?? */ + + /* + * The above command would have signalled an interrupt on command + * complete, which needs special handling, by clearing the Nth + * command bit of the CCreg + */ + iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */ + goto check_device_signature; + +skip_srst_do_ncq_error_handling: + + VPRINTK("Sending read log ext(10h) command\n"); + + memset(&qc, 0, sizeof(struct ata_queued_cmd)); + ata_tf_init(ap->device, &tf); + + tf.command = ATA_CMD_READ_LOG_EXT; + tf.lbal = ATA_LOG_SATA_NCQ; + tf.nsect = 1; + tf.hob_nsect = 0; + tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_LBA48 | ATA_TFLAG_DEVICE; + tf.protocol = ATA_PROT_PIO; + + qc.tag = ATA_TAG_INTERNAL; + qc.scsicmd = NULL; + qc.ap = ap; + qc.dev = ap->device; + + qc.tf = tf; + qc.flags |= ATA_QCFLAG_RESULT_TF; + qc.dma_dir = DMA_FROM_DEVICE; + + buf = ap->sector_buf; + ata_sg_init_one(&qc, buf, 1 * ATA_SECT_SIZE); + + /* + * Need to DMA-map the memory buffer associated with the command + */ + + sg = qc.__sg; + dma_address = dma_map_single(ap->dev, qc.buf_virt, + sg->length, DMA_FROM_DEVICE); + + sg_dma_address(sg) = dma_address; + sg_dma_len(sg) = sg->length; + + VPRINTK("EH, addr = 0x%x, len = 0x%x\n", dma_address, sg->length); + + sata_fsl_qc_prep(&qc); + sata_fsl_qc_issue(&qc); + + temp = ata_wait_register(CQ + hcr_base, 0x1, 0x1, 1, 5000); + if (temp & 0x1) { + VPRINTK("READ_LOG_EXT_10H issue failed\n"); + + VPRINTK("READ_LOG@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n", + ioread32(CQ + hcr_base), + ioread32(CA + hcr_base), ioread32(CC + hcr_base)); + + sata_fsl_scr_read(ap, SCR_ERROR, &Serror); + + VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); + VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); + VPRINTK("Serror = 0x%x\n", Serror); + goto err; + } + + iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */ + + check_device_signature: + + DPRINTK("SATA FSL : Now checking device signature\n"); + + *class = ATA_DEV_NONE; + + /* Verify if SStatus indicates device presence */ + if (ata_port_online(ap)) { + /* + * if we are here, device presence has been detected, + * 1st D2H FIS would have been received, but sfis in + * command desc. is not updated, but signature register + * would have been updated + */ + + *class = sata_fsl_dev_classify(ap); + + DPRINTK("class = %d\n", *class); + VPRINTK("ccreg = 0x%x\n", ioread32(hcr_base + CC)); + VPRINTK("cereg = 0x%x\n", ioread32(hcr_base + CE)); + } + + return 0; + +err: + return -EIO; +} + +static int sata_fsl_hardreset(struct ata_port *ap, unsigned int *class, + unsigned long deadline) +{ + int retval; + + retval = sata_std_hardreset(ap, class, deadline); + + DPRINTK("SATA FSL : in xx_hardreset, retval = 0x%d\n", retval); + + return retval; +} + +static void sata_fsl_error_handler(struct ata_port *ap) +{ + + DPRINTK("in xx_error_handler\n"); + + /* perform recovery */ + ata_do_eh(ap, ata_std_prereset, sata_fsl_softreset, sata_fsl_hardreset, + ata_std_postreset); +} + +static void sata_fsl_post_internal_cmd(struct ata_queued_cmd *qc) +{ + if (qc->flags & ATA_QCFLAG_FAILED) + qc->err_mask |= AC_ERR_OTHER; + + if (qc->err_mask) { + /* make DMA engine forget about the failed command */ + + } +} + +static void sata_fsl_irq_clear(struct ata_port *ap) +{ + /* unused */ +} + +static void sata_fsl_error_intr(struct ata_port *ap) +{ + struct ata_eh_info *ehi = &ap->eh_info; + struct sata_fsl_host_priv *host_priv = ap->host->private_data; + void __iomem *hcr_base = host_priv->hcr_base; + u32 hstatus, dereg, cereg = 0, SError = 0; + unsigned int err_mask = 0, action = 0; + struct ata_queued_cmd *qc; + int freeze = 0; + + hstatus = ioread32(hcr_base + HSTATUS); + cereg = ioread32(hcr_base + CE); + + ata_ehi_clear_desc(ehi); + + /* + * Handle & Clear SError + */ + + sata_fsl_scr_read(ap, SCR_ERROR, &SError); + if (unlikely(SError & 0xFFFF0000)) { + sata_fsl_scr_write(ap, SCR_ERROR, SError); + err_mask |= AC_ERR_ATA_BUS; + } + + DPRINTK("error_intr,hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n", + hstatus, cereg, ioread32(hcr_base + DE), SError); + + /* handle single device errors */ + if (cereg) { + /* + * clear the command error, also clears queue to the device + * in error, and we can (re)issue commands to this device. + * When a device is in error all commands queued into the + * host controller and at the device are considered aborted + * and the queue for that device is stopped. Now, after + * clearing the device error, we can issue commands to the + * device to interrogate it to find the source of the error. + */ + dereg = ioread32(hcr_base + DE); + iowrite32(dereg, hcr_base + DE); + iowrite32(cereg, hcr_base + CE); + + DPRINTK("single device error, CE=0x%x, DE=0x%x\n", + ioread32(hcr_base + CE), ioread32(hcr_base + DE)); + /* + * We should consider this as non fatal error, and TF must + * be updated as done below. + */ + + err_mask |= AC_ERR_DEV; + } + + /* handle fatal errors */ + if (hstatus & FATAL_ERROR_DECODE) { + err_mask |= AC_ERR_ATA_BUS; + action |= ATA_EH_SOFTRESET; + /* how will fatal error interrupts be completed ?? */ + freeze = 1; + } + + /* Handle PHYRDY change notification */ + if (hstatus & INT_ON_PHYRDY_CHG) { + DPRINTK("SATA FSL: PHYRDY change indication\n"); + + /* Setup a soft-reset EH action */ + ata_ehi_hotplugged(ehi); + freeze = 1; + } + + /* record error info */ + qc = ata_qc_from_tag(ap, ap->active_tag); + + if (qc) { + sata_fsl_cache_taskfile_from_d2h_fis(qc, qc->ap); + qc->err_mask |= err_mask; + } else + ehi->err_mask |= err_mask; + + ehi->action |= action; + ehi->serror |= SError; + + /* freeze or abort */ + if (freeze) + ata_port_freeze(ap); + else + ata_port_abort(ap); +} + +static void sata_fsl_qc_complete(struct ata_queued_cmd *qc) +{ + if (qc->flags & ATA_QCFLAG_RESULT_TF) { + DPRINTK("xx_qc_complete called\n"); + sata_fsl_cache_taskfile_from_d2h_fis(qc, qc->ap); + } +} + +static void sata_fsl_host_intr(struct ata_port *ap) +{ + struct sata_fsl_host_priv *host_priv = ap->host->private_data; + void __iomem *hcr_base = host_priv->hcr_base; + u32 hstatus, qc_active = 0; + struct ata_queued_cmd *qc; + u32 SError; + + hstatus = ioread32(hcr_base + HSTATUS); + + sata_fsl_scr_read(ap, SCR_ERROR, &SError); + + if (unlikely(SError & 0xFFFF0000)) { + DPRINTK("serror @host_intr : 0x%x\n", SError); + sata_fsl_error_intr(ap); + + } + + if (unlikely(hstatus & INT_ON_ERROR)) { + DPRINTK("error interrupt!!\n"); + sata_fsl_error_intr(ap); + return; + } + + if (ap->sactive) { /* only true for NCQ commands */ + int i; + /* Read command completed register */ + qc_active = ioread32(hcr_base + CC); + /* clear CC bit, this will also complete the interrupt */ + iowrite32(qc_active, hcr_base + CC); + + DPRINTK("Status of all queues :\n"); + DPRINTK("qc_active/CC = 0x%x, CA = 0x%x, CE=0x%x\n", + qc_active, ioread32(hcr_base + CA), + ioread32(hcr_base + CE)); + + for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) { + if (qc_active & (1 << i)) { + qc = ata_qc_from_tag(ap, i); + if (qc) { + sata_fsl_qc_complete(qc); + ata_qc_complete(qc); + } + DPRINTK + ("completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x\n", + i, ioread32(hcr_base + CC), + ioread32(hcr_base + CA)); + } + } + return; + + } else if (ap->qc_active) { + iowrite32(1, hcr_base + CC); + qc = ata_qc_from_tag(ap, ap->active_tag); + + DPRINTK("completing non-ncq cmd, tag=%d,CC=0x%x\n", + ap->active_tag, ioread32(hcr_base + CC)); + + if (qc) { + sata_fsl_qc_complete(qc); + ata_qc_complete(qc); + } + } else { + /* Spurious Interrupt!! */ + DPRINTK("spurious interrupt!!, CC = 0x%x\n", + ioread32(hcr_base + CC)); + return; + } +} + +static irqreturn_t sata_fsl_interrupt(int irq, void *dev_instance) +{ + struct ata_host *host = dev_instance; + struct sata_fsl_host_priv *host_priv = host->private_data; + void __iomem *hcr_base = host_priv->hcr_base; + u32 interrupt_enables; + unsigned handled = 0; + struct ata_port *ap; + + /* ack. any pending IRQs for this controller/port */ + interrupt_enables = ioread32(hcr_base + HSTATUS); + interrupt_enables &= 0x3F; + + DPRINTK("interrupt status 0x%x\n", interrupt_enables); + + if (!interrupt_enables) + return IRQ_NONE; + + spin_lock(&host->lock); + + /* Assuming one port per host controller */ + + ap = host->ports[0]; + if (ap) { + sata_fsl_host_intr(ap); + } else { + dev_printk(KERN_WARNING, host->dev, + "interrupt on disabled port 0\n"); + } + + iowrite32(interrupt_enables, hcr_base + HSTATUS); + handled = 1; + + spin_unlock(&host->lock); + + return IRQ_RETVAL(handled); +} + +/* + * Multiple ports are represented by multiple SATA controllers with + * one port per controller + */ +static int sata_fsl_init_controller(struct ata_host *host) +{ + struct sata_fsl_host_priv *host_priv = host->private_data; + void __iomem *hcr_base = host_priv->hcr_base; + u32 temp; + + /* + * NOTE : We cannot bring the controller online before setting + * the CHBA, hence main controller initialization is done as + * part of the port_start() callback + */ + + /* ack. any pending IRQs for this controller/port */ + temp = ioread32(hcr_base + HSTATUS); + if (temp & 0x3F) + iowrite32((temp & 0x3F), hcr_base + HSTATUS); + + /* Keep interrupts disabled on the controller */ + temp = ioread32(hcr_base + HCONTROL); + iowrite32((temp & ~0x3F), hcr_base + HCONTROL); + + /* Disable interrupt coalescing control(icc), for the moment */ + DPRINTK("icc = 0x%x\n", ioread32(hcr_base + ICC)); + iowrite32(0x01000000, hcr_base + ICC); + + /* clear error registers, SError is cleared by libATA */ + iowrite32(0x00000FFFF, hcr_base + CE); + iowrite32(0x00000FFFF, hcr_base + DE); + + /* initially assuming no Port multiplier, set CQPMP to 0 */ + iowrite32(0x0, hcr_base + CQPMP); + + /* + * host controller will be brought on-line, during xx_port_start() + * callback, that should also initiate the OOB, COMINIT sequence + */ + + DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); + DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); + + return 0; +} + +/* + * scsi mid-layer and libata interface structures + */ +static struct scsi_host_template sata_fsl_sht = { + .module = THIS_MODULE, + .name = "sata_fsl", + .ioctl = ata_scsi_ioctl, + .queuecommand = ata_scsi_queuecmd, + .change_queue_depth = ata_scsi_change_queue_depth, + .can_queue = SATA_FSL_QUEUE_DEPTH, + .this_id = ATA_SHT_THIS_ID, + .sg_tablesize = SATA_FSL_MAX_PRD_USABLE, + .cmd_per_lun = ATA_SHT_CMD_PER_LUN, + .emulated = ATA_SHT_EMULATED, + .use_clustering = ATA_SHT_USE_CLUSTERING, + .proc_name = "sata_fsl", + .dma_boundary = ATA_DMA_BOUNDARY, + .slave_configure = ata_scsi_slave_config, + .slave_destroy = ata_scsi_slave_destroy, + .bios_param = ata_std_bios_param, +#ifdef CONFIG_PM + .suspend = ata_scsi_device_suspend, + .resume = ata_scsi_device_resume, +#endif +}; + +static const struct ata_port_operations sata_fsl_ops = { + .port_disable = ata_port_disable, + + .check_status = sata_fsl_check_status, + .check_altstatus = sata_fsl_check_status, + .dev_select = ata_noop_dev_select, + + .tf_read = sata_fsl_tf_read, + + .qc_prep = sata_fsl_qc_prep, + .qc_issue = sata_fsl_qc_issue, + .irq_clear = sata_fsl_irq_clear, + .irq_on = ata_dummy_irq_on, + .irq_ack = ata_dummy_irq_ack, + + .scr_read = sata_fsl_scr_read, + .scr_write = sata_fsl_scr_write, + + .freeze = sata_fsl_freeze, + .thaw = sata_fsl_thaw, + .error_handler = sata_fsl_error_handler, + .post_internal_cmd = sata_fsl_post_internal_cmd, + + .port_start = sata_fsl_port_start, + .port_stop = sata_fsl_port_stop, +}; + +static const struct ata_port_info sata_fsl_port_info[] = { + { + .flags = SATA_FSL_HOST_FLAGS, + .pio_mask = 0x1f, /* pio 0-4 */ + .udma_mask = 0x7f, /* udma 0-6 */ + .port_ops = &sata_fsl_ops, + }, +}; + +static int sata_fsl_probe(struct of_device *ofdev, + const struct of_device_id *match) +{ + int retval = 0; + void __iomem *hcr_base = NULL; + void __iomem *ssr_base = NULL; + void __iomem *csr_base = NULL; + struct sata_fsl_host_priv *host_priv = NULL; + struct resource *r; + int irq; + struct ata_host *host; + + struct ata_port_info pi = sata_fsl_port_info[0]; + const struct ata_port_info *ppi[] = { &pi, NULL }; + + dev_printk(KERN_INFO, &ofdev->dev, + "Sata FSL Platform/CSB Driver init\n"); + + r = kmalloc(sizeof(struct resource), GFP_KERNEL); + + hcr_base = of_iomap(ofdev->node, 0); + if (!hcr_base) + goto error_exit_with_cleanup; + + ssr_base = hcr_base + 0x100; + csr_base = hcr_base + 0x140; + + DPRINTK("@reset i/o = 0x%x\n", ioread32(csr_base + TRANSCFG)); + DPRINTK("sizeof(cmd_desc) = %d\n", sizeof(struct command_desc)); + DPRINTK("sizeof(#define cmd_desc) = %d\n", SATA_FSL_CMD_DESC_SIZE); + + host_priv = kzalloc(sizeof(struct sata_fsl_host_priv), GFP_KERNEL); + if (!host_priv) + goto error_exit_with_cleanup; + + host_priv->hcr_base = hcr_base; + host_priv->ssr_base = ssr_base; + host_priv->csr_base = csr_base; + + irq = irq_of_parse_and_map(ofdev->node, 0); + if (irq < 0) { + dev_printk(KERN_ERR, &ofdev->dev, "invalid irq from platform\n"); + goto error_exit_with_cleanup; + } + + /* allocate host structure */ + host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_FSL_MAX_PORTS); + + /* host->iomap is not used currently */ + host->private_data = host_priv; + + /* setup port(s) */ + + host->ports[0]->ioaddr.cmd_addr = host_priv->hcr_base; + host->ports[0]->ioaddr.scr_addr = host_priv->ssr_base; + + /* initialize host controller */ + sata_fsl_init_controller(host); + + /* + * Now, register with libATA core, this will also initiate the + * device discovery process, invoking our port_start() handler & + * error_handler() to execute a dummy Softreset EH session + */ + ata_host_activate(host, irq, sata_fsl_interrupt, SATA_FSL_IRQ_FLAG, + &sata_fsl_sht); + + dev_set_drvdata(&ofdev->dev, host); + + return 0; + +error_exit_with_cleanup: + + if (hcr_base) + iounmap(hcr_base); + if (host_priv) + kfree(host_priv); + + return retval; +} + +static int sata_fsl_remove(struct of_device *ofdev) +{ + struct ata_host *host = dev_get_drvdata(&ofdev->dev); + struct sata_fsl_host_priv *host_priv = host->private_data; + + ata_host_detach(host); + + dev_set_drvdata(&ofdev->dev, NULL); + + irq_dispose_mapping(host->irq); + iounmap(host_priv->hcr_base); + kfree(host_priv); + + return 0; +} + +static struct of_device_id fsl_sata_match[] = { + { + .compatible = "fsl,mpc8315-sata", + }, + { + .compatible = "fsl,mpc8379-sata", + }, + {}, +}; + +MODULE_DEVICE_TABLE(of, fsl_sata_match); + +static struct of_platform_driver fsl_sata_driver = { + .name = "fsl-sata", + .match_table = fsl_sata_match, + .probe = sata_fsl_probe, + .remove = sata_fsl_remove, +}; + +static int __init sata_fsl_init(void) +{ + of_register_platform_driver(&fsl_sata_driver); + return 0; +} + +static void __exit sata_fsl_exit(void) +{ + of_unregister_platform_driver(&fsl_sata_driver); +} + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Ashish Kalra, Freescale Semiconductor"); +MODULE_DESCRIPTION("Freescale 3.0Gbps SATA controller low level driver"); +MODULE_VERSION("1.10"); + +module_init(sata_fsl_init); +module_exit(sata_fsl_exit); From 01839f6ddef011878e905d72786d95cee21ca039 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 15 Oct 2007 19:25:29 +0100 Subject: [PATCH 3/5] libata-sff: Correct use of check_status() ata_check_status() does an SFF compliant check ata_chk_status() does a generic call to ap->ops->check_status (usually ata_check_status) libata-sff uses the wrong one. Hardly suprising given the naming here, which ought to get fixed to ata_sff_check_status() perhaps ? Signed-off-by: Alan Cox Signed-off-by: Jeff Garzik --- drivers/ata/libata-sff.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ata/libata-sff.c b/drivers/ata/libata-sff.c index 026439e05afe..1232dcb6008d 100644 --- a/drivers/ata/libata-sff.c +++ b/drivers/ata/libata-sff.c @@ -156,7 +156,7 @@ void ata_tf_read(struct ata_port *ap, struct ata_taskfile *tf) { struct ata_ioports *ioaddr = &ap->ioaddr; - tf->command = ata_check_status(ap); + tf->command = ata_chk_status(ap); tf->feature = ioread8(ioaddr->error_addr); tf->nsect = ioread8(ioaddr->nsect_addr); tf->lbal = ioread8(ioaddr->lbal_addr); From 858c9c406688bc7244986b5836265071edfd1d3f Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Tue, 16 Oct 2007 16:43:27 +0800 Subject: [PATCH 4/5] Update libata driver for bf548 atapi controller against the 2.6.24 tree. Changes: 1. Remove irq_ack() and port_disable() methods 2. Acocomodate for the libata-link patches 3. Change Kconfig ATAPI mode option into a module param. 4. Add supported WMDMA mode. Signed-off-by: Sonic Zhang Signed-off-by: Jeff Garzik --- drivers/ata/Kconfig | 7 ---- drivers/ata/pata_bf54x.c | 77 +++++++++++++++++++--------------------- 2 files changed, 37 insertions(+), 47 deletions(-) diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index f4dc0e395976..ba63619ae5df 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig @@ -650,11 +650,4 @@ config PATA_BF54X If unsure, say N. -config PATA_BF54X_DMA - bool "DMA mode" - depends on PATA_BF54X - default y - help - Enable DMA mode for Blackfin ATAPI controller. - endif # ATA diff --git a/drivers/ata/pata_bf54x.c b/drivers/ata/pata_bf54x.c index 747549e4563a..b5e38426b815 100644 --- a/drivers/ata/pata_bf54x.c +++ b/drivers/ata/pata_bf54x.c @@ -1092,14 +1092,15 @@ static unsigned int bfin_bus_softreset(struct ata_port *ap, * Note: Original code is ata_std_softreset(). */ -static int bfin_std_softreset(struct ata_port *ap, unsigned int *classes, +static int bfin_std_softreset(struct ata_link *link, unsigned int *classes, unsigned long deadline) { + struct ata_port *ap = link->ap; unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS; unsigned int devmask = 0, err_mask; u8 err; - if (ata_port_offline(ap)) { + if (ata_link_offline(link)) { classes[0] = ATA_DEV_NONE; goto out; } @@ -1122,9 +1123,11 @@ static int bfin_std_softreset(struct ata_port *ap, unsigned int *classes, } /* determine by signature whether we have ATA or ATAPI devices */ - classes[0] = ata_dev_try_classify(ap, 0, &err); + classes[0] = ata_dev_try_classify(&ap->link.device[0], + devmask & (1 << 0), &err); if (slave_possible && err != 0x81) - classes[1] = ata_dev_try_classify(ap, 1, &err); + classes[1] = ata_dev_try_classify(&ap->link.device[1], + devmask & (1 << 1), &err); out: return 0; @@ -1167,7 +1170,7 @@ static unsigned char bfin_bmdma_status(struct ata_port *ap) static void bfin_data_xfer(struct ata_device *adev, unsigned char *buf, unsigned int buflen, int write_data) { - struct ata_port *ap = adev->ap; + struct ata_port *ap = adev->link->ap; unsigned int words = buflen >> 1; unsigned short *buf16 = (u16 *) buf; void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; @@ -1206,7 +1209,10 @@ static void bfin_irq_clear(struct ata_port *ap) void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; pr_debug("in atapi irq clear\n"); - ATAPI_SET_INT_STATUS(base, 0x1FF); + + ATAPI_SET_INT_STATUS(base, ATAPI_GET_INT_STATUS(base)|ATAPI_DEV_INT + | MULTI_DONE_INT | UDMAIN_DONE_INT | UDMAOUT_DONE_INT + | MULTI_TERM_INT | UDMAIN_TERM_INT | UDMAOUT_TERM_INT); } /** @@ -1233,33 +1239,6 @@ static unsigned char bfin_irq_on(struct ata_port *ap) return tmp; } -/** - * bfin_irq_ack - Acknowledge a device interrupt. - * @ap: Port on which interrupts are enabled. - * - * Note: Original code is ata_irq_ack(). - */ - -static unsigned char bfin_irq_ack(struct ata_port *ap, unsigned int chk_drq) -{ - void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; - unsigned int bits = chk_drq ? ATA_BUSY | ATA_DRQ : ATA_BUSY; - unsigned char status; - - pr_debug("in atapi irq ack\n"); - status = ata_busy_wait(ap, bits, 1000); - if (status & bits) - if (ata_msg_err(ap)) - dev_err(ap->dev, "abnormal status 0x%X\n", status); - - /* get controller status; clear intr, err bits */ - ATAPI_SET_INT_STATUS(base, ATAPI_GET_INT_STATUS(base)|ATAPI_DEV_INT - | MULTI_DONE_INT | UDMAIN_DONE_INT | UDMAOUT_DONE_INT - | MULTI_TERM_INT | UDMAIN_TERM_INT | UDMAOUT_TERM_INT); - - return bfin_bmdma_status(ap); -} - /** * bfin_bmdma_freeze - Freeze DMA controller port * @ap: port to freeze @@ -1308,8 +1287,9 @@ void bfin_bmdma_thaw(struct ata_port *ap) * Note: Original code is ata_std_postreset(). */ -static void bfin_std_postreset(struct ata_port *ap, unsigned int *classes) +static void bfin_std_postreset(struct ata_link *link, unsigned int *classes) { + struct ata_port *ap = link->ap; void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; /* re-enable interrupts */ @@ -1395,7 +1375,6 @@ static struct scsi_host_template bfin_sht = { }; static const struct ata_port_operations bfin_pata_ops = { - .port_disable = ata_port_disable, .set_piomode = bfin_set_piomode, .set_dmamode = bfin_set_dmamode, @@ -1423,7 +1402,6 @@ static const struct ata_port_operations bfin_pata_ops = { .irq_handler = ata_interrupt, .irq_clear = bfin_irq_clear, .irq_on = bfin_irq_on, - .irq_ack = bfin_irq_ack, .port_start = bfin_port_start, .port_stop = bfin_port_stop, @@ -1437,11 +1415,7 @@ static struct ata_port_info bfin_port_info[] = { | ATA_FLAG_NO_LEGACY, .pio_mask = 0x1f, /* pio0-4 */ .mwdma_mask = 0, -#ifdef CONFIG_PATA_BF54X_DMA - .udma_mask = ATA_UDMA5, -#else .udma_mask = 0, -#endif .port_ops = &bfin_pata_ops, }, }; @@ -1607,9 +1581,25 @@ static struct platform_driver bfin_atapi_driver = { }, }; +#define ATAPI_MODE_SIZE 10 +static char bfin_atapi_mode[ATAPI_MODE_SIZE]; + static int __init bfin_atapi_init(void) { pr_info("register bfin atapi driver\n"); + + switch(bfin_atapi_mode[0]) { + case 'p': + case 'P': + break; + case 'm': + case 'M': + bfin_port_info[0].mwdma_mask = ATA_MWDMA2; + break; + default: + bfin_port_info[0].udma_mask = ATA_UDMA5; + }; + return platform_driver_register(&bfin_atapi_driver); } @@ -1620,6 +1610,13 @@ static void __exit bfin_atapi_exit(void) module_init(bfin_atapi_init); module_exit(bfin_atapi_exit); +/* + * ATAPI mode: + * pio/PIO + * udma/UDMA (default) + * mwdma/MWDMA + */ +module_param_string(bfin_atapi_mode, bfin_atapi_mode, ATAPI_MODE_SIZE, 0); MODULE_AUTHOR("Sonic Zhang "); MODULE_DESCRIPTION("PATA driver for blackfin 54x ATAPI controller"); From 3be6cbd73f74b4a3da82cc7d6e1688a4ae595fc7 Mon Sep 17 00:00:00 2001 From: Jeff Garzik Date: Thu, 18 Oct 2007 16:21:18 -0400 Subject: [PATCH 5/5] [libata] kill ata_sg_is_last() Short term, this works around a bug introduced by early sg-chaining work. Long term, removing this function eliminates a branch from a hot path loop in each scatter/gather table build. Also, as this code demonstrates, we don't need to _track_ the end of the s/g list, as long as we mark it in some way. And doing so programatically is nice. So its a useful cleanup, regardless of its short term effects. Based conceptually on a quick patch by Jens Axboe. Signed-off-by: Jeff Garzik --- drivers/ata/pdc_adma.c | 9 ++++++--- drivers/ata/sata_mv.c | 26 +++++++------------------- drivers/ata/sata_sil24.c | 11 +++++++---- drivers/scsi/ipr.c | 11 +++++++---- include/linux/libata.h | 12 ------------ 5 files changed, 27 insertions(+), 42 deletions(-) diff --git a/drivers/ata/pdc_adma.c b/drivers/ata/pdc_adma.c index 8d1b03d5bcb1..199f7e150eb3 100644 --- a/drivers/ata/pdc_adma.c +++ b/drivers/ata/pdc_adma.c @@ -318,7 +318,7 @@ static int adma_fill_sg(struct ata_queued_cmd *qc) struct scatterlist *sg; struct ata_port *ap = qc->ap; struct adma_port_priv *pp = ap->private_data; - u8 *buf = pp->pkt; + u8 *buf = pp->pkt, *last_buf = NULL; int i = (2 + buf[3]) * 8; u8 pFLAGS = pORD | ((qc->tf.flags & ATA_TFLAG_WRITE) ? pDIRO : 0); @@ -334,8 +334,7 @@ static int adma_fill_sg(struct ata_queued_cmd *qc) *(__le32 *)(buf + i) = cpu_to_le32(len); i += 4; - if (ata_sg_is_last(sg, qc)) - pFLAGS |= pEND; + last_buf = &buf[i]; buf[i++] = pFLAGS; buf[i++] = qc->dev->dma_mode & 0xf; buf[i++] = 0; /* pPKLW */ @@ -348,6 +347,10 @@ static int adma_fill_sg(struct ata_queued_cmd *qc) VPRINTK("PRD[%u] = (0x%lX, 0x%X)\n", i/4, (unsigned long)addr, len); } + + if (likely(last_buf)) + *last_buf |= pEND; + return i; } diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c index 4df8311968e9..7f1b13e89cf7 100644 --- a/drivers/ata/sata_mv.c +++ b/drivers/ata/sata_mv.c @@ -421,7 +421,6 @@ static void mv_error_handler(struct ata_port *ap); static void mv_post_int_cmd(struct ata_queued_cmd *qc); static void mv_eh_freeze(struct ata_port *ap); static void mv_eh_thaw(struct ata_port *ap); -static int mv_slave_config(struct scsi_device *sdev); static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, @@ -459,7 +458,7 @@ static struct scsi_host_template mv5_sht = { .use_clustering = 1, .proc_name = DRV_NAME, .dma_boundary = MV_DMA_BOUNDARY, - .slave_configure = mv_slave_config, + .slave_configure = ata_scsi_slave_config, .slave_destroy = ata_scsi_slave_destroy, .bios_param = ata_std_bios_param, }; @@ -477,7 +476,7 @@ static struct scsi_host_template mv6_sht = { .use_clustering = 1, .proc_name = DRV_NAME, .dma_boundary = MV_DMA_BOUNDARY, - .slave_configure = mv_slave_config, + .slave_configure = ata_scsi_slave_config, .slave_destroy = ata_scsi_slave_destroy, .bios_param = ata_std_bios_param, }; @@ -756,17 +755,6 @@ static void mv_irq_clear(struct ata_port *ap) { } -static int mv_slave_config(struct scsi_device *sdev) -{ - int rc = ata_scsi_slave_config(sdev); - if (rc) - return rc; - - blk_queue_max_phys_segments(sdev->request_queue, MV_MAX_SG_CT / 2); - - return 0; /* scsi layer doesn't check return value, sigh */ -} - static void mv_set_edma_ptrs(void __iomem *port_mmio, struct mv_host_priv *hpriv, struct mv_port_priv *pp) @@ -1138,7 +1126,7 @@ static void mv_fill_sg(struct ata_queued_cmd *qc) { struct mv_port_priv *pp = qc->ap->private_data; struct scatterlist *sg; - struct mv_sg *mv_sg; + struct mv_sg *mv_sg, *last_sg = NULL; mv_sg = pp->sg_tbl; ata_for_each_sg(sg, qc) { @@ -1159,13 +1147,13 @@ static void mv_fill_sg(struct ata_queued_cmd *qc) sg_len -= len; addr += len; - if (!sg_len && ata_sg_is_last(sg, qc)) - mv_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL); - + last_sg = mv_sg; mv_sg++; } - } + + if (likely(last_sg)) + last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL); } static inline void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last) diff --git a/drivers/ata/sata_sil24.c b/drivers/ata/sata_sil24.c index b0619278454a..26ebffc10f3e 100644 --- a/drivers/ata/sata_sil24.c +++ b/drivers/ata/sata_sil24.c @@ -796,16 +796,19 @@ static inline void sil24_fill_sg(struct ata_queued_cmd *qc, struct sil24_sge *sge) { struct scatterlist *sg; + struct sil24_sge *last_sge = NULL; ata_for_each_sg(sg, qc) { sge->addr = cpu_to_le64(sg_dma_address(sg)); sge->cnt = cpu_to_le32(sg_dma_len(sg)); - if (ata_sg_is_last(sg, qc)) - sge->flags = cpu_to_le32(SGE_TRM); - else - sge->flags = 0; + sge->flags = 0; + + last_sge = sge; sge++; } + + if (likely(last_sge)) + last_sge->flags = cpu_to_le32(SGE_TRM); } static int sil24_qc_defer(struct ata_queued_cmd *qc) diff --git a/drivers/scsi/ipr.c b/drivers/scsi/ipr.c index b41dfb539021..c316a0bcae6c 100644 --- a/drivers/scsi/ipr.c +++ b/drivers/scsi/ipr.c @@ -5134,6 +5134,7 @@ static void ipr_build_ata_ioadl(struct ipr_cmnd *ipr_cmd, u32 ioadl_flags = 0; struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb; struct ipr_ioadl_desc *ioadl = ipr_cmd->ioadl; + struct ipr_ioadl_desc *last_ioadl = NULL; int len = qc->nbytes + qc->pad_len; struct scatterlist *sg; @@ -5156,11 +5157,13 @@ static void ipr_build_ata_ioadl(struct ipr_cmnd *ipr_cmd, ata_for_each_sg(sg, qc) { ioadl->flags_and_data_len = cpu_to_be32(ioadl_flags | sg_dma_len(sg)); ioadl->address = cpu_to_be32(sg_dma_address(sg)); - if (ata_sg_is_last(sg, qc)) - ioadl->flags_and_data_len |= cpu_to_be32(IPR_IOADL_FLAGS_LAST); - else - ioadl++; + + last_ioadl = ioadl; + ioadl++; } + + if (likely(last_ioadl)) + last_ioadl->flags_and_data_len |= cpu_to_be32(IPR_IOADL_FLAGS_LAST); } /** diff --git a/include/linux/libata.h b/include/linux/libata.h index 377e6d4d9be3..bc3b6fc7b98d 100644 --- a/include/linux/libata.h +++ b/include/linux/libata.h @@ -1037,18 +1037,6 @@ extern void ata_port_pbar_desc(struct ata_port *ap, int bar, ssize_t offset, /* * qc helpers */ -static inline int -ata_sg_is_last(struct scatterlist *sg, struct ata_queued_cmd *qc) -{ - if (sg == &qc->pad_sgent) - return 1; - if (qc->pad_len) - return 0; - if (qc->n_iter == qc->n_elem) - return 1; - return 0; -} - static inline struct scatterlist * ata_qc_first_sg(struct ata_queued_cmd *qc) {