RISC-V: Remove CLINT related code from timer and arch
Right now the RISC-V timer driver is convoluted to support: 1. Linux RISC-V S-mode (with MMU) where it will use TIME CSR for clocksource and SBI timer calls for clockevent device. 2. Linux RISC-V M-mode (without MMU) where it will use CLINT MMIO counter register for clocksource and CLINT MMIO compare register for clockevent device. We now have a separate CLINT timer driver which also provide CLINT based IPI operations so let's remove CLINT MMIO related code from arch/riscv directory and RISC-V timer driver. Signed-off-by: Anup Patel <anup.patel@wdc.com> Tested-by: Emil Renner Berhing <kernel@esmil.dk> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
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@ -81,7 +81,7 @@ config RISCV
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select PCI_DOMAINS_GENERIC if PCI
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select PCI_MSI if PCI
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select RISCV_INTC
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select RISCV_TIMER
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select RISCV_TIMER if RISCV_SBI
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select SPARSEMEM_STATIC if 32BIT
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select SPARSE_IRQ
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select SYSCTL_EXCEPTION_TRACE
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@ -12,6 +12,7 @@ config SOC_SIFIVE
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config SOC_VIRT
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bool "QEMU Virt Machine"
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select CLINT_TIMER if RISCV_M_MODE
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select POWER_RESET
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select POWER_RESET_SYSCON
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select POWER_RESET_SYSCON_POWEROFF
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@ -24,6 +25,7 @@ config SOC_VIRT
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config SOC_KENDRYTE
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bool "Kendryte K210 SoC"
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depends on !MMU
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select CLINT_TIMER if RISCV_M_MODE
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select SERIAL_SIFIVE if TTY
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select SERIAL_SIFIVE_CONSOLE if TTY
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select SIFIVE_PLIC
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@ -26,6 +26,7 @@ CONFIG_EXPERT=y
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CONFIG_SLOB=y
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# CONFIG_SLAB_MERGE_DEFAULT is not set
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# CONFIG_MMU is not set
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CONFIG_SOC_VIRT=y
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CONFIG_MAXPHYSMEM_2GB=y
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CONFIG_SMP=y
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CONFIG_CMDLINE="root=/dev/vda rw earlycon=uart8250,mmio,0x10000000,115200n8 console=ttyS0"
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@ -49,7 +50,6 @@ CONFIG_VIRTIO_BLK=y
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# CONFIG_SERIO is not set
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# CONFIG_LEGACY_PTYS is not set
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# CONFIG_LDISC_AUTOLOAD is not set
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# CONFIG_DEVMEM is not set
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CONFIG_SERIAL_8250=y
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# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
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CONFIG_SERIAL_8250_CONSOLE=y
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@ -57,16 +57,13 @@ CONFIG_SERIAL_8250_NR_UARTS=1
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CONFIG_SERIAL_8250_RUNTIME_UARTS=1
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CONFIG_SERIAL_OF_PLATFORM=y
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# CONFIG_HW_RANDOM is not set
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# CONFIG_DEVMEM is not set
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# CONFIG_HWMON is not set
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# CONFIG_LCD_CLASS_DEVICE is not set
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# CONFIG_BACKLIGHT_CLASS_DEVICE is not set
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# CONFIG_VGA_CONSOLE is not set
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# CONFIG_HID is not set
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# CONFIG_USB_SUPPORT is not set
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CONFIG_VIRTIO_MMIO=y
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CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y
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CONFIG_SIFIVE_PLIC=y
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# CONFIG_VALIDATE_FS_PARSER is not set
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CONFIG_EXT2_FS=y
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# CONFIG_DNOTIFY is not set
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# CONFIG_INOTIFY_USER is not set
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@ -1,14 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_RISCV_CLINT_H
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#define _ASM_RISCV_CLINT_H 1
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#include <linux/io.h>
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#include <linux/smp.h>
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#ifdef CONFIG_RISCV_M_MODE
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void clint_init_boot_cpu(void);
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#else /* CONFIG_RISCV_M_MODE */
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#define clint_init_boot_cpu() do { } while (0)
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#endif /* CONFIG_RISCV_M_MODE */
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#endif /* _ASM_RISCV_CLINT_H */
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@ -7,41 +7,27 @@
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#define _ASM_RISCV_TIMEX_H
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#include <asm/csr.h>
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#include <asm/mmio.h>
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typedef unsigned long cycles_t;
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extern u64 __iomem *riscv_time_val;
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extern u64 __iomem *riscv_time_cmp;
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#ifdef CONFIG_64BIT
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#define mmio_get_cycles() readq_relaxed(riscv_time_val)
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#else
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#define mmio_get_cycles() readl_relaxed(riscv_time_val)
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#define mmio_get_cycles_hi() readl_relaxed(((u32 *)riscv_time_val) + 1)
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#endif
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static inline cycles_t get_cycles(void)
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{
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if (IS_ENABLED(CONFIG_RISCV_SBI))
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return csr_read(CSR_TIME);
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return mmio_get_cycles();
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return csr_read(CSR_TIME);
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}
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#define get_cycles get_cycles
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static inline u32 get_cycles_hi(void)
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{
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return csr_read(CSR_TIMEH);
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}
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#define get_cycles_hi get_cycles_hi
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#ifdef CONFIG_64BIT
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static inline u64 get_cycles64(void)
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{
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return get_cycles();
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}
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#else /* CONFIG_64BIT */
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static inline u32 get_cycles_hi(void)
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{
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if (IS_ENABLED(CONFIG_RISCV_SBI))
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return csr_read(CSR_TIMEH);
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return mmio_get_cycles_hi();
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}
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static inline u64 get_cycles64(void)
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{
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u32 hi, lo;
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@ -31,7 +31,7 @@ obj-y += cacheinfo.o
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obj-y += patch.o
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obj-$(CONFIG_MMU) += vdso.o vdso/
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obj-$(CONFIG_RISCV_M_MODE) += clint.o traps_misaligned.o
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obj-$(CONFIG_RISCV_M_MODE) += traps_misaligned.o
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obj-$(CONFIG_FPU) += fpu.o
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obj-$(CONFIG_SMP) += smpboot.o
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obj-$(CONFIG_SMP) += smp.o
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@ -1,63 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 Christoph Hellwig.
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*/
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#include <linux/io.h>
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#include <linux/of_address.h>
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#include <linux/smp.h>
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#include <linux/types.h>
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#include <asm/clint.h>
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#include <asm/csr.h>
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#include <asm/timex.h>
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/*
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* This is the layout used by the SiFive clint, which is also shared by the qemu
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* virt platform, and the Kendryte KD210 at least.
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*/
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#define CLINT_IPI_OFF 0
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#define CLINT_TIME_CMP_OFF 0x4000
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#define CLINT_TIME_VAL_OFF 0xbff8
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u32 __iomem *clint_ipi_base;
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static void clint_send_ipi(const struct cpumask *target)
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{
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unsigned int cpu;
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for_each_cpu(cpu, target)
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writel(1, clint_ipi_base + cpuid_to_hartid_map(cpu));
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}
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static void clint_clear_ipi(void)
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{
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writel(0, clint_ipi_base + cpuid_to_hartid_map(smp_processor_id()));
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}
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static struct riscv_ipi_ops clint_ipi_ops = {
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.ipi_inject = clint_send_ipi,
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.ipi_clear = clint_clear_ipi,
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};
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void clint_init_boot_cpu(void)
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{
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struct device_node *np;
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void __iomem *base;
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np = of_find_compatible_node(NULL, NULL, "riscv,clint0");
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if (!np) {
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panic("clint not found");
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return;
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}
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base = of_iomap(np, 0);
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if (!base)
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panic("could not map CLINT");
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clint_ipi_base = base + CLINT_IPI_OFF;
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riscv_time_cmp = base + CLINT_TIME_CMP_OFF;
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riscv_time_val = base + CLINT_TIME_VAL_OFF;
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clint_clear_ipi();
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riscv_set_ipi_ops(&clint_ipi_ops);
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}
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@ -18,7 +18,6 @@
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#include <linux/swiotlb.h>
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#include <linux/smp.h>
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#include <asm/clint.h>
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#include <asm/cpu_ops.h>
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#include <asm/setup.h>
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#include <asm/sections.h>
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@ -79,7 +78,6 @@ void __init setup_arch(char **cmdline_p)
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#else
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unflatten_device_tree();
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#endif
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clint_init_boot_cpu();
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#ifdef CONFIG_SWIOTLB
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swiotlb_init(1);
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@ -18,7 +18,6 @@
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#include <linux/delay.h>
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#include <linux/irq_work.h>
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#include <asm/clint.h>
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#include <asm/sbi.h>
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#include <asm/tlbflush.h>
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#include <asm/cacheflush.h>
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@ -24,7 +24,6 @@
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#include <linux/of.h>
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#include <linux/sched/task_stack.h>
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#include <linux/sched/mm.h>
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#include <asm/clint.h>
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#include <asm/cpu_ops.h>
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#include <asm/irq.h>
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#include <asm/mmu_context.h>
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@ -653,9 +653,8 @@ config ATCPIT100_TIMER
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This option enables support for the Andestech ATCPIT100 timers.
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config RISCV_TIMER
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bool "Timer for the RISC-V platform"
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bool "Timer for the RISC-V platform" if COMPILE_TEST
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depends on GENERIC_SCHED_CLOCK && RISCV
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default y
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select TIMER_PROBE
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select TIMER_OF
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help
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@ -19,26 +19,13 @@
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#include <linux/of_irq.h>
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#include <asm/smp.h>
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#include <asm/sbi.h>
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u64 __iomem *riscv_time_cmp;
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u64 __iomem *riscv_time_val;
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static inline void mmio_set_timer(u64 val)
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{
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void __iomem *r;
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r = riscv_time_cmp + cpuid_to_hartid_map(smp_processor_id());
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writeq_relaxed(val, r);
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}
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#include <asm/timex.h>
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static int riscv_clock_next_event(unsigned long delta,
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struct clock_event_device *ce)
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{
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csr_set(CSR_IE, IE_TIE);
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if (IS_ENABLED(CONFIG_RISCV_SBI))
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sbi_set_timer(get_cycles64() + delta);
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else
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mmio_set_timer(get_cycles64() + delta);
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sbi_set_timer(get_cycles64() + delta);
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return 0;
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}
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