dts: socfpga: general updates for the socfpga platform
Mostly DTS additions to the SOCFPGA platform from Steffan Trumtrar, and a couple of device tree documentation updates/typo fix. This one does not the GPIO binding patch, as that is pending further discussion. Also, v3 fixes a rebase artifact and compile tested. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJTaFnlAAoJEBmUBAuBoyj06AEP/2mrqDlhxSalLTB2GM8dzwsK 6eVTeP1LTGmfV+qmMez5zW83z/+1tw8Ime3Z46mdvr4ORu1vynz8RQ//jb5d5366 JBms9E68vRHbmJXS3PJ9u9VegaKePKePV7NuoA6G9WtlAItPdLTrYLyuBIIiSwJP XLBPz33xUdeJBoMRGI44C4pOiL/icsOC12jmH5M61CzxrhhMX6I8qEJnF2hC6mhk S5fnGmt649pKR4sgfLrk4DE2yzemy6qfb+dSXw1K1HrnOlZDKUmhtj18dQNIVpQX K3b1kxrlIxOe1/m5pBadk8cBiKeJEJO65iNvWnimAw+x7KGRcDKaiZLSsuGG1rKH W54rbJrY4XOFssHq4IRiJ6YO5mIPpJw6pgCrWSdHKg4Shni0muymdBkZmB4Rvxm6 uWXon8X0tMEZjaJ5jjZaNYNxIiRkxtOo0+x6WwXyBy/x6aIZtSh8r4wNlPS85AFQ f7hNBslQ5YhatvuqJj8b1VIG6cMtAqOwUOk/xx64VmBMf/zkXZk1PE8pbnvCzBkd 22yLb/JWYBE+rA+kQ78o8Aj8cwrajezOkEm0G2WV26ie2gG6Qmd8W/hqm83/1TFV 9SyaomV3KXKjBf/KJGr9vYf/t293Kvw9zDpx8PfOM4BKiuuwZ3zoHQ+CkknBvzYX ckvge60rWGdynGiAFJ3f =4CDi -----END PGP SIGNATURE----- Merge tag 'socfpga-dt-updates-for-3.16_v3' of git://git.rocketboards.org/linux-socfpga-next into next/dt Merge "dts: socfpga: general updates for the socfpga platform" from Dinh Nguyen: Mostly DTS additions to the SOCFPGA platform from Steffan Trumtrar, and a couple of device tree documentation updates/typo fix. This one does not the GPIO binding patch, as that is pending further discussion. Also, v3 fixes a rebase artifact and compile tested. * tag 'socfpga-dt-updates-for-3.16_v3' of git://git.rocketboards.org/linux-socfpga-next: ARM: socfpga: dts: Add div-reg to the main_pll clocks ARM: socfpga: dts: add reset-controller Documentation: dt: reset: move socfpga-reset Documentation: dt: socfpga: add reset-cells property ARM: socfpga: dts: Add DTS entries for USB ARM: socfpga: dts: Remove hard coded clock-frequency property ARM: socfpga: dts: add eeprom and rtc on i2c0 ARM: socfpga: dts: convert to preprocessor includes ARM: socfpga: dts: add rtc on i2c0 to socrates ARM: socfpga: dts: add support for EBV SOCrates ARM: socfpga: dts: add can0+1 ARM: socfpga: dts: add i2c busses ARM: socfpga: dts: add remaining interrupts for pdma ARM: socfpga: dts: fix pdma interrupt Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
2bfac3a551
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@ -21,8 +21,8 @@ Optional properties:
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- fixed-divider : If clocks have a fixed divider value, use this property.
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- clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register
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and the bit index.
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- div-reg : For "socfpga-gate-clk", div-reg contains the divider register, bit shift,
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and width.
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- div-reg : For "socfpga-gate-clk" and "socfpga-periph-clock", div-reg contains
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the divider register, bit shift, and width.
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- clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls
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the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the second
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value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct
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@ -3,9 +3,11 @@ Altera SOCFPGA Reset Manager
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Required properties:
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- compatible : "altr,rst-mgr"
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- reg : Should contain 1 register ranges(address and length)
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- #reset-cells: 1
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Example:
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rstmgr@ffd05000 {
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#reset-cells = <1>;
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compatible = "altr,rst-mgr";
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reg = <0xffd05000 0x1000>;
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};
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@ -321,6 +321,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \
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dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \
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socfpga_cyclone5_socdk.dtb \
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socfpga_cyclone5_sockit.dtb \
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socfpga_cyclone5_socrates.dtb \
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socfpga_vt.dtb
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dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \
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spear1340-evb.dtb
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@ -15,7 +15,8 @@
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/include/ "skeleton.dtsi"
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#include "skeleton.dtsi"
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#include <dt-bindings/reset/altr,rst-mgr.h>
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/ {
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#address-cells = <1>;
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@ -75,7 +76,14 @@
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pdma: pdma@ffe01000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0xffe01000 0x1000>;
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interrupts = <0 180 4>;
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interrupts = <0 104 4>,
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<0 105 4>,
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<0 106 4>,
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<0 107 4>,
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<0 108 4>,
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<0 109 4>,
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<0 110 4>,
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<0 111 4>;
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#dma-cells = <1>;
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#dma-channels = <8>;
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#dma-requests = <32>;
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@ -84,6 +92,22 @@
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};
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};
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can0: can@ffc00000 {
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compatible = "bosch,d_can";
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reg = <0xffc00000 0x1000>;
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interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
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clocks = <&can0_clk>;
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status = "disabled";
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};
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can1: can@ffc01000 {
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compatible = "bosch,d_can";
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reg = <0xffc01000 0x1000>;
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interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
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clocks = <&can1_clk>;
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status = "disabled";
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};
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clkmgr@ffd04000 {
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compatible = "altr,clk-mgr";
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reg = <0xffd04000 0x1000>;
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@ -124,7 +148,7 @@
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&main_pll>;
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fixed-divider = <2>;
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div-reg = <0xe0 0 9>;
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reg = <0x48>;
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};
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@ -132,7 +156,7 @@
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&main_pll>;
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fixed-divider = <4>;
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div-reg = <0xe4 0 9>;
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reg = <0x4C>;
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};
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@ -140,7 +164,7 @@
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&main_pll>;
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fixed-divider = <4>;
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div-reg = <0xe8 0 9>;
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reg = <0x50>;
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};
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@ -460,6 +484,8 @@
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mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
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clocks = <&emac0_clk>;
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clock-names = "stmmaceth";
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resets = <&rst EMAC0_RESET>;
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reset-names = "stmmaceth";
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status = "disabled";
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};
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@ -472,6 +498,48 @@
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mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
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clocks = <&emac1_clk>;
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clock-names = "stmmaceth";
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resets = <&rst EMAC1_RESET>;
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reset-names = "stmmaceth";
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status = "disabled";
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};
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i2c0: i2c@ffc04000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,designware-i2c";
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reg = <0xffc04000 0x1000>;
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clocks = <&l4_sp_clk>;
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interrupts = <0 158 0x4>;
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status = "disabled";
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};
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i2c1: i2c@ffc05000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,designware-i2c";
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reg = <0xffc05000 0x1000>;
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clocks = <&l4_sp_clk>;
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interrupts = <0 159 0x4>;
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status = "disabled";
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};
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i2c2: i2c@ffc06000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,designware-i2c";
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reg = <0xffc06000 0x1000>;
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clocks = <&l4_sp_clk>;
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interrupts = <0 160 0x4>;
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status = "disabled";
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};
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i2c3: i2c@ffc07000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,designware-i2c";
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reg = <0xffc07000 0x1000>;
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clocks = <&l4_sp_clk>;
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interrupts = <0 161 0x4>;
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status = "disabled";
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};
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@ -508,24 +576,32 @@
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compatible = "snps,dw-apb-timer";
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interrupts = <0 167 4>;
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reg = <0xffc08000 0x1000>;
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clocks = <&l4_sp_clk>;
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clock-names = "timer";
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};
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timer1: timer1@ffc09000 {
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compatible = "snps,dw-apb-timer";
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interrupts = <0 168 4>;
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reg = <0xffc09000 0x1000>;
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clocks = <&l4_sp_clk>;
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clock-names = "timer";
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};
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timer2: timer2@ffd00000 {
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compatible = "snps,dw-apb-timer";
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interrupts = <0 169 4>;
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reg = <0xffd00000 0x1000>;
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clocks = <&osc1>;
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clock-names = "timer";
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};
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timer3: timer3@ffd01000 {
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compatible = "snps,dw-apb-timer";
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interrupts = <0 170 4>;
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reg = <0xffd01000 0x1000>;
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clocks = <&osc1>;
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clock-names = "timer";
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};
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uart0: serial0@ffc02000 {
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@ -534,6 +610,7 @@
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interrupts = <0 162 4>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&l4_sp_clk>;
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};
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uart1: serial1@ffc03000 {
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@ -542,13 +619,42 @@
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interrupts = <0 163 4>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&l4_sp_clk>;
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};
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rstmgr@ffd05000 {
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rst: rstmgr@ffd05000 {
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compatible = "altr,rst-mgr";
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reg = <0xffd05000 0x1000>;
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};
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usbphy0: usbphy@0 {
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#phy-cells = <0>;
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compatible = "usb-nop-xceiv";
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status = "okay";
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};
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usb0: usb@ffb00000 {
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compatible = "snps,dwc2";
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reg = <0xffb00000 0xffff>;
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interrupts = <0 125 4>;
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clocks = <&usb_mp_clk>;
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clock-names = "otg";
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phys = <&usbphy0>;
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phy-names = "usb2-phy";
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status = "disabled";
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};
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usb1: usb@ffb40000 {
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compatible = "snps,dwc2";
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reg = <0xffb40000 0xffff>;
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interrupts = <0 128 4>;
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clocks = <&usb_mp_clk>;
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clock-names = "otg";
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phys = <&usbphy0>;
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phy-names = "usb2-phy";
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status = "disabled";
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};
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sysmgr: sysmgr@ffd08000 {
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compatible = "altr,sys-mgr", "syscon";
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reg = <0xffd08000 0x4000>;
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@ -15,7 +15,7 @@
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*/
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/dts-v1/;
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/include/ "socfpga.dtsi"
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#include "socfpga.dtsi"
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/ {
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soc {
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@ -38,32 +38,8 @@
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};
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};
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serial0@ffc02000 {
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clock-frequency = <100000000>;
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};
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serial1@ffc03000 {
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clock-frequency = <100000000>;
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};
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sysmgr@ffd08000 {
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cpu1-start-addr = <0xffd080c4>;
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};
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timer0@ffc08000 {
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clock-frequency = <100000000>;
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};
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timer1@ffc09000 {
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clock-frequency = <100000000>;
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};
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timer2@ffd00000 {
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clock-frequency = <25000000>;
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};
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timer3@ffd01000 {
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clock-frequency = <25000000>;
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};
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};
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};
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@ -15,7 +15,7 @@
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/include/ "socfpga_arria5.dtsi"
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#include "socfpga_arria5.dtsi"
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/ {
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model = "Altera SOCFPGA Arria V SoC Development Kit";
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@ -59,3 +59,22 @@
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rxdv-skew-ps = <0>;
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rxc-skew-ps = <2000>;
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};
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&i2c0 {
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status = "okay";
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eeprom@51 {
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compatible = "atmel,24c32";
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reg = <0x51>;
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pagesize = <32>;
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};
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rtc@68 {
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compatible = "dallas,ds1339";
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reg = <0x68>;
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};
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};
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&usb1 {
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status = "okay";
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};
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@ -16,7 +16,7 @@
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*/
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/dts-v1/;
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/include/ "socfpga.dtsi"
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#include "socfpga.dtsi"
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/ {
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soc {
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@ -45,30 +45,6 @@
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status = "okay";
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};
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timer0@ffc08000 {
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clock-frequency = <100000000>;
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};
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timer1@ffc09000 {
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clock-frequency = <100000000>;
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};
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timer2@ffd00000 {
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clock-frequency = <25000000>;
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};
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timer3@ffd01000 {
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clock-frequency = <25000000>;
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};
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serial0@ffc02000 {
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clock-frequency = <100000000>;
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};
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serial1@ffc03000 {
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clock-frequency = <100000000>;
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};
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sysmgr@ffd08000 {
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cpu1-start-addr = <0xffd080c4>;
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};
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|
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|
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@ -15,7 +15,7 @@
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
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/include/ "socfpga_cyclone5.dtsi"
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#include "socfpga_cyclone5.dtsi"
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/ {
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model = "Altera SOCFPGA Cyclone V SoC Development Kit";
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@ -52,3 +52,22 @@
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rxdv-skew-ps = <0>;
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rxc-skew-ps = <2000>;
|
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};
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&i2c0 {
|
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status = "okay";
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|
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eeprom@51 {
|
||||
compatible = "atmel,24c32";
|
||||
reg = <0x51>;
|
||||
pagesize = <32>;
|
||||
};
|
||||
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds1339";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -15,7 +15,7 @@
|
|||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/include/ "socfpga_cyclone5.dtsi"
|
||||
#include "socfpga_cyclone5.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Terasic SoCkit";
|
||||
|
|
@ -52,3 +52,7 @@
|
|||
rxdv-skew-ps = <0>;
|
||||
rxc-skew-ps = <2000>;
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,50 @@
|
|||
/*
|
||||
* Copyright (C) 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include "socfpga_cyclone5.dtsi"
|
||||
|
||||
/ {
|
||||
model = "EBV SOCrates";
|
||||
compatible = "ebv,socrates", "altr,socfpga-cyclone5", "altr,socfpga";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200";
|
||||
};
|
||||
|
||||
memory {
|
||||
name = "memory";
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x40000000>; /* 1GB */
|
||||
};
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
rtc: rtc@68 {
|
||||
compatible = "stm,m41t82";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
&mmc {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -16,7 +16,7 @@
|
|||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "socfpga.dtsi"
|
||||
#include "socfpga.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Altera SOCFPGA VT";
|
||||
|
|
|
|||
|
|
@ -0,0 +1,90 @@
|
|||
/*
|
||||
* Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de>
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_H
|
||||
#define _DT_BINDINGS_RESET_ALTR_RST_MGR_H
|
||||
|
||||
/* MPUMODRST */
|
||||
#define CPU0_RESET 0
|
||||
#define CPU1_RESET 1
|
||||
#define WDS_RESET 2
|
||||
#define SCUPER_RESET 3
|
||||
#define L2_RESET 4
|
||||
|
||||
/* PERMODRST */
|
||||
#define EMAC0_RESET 32
|
||||
#define EMAC1_RESET 33
|
||||
#define USB0_RESET 34
|
||||
#define USB1_RESET 35
|
||||
#define NAND_RESET 36
|
||||
#define QSPI_RESET 37
|
||||
#define L4WD0_RESET 38
|
||||
#define L4WD1_RESET 39
|
||||
#define OSC1TIMER0_RESET 40
|
||||
#define OSC1TIMER1_RESET 41
|
||||
#define SPTIMER0_RESET 42
|
||||
#define SPTIMER1_RESET 43
|
||||
#define I2C0_RESET 44
|
||||
#define I2C1_RESET 45
|
||||
#define I2C2_RESET 46
|
||||
#define I2C3_RESET 47
|
||||
#define UART0_RESET 48
|
||||
#define UART1_RESET 49
|
||||
#define SPIM0_RESET 50
|
||||
#define SPIM1_RESET 51
|
||||
#define SPIS0_RESET 52
|
||||
#define SPIS1_RESET 53
|
||||
#define SDMMC_RESET 54
|
||||
#define CAN0_RESET 55
|
||||
#define CAN1_RESET 56
|
||||
#define GPIO0_RESET 57
|
||||
#define GPIO1_RESET 58
|
||||
#define GPIO2_RESET 59
|
||||
#define DMA_RESET 60
|
||||
#define SDR_RESET 61
|
||||
|
||||
/* PER2MODRST */
|
||||
#define DMAIF0_RESET 64
|
||||
#define DMAIF1_RESET 65
|
||||
#define DMAIF2_RESET 66
|
||||
#define DMAIF3_RESET 67
|
||||
#define DMAIF4_RESET 68
|
||||
#define DMAIF5_RESET 69
|
||||
#define DMAIF6_RESET 70
|
||||
#define DMAIF7_RESET 71
|
||||
|
||||
/* BRGMODRST */
|
||||
#define HPS2FPGA_RESET 96
|
||||
#define LWHPS2FPGA_RESET 97
|
||||
#define FPGA2HPS_RESET 98
|
||||
|
||||
/* MISCMODRST*/
|
||||
#define ROM_RESET 128
|
||||
#define OCRAM_RESET 129
|
||||
#define SYSMGR_RESET 130
|
||||
#define SYSMGRCOLD_RESET 131
|
||||
#define FPGAMGR_RESET 132
|
||||
#define ACPIDMAP_RESET 133
|
||||
#define S2F_RESET 134
|
||||
#define S2FCOLD_RESET 135
|
||||
#define NRSTPIN_RESET 136
|
||||
#define TIMESTAMPCOLD_RESET 137
|
||||
#define CLKMGRCOLD_RESET 138
|
||||
#define SCANMGR_RESET 139
|
||||
#define FRZCTRLCOLD_RESET 140
|
||||
#define SYSDBG_RESET 141
|
||||
#define DBG_RESET 142
|
||||
#define TAPCOLD_RESET 143
|
||||
#define SDRCOLD_RESET 144
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue