OpenE2K
/
linux
6
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

The i.MX clock fixes for 4.6: 

- Fix the typo in CAN clock definition which is introduced by commit
    ee36027427 ("clk: imx: Add clock support for imx6qp")
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQEcBAABAgAGBQJXDfVNAAoJEFBXWFqHsHzOoKwIALheb8malCyK2qqbYnALttq+
 fj/dCWG6Qg4Z/DtoudEzNxFcskZcKjI+Apy6DA4JKS5Z+j9fF9kDYpqiOsagUC1+
 FR/DmUVgRUGD8nl//xsh2akLxthgj/vGb1dvmUIYrtw0RxNrjM74c2bpmsMGFBOY
 4YB2atE0sUpvy10nUBSnKzAIBp+0PKq7+bCgAxedIF7ACdGoDwk6gamF8ypH3nhe
 nJHAcgkM0I2MWBTRP/esooCBegZ1fSo+UwJ6savMN8L+EMswV6cOTplxmagSd/gb
 9GLun+IGCpYqx9veryARFvdT8TqIMq8BciP/ZfxyLkG4qZSuDUkF55ypv/LOsRU=
 =0uIk
 -----END PGP SIGNATURE-----

Merge tag 'imx-clk-fixes-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-fixes

The i.MX clk fixes for 4.6:
 - Fix the typo in CAN clock definition which is introduced by commit
   ee36027427 ("clk: imx: Add clock support for imx6qp")

* tag 'imx-clk-fixes-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  clk: imx6q: fix typo in CAN clock definition
This commit is contained in:
Stephen Boyd 2016-04-15 15:40:49 -07:00
parent 2aac7ddf9a 7196c52c93
commit 2c49477f2a
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/clk/imx/clk-imx6q.c
View File

@ -394,7 +394,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
clk[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1", 2, 7);
} else {
clk[IMX6QDL_CLK_ECSPI_ROOT] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6);
clk[IMX6QDL_CLK_CAN_ROOT] = imx_clk_divider("can_root", "pll3_60", base + 0x20, 2, 6);
clk[IMX6QDL_CLK_CAN_ROOT] = imx_clk_divider("can_root", "pll3_60m", base + 0x20, 2, 6);
clk[IMX6QDL_CLK_IPG_PER] = imx_clk_fixup_divider("ipg_per", "ipg", base + 0x1c, 0, 6, imx_cscmr1_fixup);
clk[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6);
clk[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);