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x86: Cleanup the genirq name space 

genirq is switching to a consistent name space for the irq related
functions. Convert x86. Conversion was done with coccinelle.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
Thomas Gleixner 2011-03-12 12:20:43 +01:00
parent c1c5e4d463
commit 2c778651f7
8 changed files with 51 additions and 48 deletions
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75
arch/x86/kernel/apic/io_apic.c
View File

@ -187,7 +187,7 @@ int __init arch_early_irq_init(void)
irq_reserve_irqs(0, legacy_pic->nr_legacy_irqs);
for (i = 0; i < count; i++) {
set_irq_chip_data(i, &cfg[i]);
irq_set_chip_data(i, &cfg[i]);
zalloc_cpumask_var_node(&cfg[i].domain, GFP_KERNEL, node);
zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_KERNEL, node);
/*
@ -206,7 +206,7 @@ int __init arch_early_irq_init(void)
#ifdef CONFIG_SPARSE_IRQ
static struct irq_cfg *irq_cfg(unsigned int irq)
{
return get_irq_chip_data(irq);
return irq_get_chip_data(irq);
}
static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node)
@ -232,7 +232,7 @@ static void free_irq_cfg(unsigned int at, struct irq_cfg *cfg)
{
if (!cfg)
return;
set_irq_chip_data(at, NULL);
irq_set_chip_data(at, NULL);
free_cpumask_var(cfg->domain);
free_cpumask_var(cfg->old_domain);
kfree(cfg);
@ -262,14 +262,14 @@ static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node)
if (res < 0) {
if (res != -EEXIST)
return NULL;
cfg = get_irq_chip_data(at);
cfg = irq_get_chip_data(at);
if (cfg)
return cfg;
}
cfg = alloc_irq_cfg(at, node);
if (cfg)
set_irq_chip_data(at, cfg);
irq_set_chip_data(at, cfg);
else
irq_free_desc(at);
return cfg;
@ -1185,7 +1185,7 @@ void __setup_vector_irq(int cpu)
raw_spin_lock(&vector_lock);
/* Mark the inuse vectors */
for_each_active_irq(irq) {
cfg = get_irq_chip_data(irq);
cfg = irq_get_chip_data(irq);
if (!cfg)
continue;
/*
@ -1249,25 +1249,24 @@ static void ioapic_register_intr(unsigned int irq, unsigned long trigger)
else
irq_clear_status_flags(irq, IRQ_LEVEL);
if (irq_remapped(get_irq_chip_data(irq))) {
if (irq_remapped(irq_get_chip_data(irq))) {
irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
if (trigger)
set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
irq_set_chip_and_handler_name(irq, &ir_ioapic_chip,
handle_fasteoi_irq,
"fasteoi");
"fasteoi");
else
set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
irq_set_chip_and_handler_name(irq, &ir_ioapic_chip,
handle_edge_irq, "edge");
return;
}
if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
trigger == IOAPIC_LEVEL)
set_irq_chip_and_handler_name(irq, &ioapic_chip,
handle_fasteoi_irq,
"fasteoi");
irq_set_chip_and_handler_name(irq, &ioapic_chip,
handle_fasteoi_irq, "fasteoi");
else
set_irq_chip_and_handler_name(irq, &ioapic_chip,
irq_set_chip_and_handler_name(irq, &ioapic_chip,
handle_edge_irq, "edge");
}
@ -1491,7 +1490,8 @@ static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
* The timer IRQ doesn't have to know that behind the
* scene we may have a 8259A-master in AEOI mode ...
*/
set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq,
"edge");
/*
* Add it to the IO-APIC irq-routing table:
@ -1598,7 +1598,7 @@ __apicdebuginit(void) print_IO_APIC(void)
for_each_active_irq(irq) {
struct irq_pin_list *entry;
cfg = get_irq_chip_data(irq);
cfg = irq_get_chip_data(irq);
if (!cfg)
continue;
entry = cfg->irq_2_pin;
@ -2364,7 +2364,7 @@ static void irq_complete_move(struct irq_cfg *cfg)
void irq_force_complete_move(int irq)
{
struct irq_cfg *cfg = get_irq_chip_data(irq);
struct irq_cfg *cfg = irq_get_chip_data(irq);
if (!cfg)
return;
@ -2587,7 +2587,7 @@ static inline void init_IO_APIC_traps(void)
* 0x80, because int 0x80 is hm, kind of importantish. ;)
*/
for_each_active_irq(irq) {
cfg = get_irq_chip_data(irq);
cfg = irq_get_chip_data(irq);
if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
/*
* Hmm.. We don't have an entry for this,
@ -2598,7 +2598,7 @@ static inline void init_IO_APIC_traps(void)
legacy_pic->make_irq(irq);
else
/* Strange. Oh, well.. */
set_irq_chip(irq, &no_irq_chip);
irq_set_chip(irq, &no_irq_chip);
}
}
}
@ -2638,7 +2638,7 @@ static struct irq_chip lapic_chip __read_mostly = {
static void lapic_register_intr(int irq)
{
irq_clear_status_flags(irq, IRQ_LEVEL);
set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
"edge");
}
@ -2722,7 +2722,7 @@ int timer_through_8259 __initdata;
*/
static inline void __init check_timer(void)
{
struct irq_cfg *cfg = get_irq_chip_data(0);
struct irq_cfg *cfg = irq_get_chip_data(0);
int node = cpu_to_node(0);
int apic1, pin1, apic2, pin2;
unsigned long flags;
@ -3033,7 +3033,7 @@ unsigned int create_irq_nr(unsigned int from, int node)
raw_spin_unlock_irqrestore(&vector_lock, flags);
if (ret) {
set_irq_chip_data(irq, cfg);
irq_set_chip_data(irq, cfg);
irq_clear_status_flags(irq, IRQ_NOREQUEST);
} else {
free_irq_at(irq, cfg);
@ -3058,7 +3058,7 @@ int create_irq(void)
void destroy_irq(unsigned int irq)
{
struct irq_cfg *cfg = get_irq_chip_data(irq);
struct irq_cfg *cfg = irq_get_chip_data(irq);
unsigned long flags;
irq_set_status_flags(irq, IRQ_NOREQUEST|IRQ_NOPROBE);
@ -3092,7 +3092,7 @@ static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
if (irq_remapped(get_irq_chip_data(irq))) {
if (irq_remapped(irq_get_chip_data(irq))) {
struct irte irte;
int ir_index;
u16 sub_handle;
@ -3271,14 +3271,16 @@ static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
if (ret < 0)
return ret;
set_irq_msi(irq, msidesc);
irq_set_msi_desc(irq, msidesc);
write_msi_msg(irq, &msg);
if (irq_remapped(get_irq_chip_data(irq))) {
if (irq_remapped(irq_get_chip_data(irq))) {
irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
irq_set_chip_and_handler_name(irq, &msi_ir_chip,
handle_edge_irq, "edge");
} else
set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
irq_set_chip_and_handler_name(irq, &msi_chip,
handle_edge_irq, "edge");
dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
@ -3396,8 +3398,8 @@ int arch_setup_dmar_msi(unsigned int irq)
if (ret < 0)
return ret;
dmar_msi_write(irq, &msg);
set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
"edge");
irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
"edge");
return 0;
}
#endif
@ -3474,13 +3476,13 @@ int arch_setup_hpet_msi(unsigned int irq, unsigned int id)
if (ret < 0)
return ret;
hpet_msi_write(get_irq_data(irq), &msg);
hpet_msi_write(irq_get_handler_data(irq), &msg);
irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
if (irq_remapped(get_irq_chip_data(irq)))
set_irq_chip_and_handler_name(irq, &ir_hpet_msi_type,
if (irq_remapped(irq_get_chip_data(irq)))
irq_set_chip_and_handler_name(irq, &ir_hpet_msi_type,
handle_edge_irq, "edge");
else
set_irq_chip_and_handler_name(irq, &hpet_msi_type,
irq_set_chip_and_handler_name(irq, &hpet_msi_type,
handle_edge_irq, "edge");
return 0;
@ -3569,7 +3571,7 @@ int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
write_ht_irq_msg(irq, &msg);
set_irq_chip_and_handler_name(irq, &ht_irq_chip,
irq_set_chip_and_handler_name(irq, &ht_irq_chip,
handle_edge_irq, "edge");
dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
@ -4054,5 +4056,6 @@ void __init pre_init_apic_IRQ0(void)
setup_local_APIC();
io_apic_setup_irq_pin(0, 0, &attr);
set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq,
"edge");
}

2
arch/x86/kernel/hpet.c
View File

@ -503,7 +503,7 @@ static int hpet_assign_irq(struct hpet_dev *dev)
if (!irq)
return -EINVAL;
set_irq_data(irq, dev);
irq_set_handler_data(irq, dev);
if (hpet_setup_msi_irq(irq))
return -EINVAL;

2
arch/x86/kernel/i8259.c
View File

@ -112,7 +112,7 @@ static void make_8259A_irq(unsigned int irq)
{
disable_irq_nosync(irq);
io_apic_irqs &= ~(1<<irq);
set_irq_chip_and_handler_name(irq, &i8259A_chip, handle_level_irq,
irq_set_chip_and_handler_name(irq, &i8259A_chip, handle_level_irq,
i8259A_chip.name);
enable_irq(irq);
}

2
arch/x86/kernel/irqinit.c
View File

@ -110,7 +110,7 @@ void __init init_ISA_irqs(void)
legacy_pic->init(0);
for (i = 0; i < legacy_pic->nr_legacy_irqs; i++)
set_irq_chip_and_handler_name(i, chip, handle_level_irq, name);
irq_set_chip_and_handler_name(i, chip, handle_level_irq, name);
}
void __init init_IRQ(void)

4
arch/x86/lguest/boot.c
View File

@ -847,7 +847,7 @@ static void __init lguest_init_IRQ(void)
void lguest_setup_irq(unsigned int irq)
{
irq_alloc_desc_at(irq, 0);
set_irq_chip_and_handler_name(irq, &lguest_irq_controller,
irq_set_chip_and_handler_name(irq, &lguest_irq_controller,
handle_level_irq, "level");
}
@ -995,7 +995,7 @@ static void lguest_time_irq(unsigned int irq, struct irq_desc *desc)
static void lguest_time_init(void)
{
/* Set up the timer interrupt (0) to go to our simple timer routine */
set_irq_handler(0, lguest_time_irq);
irq_set_handler(0, lguest_time_irq);
clocksource_register(&lguest_clock);

8
arch/x86/pci/xen.c
View File

@ -104,7 +104,7 @@ static int xen_hvm_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
"msi-x" : "msi", &irq, &pirq, XEN_ALLOC_IRQ);
if (irq < 0)
goto error;
ret = set_irq_msi(irq, msidesc);
ret = irq_set_msi_desc(irq, msidesc);
if (ret < 0)
goto error_while;
printk(KERN_DEBUG "xen: msi already setup: msi --> irq=%d"
@ -117,7 +117,7 @@ static int xen_hvm_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
goto error;
printk(KERN_DEBUG "xen: msi --> irq=%d, pirq=%d\n", irq, pirq);
xen_msi_compose_msg(dev, pirq, &msg);
ret = set_irq_msi(irq, msidesc);
ret = irq_set_msi_desc(irq, msidesc);
if (ret < 0)
goto error_while;
write_msi_msg(irq, &msg);
@ -165,7 +165,7 @@ static int xen_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
goto free;
}
ret = set_irq_msi(irq, msidesc);
ret = irq_set_msi_desc(irq, msidesc);
if (ret)
goto error_while;
i++;
@ -210,7 +210,7 @@ static int xen_initdom_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
if (irq < 0)
return -1;
ret = set_irq_msi(irq, msidesc);
ret = irq_set_msi_desc(irq, msidesc);
if (ret)
goto error;
}

4
arch/x86/platform/uv/uv_irq.c
View File

@ -131,7 +131,7 @@ arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
unsigned long mmr_offset, int limit)
{
const struct cpumask *eligible_cpu = cpumask_of(cpu);
struct irq_cfg *cfg = get_irq_chip_data(irq);
struct irq_cfg *cfg = irq_get_chip_data(irq);
unsigned long mmr_value;
struct uv_IO_APIC_route_entry *entry;
int mmr_pnode, err;
@ -148,7 +148,7 @@ arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
else
irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
irq_set_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
irq_name);
mmr_value = 0;

2
arch/x86/platform/visws/visws_quirks.c
View File

@ -606,7 +606,7 @@ static void __init visws_pre_intr_init(void)
chip = &cobalt_irq_type;
if (chip)
set_irq_chip(i, chip);
irq_set_chip(i, chip);
}
setup_irq(CO_IRQ_8259, &master_action);