- Fix PCH reference clock for FDI on HSW/BDW which was causing users blank screen
- Small documentation fix for TGL display PLLs -----BEGIN PGP SIGNATURE----- iQEcBAABAgAGBQJduxXJAAoJEPpiX2QO6xPK2RgIALTt7ABu9pEDKeFzVnlccRqx XO2wTDD+an1QAegIARDAmmqYfEBtE5HpA6UFkM+v7zqLwT66CTvcKilgwGXuTk9E 6X8Y4JwqImAZJiVfzSLF3yRdNgNyOubNf7yhXNKPWTeolxXsLPljZXpFHGeXMFv4 Gp99CkZL4Q/Tgh8pRSXQZT4nXk6mO0t9FMJVyP7++mXtrN5pzw/gjb5J89VWkgXC koAVUvkbPIs7VUB/1B2N8fhP33d15snbQjVS4+NwRWBRPr/r66OmHYKRZS538fbL IUMqpKHAyWXBr59PO4JRBxnDDUXMa0xZ5bUmZ5JcK4eDNO3BxA70jJ1hFGeLrFE= =N65J -----END PGP SIGNATURE----- Merge tag 'drm-intel-fixes-2019-10-31' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes - Fix PCH reference clock for FDI on HSW/BDW which was causing users blank screen - Small documentation fix for TGL display PLLs Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191031171209.GA6586@intel.com
This commit is contained in:
commit
2cac8c4480
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@ -9315,7 +9315,6 @@ static bool wrpll_uses_pch_ssc(struct drm_i915_private *dev_priv,
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static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
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static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
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{
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{
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struct intel_encoder *encoder;
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struct intel_encoder *encoder;
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bool pch_ssc_in_use = false;
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bool has_fdi = false;
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bool has_fdi = false;
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for_each_intel_encoder(&dev_priv->drm, encoder) {
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for_each_intel_encoder(&dev_priv->drm, encoder) {
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@ -9343,22 +9342,24 @@ static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
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* clock hierarchy. That would also allow us to do
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* clock hierarchy. That would also allow us to do
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* clock bending finally.
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* clock bending finally.
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*/
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*/
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dev_priv->pch_ssc_use = 0;
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if (spll_uses_pch_ssc(dev_priv)) {
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if (spll_uses_pch_ssc(dev_priv)) {
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DRM_DEBUG_KMS("SPLL using PCH SSC\n");
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DRM_DEBUG_KMS("SPLL using PCH SSC\n");
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pch_ssc_in_use = true;
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dev_priv->pch_ssc_use |= BIT(DPLL_ID_SPLL);
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}
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}
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if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL1)) {
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if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL1)) {
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DRM_DEBUG_KMS("WRPLL1 using PCH SSC\n");
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DRM_DEBUG_KMS("WRPLL1 using PCH SSC\n");
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pch_ssc_in_use = true;
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dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL1);
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}
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}
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if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL2)) {
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if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL2)) {
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DRM_DEBUG_KMS("WRPLL2 using PCH SSC\n");
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DRM_DEBUG_KMS("WRPLL2 using PCH SSC\n");
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pch_ssc_in_use = true;
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dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL2);
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}
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}
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if (pch_ssc_in_use)
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if (dev_priv->pch_ssc_use)
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return;
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return;
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if (has_fdi) {
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if (has_fdi) {
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@ -525,16 +525,31 @@ static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv,
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val = I915_READ(WRPLL_CTL(id));
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val = I915_READ(WRPLL_CTL(id));
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I915_WRITE(WRPLL_CTL(id), val & ~WRPLL_PLL_ENABLE);
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I915_WRITE(WRPLL_CTL(id), val & ~WRPLL_PLL_ENABLE);
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POSTING_READ(WRPLL_CTL(id));
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POSTING_READ(WRPLL_CTL(id));
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/*
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* Try to set up the PCH reference clock once all DPLLs
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* that depend on it have been shut down.
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*/
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if (dev_priv->pch_ssc_use & BIT(id))
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intel_init_pch_refclk(dev_priv);
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}
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}
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static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv,
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static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv,
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struct intel_shared_dpll *pll)
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struct intel_shared_dpll *pll)
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{
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{
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enum intel_dpll_id id = pll->info->id;
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u32 val;
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u32 val;
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val = I915_READ(SPLL_CTL);
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val = I915_READ(SPLL_CTL);
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I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
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I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
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POSTING_READ(SPLL_CTL);
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POSTING_READ(SPLL_CTL);
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/*
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* Try to set up the PCH reference clock once all DPLLs
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* that depend on it have been shut down.
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*/
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if (dev_priv->pch_ssc_use & BIT(id))
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intel_init_pch_refclk(dev_priv);
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}
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}
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static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv,
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static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv,
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@ -147,11 +147,11 @@ enum intel_dpll_id {
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*/
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*/
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DPLL_ID_ICL_MGPLL4 = 6,
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DPLL_ID_ICL_MGPLL4 = 6,
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/**
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/**
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* @DPLL_ID_TGL_TCPLL5: TGL TC PLL port 5 (TC5)
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* @DPLL_ID_TGL_MGPLL5: TGL TC PLL port 5 (TC5)
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*/
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*/
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DPLL_ID_TGL_MGPLL5 = 7,
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DPLL_ID_TGL_MGPLL5 = 7,
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/**
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/**
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* @DPLL_ID_TGL_TCPLL6: TGL TC PLL port 6 (TC6)
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* @DPLL_ID_TGL_MGPLL6: TGL TC PLL port 6 (TC6)
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*/
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*/
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DPLL_ID_TGL_MGPLL6 = 8,
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DPLL_ID_TGL_MGPLL6 = 8,
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};
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};
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@ -1723,6 +1723,8 @@ struct drm_i915_private {
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struct work_struct idle_work;
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struct work_struct idle_work;
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} gem;
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} gem;
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u8 pch_ssc_use;
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/* For i945gm vblank irq vs. C3 workaround */
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/* For i945gm vblank irq vs. C3 workaround */
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struct {
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struct {
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struct work_struct work;
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struct work_struct work;
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