clk: samsung: exynos5420: Add clock IDs needed by GPU
Adds IDs for the clocks needed by the ARM Mali GPU in exynos5420. Signed-off-by: Arun Kumar K <arun.kk@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
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@ -363,7 +363,7 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
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MUX(0, "mout_aclk66_psgen", aclk66_peric_p, SRC_TOP5, 4, 1),
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MUX(0, "mout_user_aclk333_g2d", user_aclk333_g2d_p, SRC_TOP5, 8, 1),
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MUX(0, "mout_user_aclk266_g2d", user_aclk266_g2d_p, SRC_TOP5, 12, 1),
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MUX_A(0, "mout_user_aclk_g3d", user_aclk_g3d_p,
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MUX_A(CLK_MOUT_G3D, "mout_user_aclk_g3d", user_aclk_g3d_p,
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SRC_TOP5, 16, 1, "aclkg3d"),
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MUX(0, "mout_user_aclk300_jpeg", user_aclk300_jpeg_p,
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SRC_TOP5, 20, 1),
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@ -373,7 +373,7 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
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SRC_TOP5, 28, 1),
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MUX(0, "sclk_mpll", mpll_p, SRC_TOP6, 0, 1),
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MUX(0, "sclk_vpll", vpll_p, SRC_TOP6, 4, 1),
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MUX(CLK_MOUT_VPLL, "sclk_vpll", vpll_p, SRC_TOP6, 4, 1),
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MUX(0, "sclk_spll", spll_p, SRC_TOP6, 8, 1),
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MUX(0, "sclk_ipll", ipll_p, SRC_TOP6, 12, 1),
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MUX(0, "sclk_rpll", rpll_p, SRC_TOP6, 16, 1),
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@ -178,6 +178,8 @@
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/* mux clocks */
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#define CLK_MOUT_HDMI 640
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#define CLK_MOUT_G3D 641
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#define CLK_MOUT_VPLL 642
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/* divider clocks */
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#define CLK_DOUT_PIXEL 768
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