[ARM] S3C2443: Add prediv clk and fix setting of h and p clocks
Update the S3C2443 clock support to add the prediv clock that is sourced via a divider from msysclk. Also fix the setting of p and h clocks from this prediv clock. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
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@ -678,6 +678,29 @@ static struct clk clk_display = {
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.round_rate = s3c2443_roundrate_clksrc256,
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.round_rate = s3c2443_roundrate_clksrc256,
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};
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};
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/* prediv
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*
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* this divides the msysclk down to pass to h/p/etc.
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*/
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static unsigned long s3c2443_prediv_getrate(struct clk *clk)
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{
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unsigned long rate = clk_get_rate(clk->parent);
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unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
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clkdiv0 &= S3C2443_CLKDIV0_PREDIV_MASK;
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clkdiv0 >>= S3C2443_CLKDIV0_PREDIV_SHIFT;
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return rate / (clkdiv0 + 1);
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}
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static struct clk clk_prediv = {
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.name = "prediv",
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.id = -1,
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.parent = &clk_msysclk,
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.get_rate = s3c2443_prediv_getrate,
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};
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/* standard clock definitions */
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/* standard clock definitions */
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static struct clk init_clocks_disable[] = {
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static struct clk init_clocks_disable[] = {
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@ -957,10 +980,9 @@ static inline unsigned int s3c2443_fclk_div(unsigned long clkcon0)
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return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT];
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return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT];
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}
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}
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static inline unsigned long s3c2443_get_prediv(unsigned long clkcon0)
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static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0)
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{
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{
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clkcon0 &= S3C2443_CLKDIV0_PREDIV_MASK;
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clkcon0 &= S3C2443_CLKDIV0_HCLKDIV_MASK;
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clkcon0 >>= S3C2443_CLKDIV0_PREDIV_SHIFT;
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return clkcon0 + 1;
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return clkcon0 + 1;
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}
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}
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@ -986,6 +1008,7 @@ static struct clk *clks[] __initdata = {
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&clk_hsmmc,
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&clk_hsmmc,
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&clk_armdiv,
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&clk_armdiv,
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&clk_arm,
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&clk_arm,
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&clk_prediv,
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};
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};
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void __init s3c2443_init_clocks(int xtal)
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void __init s3c2443_init_clocks(int xtal)
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@ -1001,15 +1024,19 @@ void __init s3c2443_init_clocks(int xtal)
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int ret;
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int ret;
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int ptr;
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int ptr;
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/* s3c2443 parents h and p clocks from prediv */
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clk_h.parent = &clk_prediv;
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clk_p.parent = &clk_prediv;
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pll = s3c2443_get_mpll(mpllcon, xtal);
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pll = s3c2443_get_mpll(mpllcon, xtal);
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clk_msysclk.rate = pll;
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fclk = pll / s3c2443_fclk_div(clkdiv0);
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fclk = pll / s3c2443_fclk_div(clkdiv0);
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hclk = fclk / s3c2443_get_prediv(clkdiv0);
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hclk = s3c2443_prediv_getrate(&clk_prediv);
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hclk = hclk / s3c2443_get_hdiv(clkdiv0);
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hclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_HCLK) ? 2 : 1);
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hclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_HCLK) ? 2 : 1);
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pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1);
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pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1);
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clk_armdiv.rate = fclk;
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s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);
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s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);
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printk("S3C2443: mpll %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n",
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printk("S3C2443: mpll %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n",
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