Merge branch 'pci/misc' into next
* pci/misc: PCI: Remove pcie_cap_has_devctl() PCI: Support PCIe Capability Slot registers only for ports with slots PCI: Remove PCIe Capability version checks PCI: Allow PCIe Capability link-related register access for switches PCI: Add offsets of PCIe capability registers PCI: Tidy bitmasks and spacing of PCIe capability definitions PCI: Remove obsolete comment reference to pci_pcie_cap2() PCI: Clarify PCI_EXP_TYPE_PCI_BRIDGE comment PCI: Rename PCIe capability definitions to follow convention PCI: Disable decoding for BAR sizing only when it was actually enabled PCI: Add comment about needing pci_msi_off() even when CONFIG_PCI_MSI=n PCI: Add pcibios_pm_ops for optional arch-specific hibernate functionality
This commit is contained in:
Bjorn Helgaas
commit
2e8b5f621d
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@ -44,7 +44,7 @@ static int rts5227_extra_init_hw(struct rtsx_pcr *pcr)
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
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/* Configure LTR */
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pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &cap);
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if (cap & PCI_EXP_LTR_EN)
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if (cap & PCI_EXP_DEVCTL2_LTR_EN)
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LTR_CTL, 0xFF, 0xA3);
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/* Configure OBFF */
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OBFF_CFG, 0x03, 0x03);
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@ -475,37 +475,33 @@ static inline int pcie_cap_version(const struct pci_dev *dev)
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return pcie_caps_reg(dev) & PCI_EXP_FLAGS_VERS;
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}
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static inline bool pcie_cap_has_devctl(const struct pci_dev *dev)
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{
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return true;
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}
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static inline bool pcie_cap_has_lnkctl(const struct pci_dev *dev)
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{
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int type = pci_pcie_type(dev);
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return pcie_cap_version(dev) > 1 ||
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return type == PCI_EXP_TYPE_ENDPOINT ||
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type == PCI_EXP_TYPE_LEG_END ||
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type == PCI_EXP_TYPE_ROOT_PORT ||
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type == PCI_EXP_TYPE_ENDPOINT ||
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type == PCI_EXP_TYPE_LEG_END;
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type == PCI_EXP_TYPE_UPSTREAM ||
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type == PCI_EXP_TYPE_DOWNSTREAM ||
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type == PCI_EXP_TYPE_PCI_BRIDGE ||
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type == PCI_EXP_TYPE_PCIE_BRIDGE;
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}
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static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev)
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{
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int type = pci_pcie_type(dev);
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return pcie_cap_version(dev) > 1 ||
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type == PCI_EXP_TYPE_ROOT_PORT ||
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(type == PCI_EXP_TYPE_DOWNSTREAM &&
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pcie_caps_reg(dev) & PCI_EXP_FLAGS_SLOT);
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return (type == PCI_EXP_TYPE_ROOT_PORT ||
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type == PCI_EXP_TYPE_DOWNSTREAM) &&
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pcie_caps_reg(dev) & PCI_EXP_FLAGS_SLOT;
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}
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static inline bool pcie_cap_has_rtctl(const struct pci_dev *dev)
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{
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int type = pci_pcie_type(dev);
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return pcie_cap_version(dev) > 1 ||
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type == PCI_EXP_TYPE_ROOT_PORT ||
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return type == PCI_EXP_TYPE_ROOT_PORT ||
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type == PCI_EXP_TYPE_RC_EC;
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}
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@ -520,7 +516,7 @@ static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
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case PCI_EXP_DEVCAP:
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case PCI_EXP_DEVCTL:
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case PCI_EXP_DEVSTA:
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return pcie_cap_has_devctl(dev);
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return true;
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case PCI_EXP_LNKCAP:
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case PCI_EXP_LNKCTL:
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case PCI_EXP_LNKSTA:
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@ -763,6 +763,13 @@ static int pci_pm_resume(struct device *dev)
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#ifdef CONFIG_HIBERNATE_CALLBACKS
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/*
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* pcibios_pm_ops - provide arch-specific hooks when a PCI device is doing
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* a hibernate transition
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*/
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struct dev_pm_ops __weak pcibios_pm_ops;
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static int pci_pm_freeze(struct device *dev)
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{
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struct pci_dev *pci_dev = to_pci_dev(dev);
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@ -786,6 +793,9 @@ static int pci_pm_freeze(struct device *dev)
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return error;
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}
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if (pcibios_pm_ops.freeze)
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return pcibios_pm_ops.freeze(dev);
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return 0;
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}
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@ -811,6 +821,9 @@ static int pci_pm_freeze_noirq(struct device *dev)
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pci_pm_set_unknown_state(pci_dev);
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if (pcibios_pm_ops.freeze_noirq)
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return pcibios_pm_ops.freeze_noirq(dev);
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return 0;
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}
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@ -820,6 +833,12 @@ static int pci_pm_thaw_noirq(struct device *dev)
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struct device_driver *drv = dev->driver;
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int error = 0;
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if (pcibios_pm_ops.thaw_noirq) {
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error = pcibios_pm_ops.thaw_noirq(dev);
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if (error)
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return error;
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}
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if (pci_has_legacy_pm_support(pci_dev))
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return pci_legacy_resume_early(dev);
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@ -837,6 +856,12 @@ static int pci_pm_thaw(struct device *dev)
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const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL;
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int error = 0;
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if (pcibios_pm_ops.thaw) {
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error = pcibios_pm_ops.thaw(dev);
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if (error)
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return error;
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}
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if (pci_has_legacy_pm_support(pci_dev))
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return pci_legacy_resume(dev);
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@ -878,6 +903,9 @@ static int pci_pm_poweroff(struct device *dev)
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Fixup:
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pci_fixup_device(pci_fixup_suspend, pci_dev);
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if (pcibios_pm_ops.poweroff)
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return pcibios_pm_ops.poweroff(dev);
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return 0;
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}
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@ -911,6 +939,9 @@ static int pci_pm_poweroff_noirq(struct device *dev)
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if (pci_dev->class == PCI_CLASS_SERIAL_USB_EHCI)
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pci_write_config_word(pci_dev, PCI_COMMAND, 0);
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if (pcibios_pm_ops.poweroff_noirq)
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return pcibios_pm_ops.poweroff_noirq(dev);
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return 0;
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}
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@ -920,6 +951,12 @@ static int pci_pm_restore_noirq(struct device *dev)
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struct device_driver *drv = dev->driver;
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int error = 0;
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if (pcibios_pm_ops.restore_noirq) {
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error = pcibios_pm_ops.restore_noirq(dev);
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if (error)
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return error;
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}
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pci_pm_default_resume_early(pci_dev);
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if (pci_has_legacy_pm_support(pci_dev))
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@ -937,6 +974,12 @@ static int pci_pm_restore(struct device *dev)
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const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL;
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int error = 0;
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if (pcibios_pm_ops.restore) {
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error = pcibios_pm_ops.restore(dev);
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if (error)
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return error;
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}
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/*
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* This is necessary for the hibernation error path in which restore is
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* called without restoring the standard config registers of the device.
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@ -2116,9 +2116,9 @@ void pci_enable_ido(struct pci_dev *dev, unsigned long type)
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u16 ctrl = 0;
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if (type & PCI_EXP_IDO_REQUEST)
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ctrl |= PCI_EXP_IDO_REQ_EN;
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ctrl |= PCI_EXP_DEVCTL2_IDO_REQ_EN;
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if (type & PCI_EXP_IDO_COMPLETION)
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ctrl |= PCI_EXP_IDO_CMP_EN;
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ctrl |= PCI_EXP_DEVCTL2_IDO_CMP_EN;
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if (ctrl)
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pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, ctrl);
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}
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@ -2134,9 +2134,9 @@ void pci_disable_ido(struct pci_dev *dev, unsigned long type)
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u16 ctrl = 0;
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if (type & PCI_EXP_IDO_REQUEST)
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ctrl |= PCI_EXP_IDO_REQ_EN;
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ctrl |= PCI_EXP_DEVCTL2_IDO_REQ_EN;
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if (type & PCI_EXP_IDO_COMPLETION)
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ctrl |= PCI_EXP_IDO_CMP_EN;
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ctrl |= PCI_EXP_DEVCTL2_IDO_CMP_EN;
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if (ctrl)
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pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, ctrl);
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}
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@ -2168,7 +2168,7 @@ int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
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int ret;
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pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
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if (!(cap & PCI_EXP_OBFF_MASK))
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if (!(cap & PCI_EXP_DEVCAP2_OBFF_MASK))
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return -ENOTSUPP; /* no OBFF support at all */
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/* Make sure the topology supports OBFF as well */
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@ -2179,17 +2179,17 @@ int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
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}
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pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &ctrl);
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if (cap & PCI_EXP_OBFF_WAKE)
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ctrl |= PCI_EXP_OBFF_WAKE_EN;
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if (cap & PCI_EXP_DEVCAP2_OBFF_WAKE)
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ctrl |= PCI_EXP_DEVCTL2_OBFF_WAKE_EN;
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else {
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switch (type) {
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case PCI_EXP_OBFF_SIGNAL_L0:
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if (!(ctrl & PCI_EXP_OBFF_WAKE_EN))
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ctrl |= PCI_EXP_OBFF_MSGA_EN;
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if (!(ctrl & PCI_EXP_DEVCTL2_OBFF_WAKE_EN))
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ctrl |= PCI_EXP_DEVCTL2_OBFF_MSGA_EN;
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break;
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case PCI_EXP_OBFF_SIGNAL_ALWAYS:
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ctrl &= ~PCI_EXP_OBFF_WAKE_EN;
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ctrl |= PCI_EXP_OBFF_MSGB_EN;
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ctrl &= ~PCI_EXP_DEVCTL2_OBFF_WAKE_EN;
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ctrl |= PCI_EXP_DEVCTL2_OBFF_MSGB_EN;
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break;
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default:
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WARN(1, "bad OBFF signal type\n");
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@ -2210,7 +2210,8 @@ EXPORT_SYMBOL(pci_enable_obff);
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*/
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void pci_disable_obff(struct pci_dev *dev)
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{
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pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_OBFF_WAKE_EN);
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pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2,
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PCI_EXP_DEVCTL2_OBFF_WAKE_EN);
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}
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EXPORT_SYMBOL(pci_disable_obff);
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@ -2258,7 +2259,8 @@ int pci_enable_ltr(struct pci_dev *dev)
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return ret;
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}
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return pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_LTR_EN);
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return pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
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PCI_EXP_DEVCTL2_LTR_EN);
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}
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EXPORT_SYMBOL(pci_enable_ltr);
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@ -2275,7 +2277,8 @@ void pci_disable_ltr(struct pci_dev *dev)
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if (!pci_ltr_supported(dev))
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return;
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pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_LTR_EN);
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pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2,
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PCI_EXP_DEVCTL2_LTR_EN);
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}
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EXPORT_SYMBOL(pci_disable_ltr);
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@ -3141,18 +3144,23 @@ bool pci_check_and_unmask_intx(struct pci_dev *dev)
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EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
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/**
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* pci_msi_off - disables any msi or msix capabilities
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* pci_msi_off - disables any MSI or MSI-X capabilities
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* @dev: the PCI device to operate on
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*
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* If you want to use msi see pci_enable_msi and friends.
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* This is a lower level primitive that allows us to disable
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* msi operation at the device level.
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* If you want to use MSI, see pci_enable_msi() and friends.
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* This is a lower-level primitive that allows us to disable
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* MSI operation at the device level.
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*/
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void pci_msi_off(struct pci_dev *dev)
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{
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int pos;
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u16 control;
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/*
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* This looks like it could go in msi.c, but we need it even when
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* CONFIG_PCI_MSI=n. For the same reason, we can't use
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* dev->msi_cap or dev->msix_cap here.
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*/
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pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
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if (pos) {
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pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
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@ -156,6 +156,8 @@ static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
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return flags;
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}
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#define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
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/**
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* pci_read_base - read a PCI BAR
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* @dev: the PCI device
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@ -178,8 +180,10 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
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/* No printks while decoding is disabled! */
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if (!dev->mmio_always_on) {
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pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
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pci_write_config_word(dev, PCI_COMMAND,
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orig_cmd & ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
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if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
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pci_write_config_word(dev, PCI_COMMAND,
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orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
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}
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}
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res->name = pci_name(dev);
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@ -293,7 +297,8 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
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fail:
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res->flags = 0;
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out:
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if (!dev->mmio_always_on)
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if (!dev->mmio_always_on &&
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(orig_cmd & PCI_COMMAND_DECODE_ENABLE))
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pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
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if (bar_too_big)
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|
|
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@ -1654,6 +1654,10 @@ int pcibios_set_pcie_reset_state(struct pci_dev *dev,
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int pcibios_add_device(struct pci_dev *dev);
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void pcibios_release_device(struct pci_dev *dev);
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#ifdef CONFIG_HIBERNATE_CALLBACKS
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extern struct dev_pm_ops pcibios_pm_ops;
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#endif
|
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|
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#ifdef CONFIG_PCI_MMCONFIG
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void __init pci_mmcfg_early_init(void);
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void __init pci_mmcfg_late_init(void);
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|
|
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@ -421,24 +421,24 @@
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#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
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#define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
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#define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
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#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */
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#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIE Bridge */
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#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCIe to PCI/PCI-X Bridge */
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#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIe Bridge */
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#define PCI_EXP_TYPE_RC_END 0x9 /* Root Complex Integrated Endpoint */
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#define PCI_EXP_TYPE_RC_EC 0xa /* Root Complex Event Collector */
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#define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
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#define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
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#define PCI_EXP_DEVCAP 4 /* Device capabilities */
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#define PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */
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#define PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */
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#define PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */
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#define PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */
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#define PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */
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#define PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */
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#define PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */
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#define PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */
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#define PCI_EXP_DEVCAP_RBER 0x8000 /* Role-Based Error Reporting */
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#define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
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#define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
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#define PCI_EXP_DEVCAP_PAYLOAD 0x00000007 /* Max_Payload_Size */
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#define PCI_EXP_DEVCAP_PHANTOM 0x00000018 /* Phantom functions */
|
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#define PCI_EXP_DEVCAP_EXT_TAG 0x00000020 /* Extended tags */
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#define PCI_EXP_DEVCAP_L0S 0x000001c0 /* L0s Acceptable Latency */
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#define PCI_EXP_DEVCAP_L1 0x00000e00 /* L1 Acceptable Latency */
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#define PCI_EXP_DEVCAP_ATN_BUT 0x00001000 /* Attention Button Present */
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#define PCI_EXP_DEVCAP_ATN_IND 0x00002000 /* Attention Indicator Present */
|
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#define PCI_EXP_DEVCAP_PWR_IND 0x00004000 /* Power Indicator Present */
|
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#define PCI_EXP_DEVCAP_RBER 0x00008000 /* Role-Based Error Reporting */
|
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#define PCI_EXP_DEVCAP_PWR_VAL 0x03fc0000 /* Slot Power Limit Value */
|
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#define PCI_EXP_DEVCAP_PWR_SCL 0x0c000000 /* Slot Power Limit Scale */
|
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#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */
|
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#define PCI_EXP_DEVCTL 8 /* Device Control */
|
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#define PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */
|
||||
|
|
@ -454,16 +454,16 @@
|
|||
#define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
|
||||
#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */
|
||||
#define PCI_EXP_DEVSTA 10 /* Device Status */
|
||||
#define PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */
|
||||
#define PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */
|
||||
#define PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */
|
||||
#define PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Request Detected */
|
||||
#define PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */
|
||||
#define PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */
|
||||
#define PCI_EXP_DEVSTA_CED 0x0001 /* Correctable Error Detected */
|
||||
#define PCI_EXP_DEVSTA_NFED 0x0002 /* Non-Fatal Error Detected */
|
||||
#define PCI_EXP_DEVSTA_FED 0x0004 /* Fatal Error Detected */
|
||||
#define PCI_EXP_DEVSTA_URD 0x0008 /* Unsupported Request Detected */
|
||||
#define PCI_EXP_DEVSTA_AUXPD 0x0010 /* AUX Power Detected */
|
||||
#define PCI_EXP_DEVSTA_TRPND 0x0020 /* Transactions Pending */
|
||||
#define PCI_EXP_LNKCAP 12 /* Link Capabilities */
|
||||
#define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */
|
||||
#define PCI_EXP_LNKCAP_SLS_2_5GB 0x1 /* LNKCAP2 SLS Vector bit 0 (2.5GT/s) */
|
||||
#define PCI_EXP_LNKCAP_SLS_5_0GB 0x2 /* LNKCAP2 SLS Vector bit 1 (5.0GT/s) */
|
||||
#define PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001 /* LNKCAP2 SLS Vector bit 0 */
|
||||
#define PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 /* LNKCAP2 SLS Vector bit 1 */
|
||||
#define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */
|
||||
#define PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */
|
||||
#define PCI_EXP_LNKCAP_L0SEL 0x00007000 /* L0s Exit Latency */
|
||||
|
|
@ -475,21 +475,21 @@
|
|||
#define PCI_EXP_LNKCAP_PN 0xff000000 /* Port Number */
|
||||
#define PCI_EXP_LNKCTL 16 /* Link Control */
|
||||
#define PCI_EXP_LNKCTL_ASPMC 0x0003 /* ASPM Control */
|
||||
#define PCI_EXP_LNKCTL_ASPM_L0S 0x01 /* L0s Enable */
|
||||
#define PCI_EXP_LNKCTL_ASPM_L1 0x02 /* L1 Enable */
|
||||
#define PCI_EXP_LNKCTL_ASPM_L0S 0x0001 /* L0s Enable */
|
||||
#define PCI_EXP_LNKCTL_ASPM_L1 0x0002 /* L1 Enable */
|
||||
#define PCI_EXP_LNKCTL_RCB 0x0008 /* Read Completion Boundary */
|
||||
#define PCI_EXP_LNKCTL_LD 0x0010 /* Link Disable */
|
||||
#define PCI_EXP_LNKCTL_RL 0x0020 /* Retrain Link */
|
||||
#define PCI_EXP_LNKCTL_CCC 0x0040 /* Common Clock Configuration */
|
||||
#define PCI_EXP_LNKCTL_ES 0x0080 /* Extended Synch */
|
||||
#define PCI_EXP_LNKCTL_CLKREQ_EN 0x100 /* Enable clkreq */
|
||||
#define PCI_EXP_LNKCTL_CLKREQ_EN 0x0100 /* Enable clkreq */
|
||||
#define PCI_EXP_LNKCTL_HAWD 0x0200 /* Hardware Autonomous Width Disable */
|
||||
#define PCI_EXP_LNKCTL_LBMIE 0x0400 /* Link Bandwidth Management Interrupt Enable */
|
||||
#define PCI_EXP_LNKCTL_LABIE 0x0800 /* Lnk Autonomous Bandwidth Interrupt Enable */
|
||||
#define PCI_EXP_LNKSTA 18 /* Link Status */
|
||||
#define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */
|
||||
#define PCI_EXP_LNKSTA_CLS_2_5GB 0x01 /* Current Link Speed 2.5GT/s */
|
||||
#define PCI_EXP_LNKSTA_CLS_5_0GB 0x02 /* Current Link Speed 5.0GT/s */
|
||||
#define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */
|
||||
#define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */
|
||||
#define PCI_EXP_LNKSTA_NLW 0x03f0 /* Nogotiated Link Width */
|
||||
#define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */
|
||||
#define PCI_EXP_LNKSTA_LT 0x0800 /* Link Training */
|
||||
|
|
@ -534,44 +534,49 @@
|
|||
#define PCI_EXP_SLTSTA_EIS 0x0080 /* Electromechanical Interlock Status */
|
||||
#define PCI_EXP_SLTSTA_DLLSC 0x0100 /* Data Link Layer State Changed */
|
||||
#define PCI_EXP_RTCTL 28 /* Root Control */
|
||||
#define PCI_EXP_RTCTL_SECEE 0x01 /* System Error on Correctable Error */
|
||||
#define PCI_EXP_RTCTL_SENFEE 0x02 /* System Error on Non-Fatal Error */
|
||||
#define PCI_EXP_RTCTL_SEFEE 0x04 /* System Error on Fatal Error */
|
||||
#define PCI_EXP_RTCTL_PMEIE 0x08 /* PME Interrupt Enable */
|
||||
#define PCI_EXP_RTCTL_CRSSVE 0x10 /* CRS Software Visibility Enable */
|
||||
#define PCI_EXP_RTCTL_SECEE 0x0001 /* System Error on Correctable Error */
|
||||
#define PCI_EXP_RTCTL_SENFEE 0x0002 /* System Error on Non-Fatal Error */
|
||||
#define PCI_EXP_RTCTL_SEFEE 0x0004 /* System Error on Fatal Error */
|
||||
#define PCI_EXP_RTCTL_PMEIE 0x0008 /* PME Interrupt Enable */
|
||||
#define PCI_EXP_RTCTL_CRSSVE 0x0010 /* CRS Software Visibility Enable */
|
||||
#define PCI_EXP_RTCAP 30 /* Root Capabilities */
|
||||
#define PCI_EXP_RTSTA 32 /* Root Status */
|
||||
#define PCI_EXP_RTSTA_PME 0x10000 /* PME status */
|
||||
#define PCI_EXP_RTSTA_PENDING 0x20000 /* PME pending */
|
||||
#define PCI_EXP_RTSTA_PME 0x00010000 /* PME status */
|
||||
#define PCI_EXP_RTSTA_PENDING 0x00020000 /* PME pending */
|
||||
/*
|
||||
* Note that the following PCI Express 'Capability Structure' registers
|
||||
* were introduced with 'Capability Version' 0x2 (v2). These registers
|
||||
* do not exist on devices with Capability Version 1. Use pci_pcie_cap2()
|
||||
* to use these fields safely.
|
||||
* The Device Capabilities 2, Device Status 2, Device Control 2,
|
||||
* Link Capabilities 2, Link Status 2, Link Control 2,
|
||||
* Slot Capabilities 2, Slot Status 2, and Slot Control 2 registers
|
||||
* are only present on devices with PCIe Capability version 2.
|
||||
* Use pcie_capability_read_word() and similar interfaces to use them
|
||||
* safely.
|
||||
*/
|
||||
#define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */
|
||||
#define PCI_EXP_DEVCAP2_ARI 0x20 /* Alternative Routing-ID */
|
||||
#define PCI_EXP_DEVCAP2_LTR 0x800 /* Latency tolerance reporting */
|
||||
#define PCI_EXP_OBFF_MASK 0xc0000 /* OBFF support mechanism */
|
||||
#define PCI_EXP_OBFF_MSG 0x40000 /* New message signaling */
|
||||
#define PCI_EXP_OBFF_WAKE 0x80000 /* Re-use WAKE# for OBFF */
|
||||
#define PCI_EXP_DEVCAP2_ARI 0x00000020 /* Alternative Routing-ID */
|
||||
#define PCI_EXP_DEVCAP2_LTR 0x00000800 /* Latency tolerance reporting */
|
||||
#define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c0000 /* OBFF support mechanism */
|
||||
#define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 /* New message signaling */
|
||||
#define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 /* Re-use WAKE# for OBFF */
|
||||
#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
|
||||
#define PCI_EXP_DEVCTL2_ARI 0x20 /* Alternative Routing-ID */
|
||||
#define PCI_EXP_IDO_REQ_EN 0x100 /* ID-based ordering request enable */
|
||||
#define PCI_EXP_IDO_CMP_EN 0x200 /* ID-based ordering completion enable */
|
||||
#define PCI_EXP_LTR_EN 0x400 /* Latency tolerance reporting */
|
||||
#define PCI_EXP_OBFF_MSGA_EN 0x2000 /* OBFF enable with Message type A */
|
||||
#define PCI_EXP_OBFF_MSGB_EN 0x4000 /* OBFF enable with Message type B */
|
||||
#define PCI_EXP_OBFF_WAKE_EN 0x6000 /* OBFF using WAKE# signaling */
|
||||
#define PCI_EXP_DEVCTL2_ARI 0x20 /* Alternative Routing-ID */
|
||||
#define PCI_EXP_DEVCTL2_IDO_REQ_EN 0x0100 /* Allow IDO for requests */
|
||||
#define PCI_EXP_DEVCTL2_IDO_CMP_EN 0x0200 /* Allow IDO for completions */
|
||||
#define PCI_EXP_DEVCTL2_LTR_EN 0x0400 /* Enable LTR mechanism */
|
||||
#define PCI_EXP_DEVCTL2_OBFF_MSGA_EN 0x2000 /* Enable OBFF Message type A */
|
||||
#define PCI_EXP_DEVCTL2_OBFF_MSGB_EN 0x4000 /* Enable OBFF Message type B */
|
||||
#define PCI_EXP_DEVCTL2_OBFF_WAKE_EN 0x6000 /* OBFF using WAKE# signaling */
|
||||
#define PCI_EXP_DEVSTA2 42 /* Device Status 2 */
|
||||
#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 44 /* v2 endpoints end here */
|
||||
#define PCI_EXP_LNKCAP2 44 /* Link Capability 2 */
|
||||
#define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */
|
||||
#define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */
|
||||
#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */
|
||||
#define PCI_EXP_LNKCAP2_CROSSLINK 0x100 /* Crosslink supported */
|
||||
#define PCI_EXP_LNKCAP2 44 /* Link Capabilities 2 */
|
||||
#define PCI_EXP_LNKCAP2_SLS_2_5GB 0x00000002 /* Supported Speed 2.5GT/s */
|
||||
#define PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004 /* Supported Speed 5.0GT/s */
|
||||
#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008 /* Supported Speed 8.0GT/s */
|
||||
#define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 /* Crosslink supported */
|
||||
#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
|
||||
#define PCI_EXP_LNKSTA2 50 /* Link Status 2 */
|
||||
#define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */
|
||||
#define PCI_EXP_SLTCTL2 56 /* Slot Control 2 */
|
||||
#define PCI_EXP_SLTSTA2 58 /* Slot Status 2 */
|
||||
|
||||
/* Extended Capabilities (PCI-X 2.0 and Express) */
|
||||
#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff)
|
||||
|
|
|
|||
Loading…
Reference in New Issue