carl9170: import 1.9.9 firmware headers
Import new headers from my firmware branch: <https://github.com/chunkeey/carl9170fw> Signed-off-by: Christian Lamparter <chunkeey@googlemail.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
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@ -56,6 +56,7 @@ enum carl9170_cmd_oids {
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CARL9170_CMD_RX_FILTER = 0x07,
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CARL9170_CMD_RX_FILTER = 0x07,
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CARL9170_CMD_WOL = 0x08,
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CARL9170_CMD_WOL = 0x08,
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CARL9170_CMD_TALLY = 0x09,
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CARL9170_CMD_TALLY = 0x09,
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CARL9170_CMD_WREGB = 0x0a,
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/* CAM */
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/* CAM */
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CARL9170_CMD_EKEY = 0x10,
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CARL9170_CMD_EKEY = 0x10,
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@ -123,6 +124,12 @@ struct carl9170_write_reg {
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} regs[0] __packed;
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} regs[0] __packed;
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} __packed;
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} __packed;
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struct carl9170_write_reg_byte {
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__le32 addr;
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__le32 count;
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u8 val[0];
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} __packed;
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#define CARL9170FW_PHY_HT_ENABLE 0x4
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#define CARL9170FW_PHY_HT_ENABLE 0x4
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#define CARL9170FW_PHY_HT_DYN2040 0x8
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#define CARL9170FW_PHY_HT_DYN2040 0x8
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#define CARL9170FW_PHY_HT_EXT_CHAN_OFF 0x3
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#define CARL9170FW_PHY_HT_EXT_CHAN_OFF 0x3
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@ -226,6 +233,7 @@ struct carl9170_cmd {
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struct carl9170_u32_list echo;
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struct carl9170_u32_list echo;
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struct carl9170_reg_list rreg;
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struct carl9170_reg_list rreg;
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struct carl9170_write_reg wreg;
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struct carl9170_write_reg wreg;
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struct carl9170_write_reg_byte wregb;
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struct carl9170_rf_init rf_init;
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struct carl9170_rf_init rf_init;
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struct carl9170_psm psm;
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struct carl9170_psm psm;
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struct carl9170_wol_cmd wol;
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struct carl9170_wol_cmd wol;
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@ -81,6 +81,12 @@ enum carl9170fw_feature_list {
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/* Firmware will pass BA when BARs are queued */
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/* Firmware will pass BA when BARs are queued */
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CARL9170FW_RX_BA_FILTER,
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CARL9170FW_RX_BA_FILTER,
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/* Firmware has support to write a byte at a time */
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CARL9170FW_HAS_WREGB_CMD,
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/* Pattern generator */
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CARL9170FW_PATTERN_GENERATOR,
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/* KEEP LAST */
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/* KEEP LAST */
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__CARL9170FW_FEATURE_NUM
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__CARL9170FW_FEATURE_NUM
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};
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};
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@ -453,9 +453,74 @@
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#define AR9170_MC_REG_BASE 0x1d1000
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#define AR9170_MC_REG_BASE 0x1d1000
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#define AR9170_MC_REG_FLASH_WAIT_STATE (AR9170_MC_REG_BASE + 0x000)
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#define AR9170_MC_REG_FLASH_WAIT_STATE (AR9170_MC_REG_BASE + 0x000)
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#define AR9170_MC_REG_SEEPROM_WP0 (AR9170_MC_REG_BASE + 0x400)
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#define AR9170_MC_REG_SEEPROM_WP1 (AR9170_MC_REG_BASE + 0x404)
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#define AR9170_SPI_REG_BASE (AR9170_MC_REG_BASE + 0x200)
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#define AR9170_MC_REG_SEEPROM_WP2 (AR9170_MC_REG_BASE + 0x408)
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#define AR9170_SPI_REG_CONTROL0 (AR9170_SPI_REG_BASE + 0x000)
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#define AR9170_SPI_CONTROL0_BUSY BIT(0)
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#define AR9170_SPI_CONTROL0_CMD_GO BIT(1)
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#define AR9170_SPI_CONTROL0_PAGE_WR BIT(2)
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#define AR9170_SPI_CONTROL0_SEQ_RD BIT(3)
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#define AR9170_SPI_CONTROL0_CMD_ABORT BIT(4)
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#define AR9170_SPI_CONTROL0_CMD_LEN_S 8
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#define AR9170_SPI_CONTROL0_CMD_LEN 0x00000f00
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#define AR9170_SPI_CONTROL0_RD_LEN_S 12
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#define AR9170_SPI_CONTROL0_RD_LEN 0x00007000
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#define AR9170_SPI_REG_CONTROL1 (AR9170_SPI_REG_BASE + 0x004)
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#define AR9170_SPI_CONTROL1_SCK_RATE BIT(0)
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#define AR9170_SPI_CONTROL1_DRIVE_SDO BIT(1)
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#define AR9170_SPI_CONTROL1_MODE_SEL_S 2
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#define AR9170_SPI_CONTROL1_MODE_SEL 0x000000c0
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#define AR9170_SPI_CONTROL1_WRITE_PROTECT BIT(4)
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#define AR9170_SPI_REG_COMMAND_PORT0 (AR9170_SPI_REG_BASE + 0x008)
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#define AR9170_SPI_COMMAND_PORT0_CMD0_S 0
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#define AR9170_SPI_COMMAND_PORT0_CMD0 0x000000ff
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#define AR9170_SPI_COMMAND_PORT0_CMD1_S 8
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#define AR9170_SPI_COMMAND_PORT0_CMD1 0x0000ff00
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#define AR9170_SPI_COMMAND_PORT0_CMD2_S 16
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#define AR9170_SPI_COMMAND_PORT0_CMD2 0x00ff0000
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#define AR9170_SPI_COMMAND_PORT0_CMD3_S 24
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#define AR9170_SPI_COMMAND_PORT0_CMD3 0xff000000
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#define AR9170_SPI_REG_COMMAND_PORT1 (AR9170_SPI_REG_BASE + 0x00C)
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#define AR9170_SPI_COMMAND_PORT1_CMD4_S 0
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#define AR9170_SPI_COMMAND_PORT1_CMD4 0x000000ff
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#define AR9170_SPI_COMMAND_PORT1_CMD5_S 8
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#define AR9170_SPI_COMMAND_PORT1_CMD5 0x0000ff00
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#define AR9170_SPI_COMMAND_PORT1_CMD6_S 16
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#define AR9170_SPI_COMMAND_PORT1_CMD6 0x00ff0000
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#define AR9170_SPI_COMMAND_PORT1_CMD7_S 24
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#define AR9170_SPI_COMMAND_PORT1_CMD7 0xff000000
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#define AR9170_SPI_REG_DATA_PORT (AR9170_SPI_REG_BASE + 0x010)
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#define AR9170_SPI_REG_PAGE_WRITE_LEN (AR9170_SPI_REG_BASE + 0x014)
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#define AR9170_EEPROM_REG_BASE (AR9170_MC_REG_BASE + 0x400)
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#define AR9170_EEPROM_REG_WP_MAGIC1 (AR9170_EEPROM_REG_BASE + 0x000)
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#define AR9170_EEPROM_WP_MAGIC1 0x12345678
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#define AR9170_EEPROM_REG_WP_MAGIC2 (AR9170_EEPROM_REG_BASE + 0x004)
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#define AR9170_EEPROM_WP_MAGIC2 0x55aa00ff
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#define AR9170_EEPROM_REG_WP_MAGIC3 (AR9170_EEPROM_REG_BASE + 0x008)
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#define AR9170_EEPROM_WP_MAGIC3 0x13579ace
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#define AR9170_EEPROM_REG_CLOCK_DIV (AR9170_EEPROM_REG_BASE + 0x00C)
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#define AR9170_EEPROM_CLOCK_DIV_FAC_S 0
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#define AR9170_EEPROM_CLOCK_DIV_FAC 0x000001ff
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#define AR9170_EEPROM_CLOCK_DIV_FAC_39KHZ 0xff
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#define AR9170_EEPROM_CLOCK_DIV_FAC_78KHZ 0x7f
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#define AR9170_EEPROM_CLOCK_DIV_FAC_312KHZ 0x1f
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#define AR9170_EEPROM_CLOCK_DIV_FAC_10MHZ 0x0
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#define AR9170_EEPROM_CLOCK_DIV_SOFT_RST BIT(9)
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#define AR9170_EEPROM_REG_MODE (AR9170_EEPROM_REG_BASE + 0x010)
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#define AR9170_EEPROM_MODE_EEPROM_SIZE_16K_PLUS BIT(31)
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#define AR9170_EEPROM_REG_WRITE_PROTECT (AR9170_EEPROM_REG_BASE + 0x014)
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#define AR9170_EEPROM_WRITE_PROTECT_WP_STATUS BIT(0)
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#define AR9170_EEPROM_WRITE_PROTECT_WP_SET BIT(8)
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/* Interrupt Controller */
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/* Interrupt Controller */
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#define AR9170_MAX_INT_SRC 9
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#define AR9170_MAX_INT_SRC 9
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@ -589,11 +654,13 @@
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#define AR9170_USB_REG_EP10_MAP (AR9170_USB_REG_BASE + 0x039)
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#define AR9170_USB_REG_EP10_MAP (AR9170_USB_REG_BASE + 0x039)
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#define AR9170_USB_REG_EP_IN_MAX_SIZE_HIGH (AR9170_USB_REG_BASE + 0x03f)
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#define AR9170_USB_REG_EP_IN_MAX_SIZE_HIGH (AR9170_USB_REG_BASE + 0x03f)
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#define AR9170_USB_EP_IN_STALL 0x8
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#define AR9170_USB_EP_IN_TOGGLE 0x10
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#define AR9170_USB_EP_IN_TOGGLE 0x10
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#define AR9170_USB_REG_EP_IN_MAX_SIZE_LOW (AR9170_USB_REG_BASE + 0x03e)
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#define AR9170_USB_REG_EP_IN_MAX_SIZE_LOW (AR9170_USB_REG_BASE + 0x03e)
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#define AR9170_USB_REG_EP_OUT_MAX_SIZE_HIGH (AR9170_USB_REG_BASE + 0x05f)
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#define AR9170_USB_REG_EP_OUT_MAX_SIZE_HIGH (AR9170_USB_REG_BASE + 0x05f)
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#define AR9170_USB_EP_OUT_STALL 0x8
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#define AR9170_USB_EP_OUT_TOGGLE 0x10
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#define AR9170_USB_EP_OUT_TOGGLE 0x10
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#define AR9170_USB_REG_EP_OUT_MAX_SIZE_LOW (AR9170_USB_REG_BASE + 0x05e)
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#define AR9170_USB_REG_EP_OUT_MAX_SIZE_LOW (AR9170_USB_REG_BASE + 0x05e)
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@ -1,7 +1,7 @@
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#ifndef __CARL9170_SHARED_VERSION_H
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#ifndef __CARL9170_SHARED_VERSION_H
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#define __CARL9170_SHARED_VERSION_H
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#define __CARL9170_SHARED_VERSION_H
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#define CARL9170FW_VERSION_YEAR 12
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#define CARL9170FW_VERSION_YEAR 16
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#define CARL9170FW_VERSION_MONTH 12
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#define CARL9170FW_VERSION_MONTH 2
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#define CARL9170FW_VERSION_DAY 15
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#define CARL9170FW_VERSION_DAY 15
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#define CARL9170FW_VERSION_GIT "1.9.7"
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#define CARL9170FW_VERSION_GIT "1.9.9"
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#endif /* __CARL9170_SHARED_VERSION_H */
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#endif /* __CARL9170_SHARED_VERSION_H */
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